JPS6178170A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the parasitic resistance of a gate electrode, and to increase the withstanding voltage of a Schottky gate by a method wherein a high-concentration semiconductor layer is formed to a semi-insulating substrate, a first insulating film is shaped onto the whole surface, a recessed section is formed at the central section of the high-concentration semiconductor layer through etching, ions are implanted to the high-concentration semiconductor layer in the lower section of the recessed section, a second insulating layer is shaped onto the whole surface and changed into a gate insulating film through activation and etching, and the gate electrode is formed in the recessed section. CONSTITUTION:The ions of an impurity are implanted while a semi-insulating GaAs substrate 1 is formed in a (100) face and a photo-resist 2 is used as a mask to shape an N<+> type high-concentration semiconductor layer 3. A first insulating film 4 is formed onto the whole surface, the first insulating film 4 is bored, and a recessed section 6 is processed to the N<+> type high-concentration semiconductor layer 3 through etching. Impurity ions are implanted through the recessed section to shape an N type channel layer 7, a second insulating film 8 is formed onto the whole surface and activated and annealed, a gate insulating film 9 is shaped to the recessed section 6 and the side wall section of the first insulating film 4 through etching, and a metal is evaporated and a gate electrode 11 is shaped through photoetching.

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to semiconductor manufacturing equipment, and more particularly to a compound semiconductor MESFET formed on a semi-insulating substrate. [Background Art] A variety of GaΔs MESFETs have been developed, taking advantage of the fact that the substrate is semi-insulating and the high speed performance thereof. By the way, for the purpose of reducing parasitic resistance, QaAs technology is used in which ions are implanted in a self-aligned manner using the gate metal as a mask.
In the FET, the lateral spread of the N" type high concentration semiconductor layer has been a problem. Due to the lateral spread of the N4" type high concentration semiconductor layer, some of the ions are also below the gate electrode. Because of the injection, N1 of the source and drain
This method has drawbacks such as short-circuiting between the high-concentration semiconductor region and the gate electrode, or poor breakdown voltage. Furthermore, since annealing was performed after forming the gate metal, it was necessary to use a heat-resistant gate metal. Furthermore, the channel layer of the conventional GaAs MESFET is located in the high concentration profile portion of the drain/source region, and in order to obtain stable characteristics, it is necessary to improve manufacturing controllability. In addition, the manufacturing method of MESFET is shown, for example in Electronic Materials, January 1983 issue, pages 43-50. [Object of the Invention] An object of the present invention is to manufacture a semiconductor device that can form a gate electrode in a self-aligned manner to reduce its parasitic resistance, improve the breakdown voltage of a Schottky gate, and obtain stable characteristics. The present invention provides a method. The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings. [Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows. That is, an N++ high concentration semiconductor layer is formed on a semi-insulating substrate by ion implantation, a first insulating film is formed on the entire surface, and then a recess is formed in the center of the N1 type high concentration semiconductor layer by etching. next. The N++ high concentration semiconductor layer remaining below this recess is further subjected to E/D type adjustment ion implantation to form an N type channel layer. N like this
++ The high concentration semiconductor layer and the N-type channel layer can also be formed using still another process. That is, first, an N4'' type high concentration semiconductor layer for forming source and drain regions is ion-implanted into a semi-insulating substrate.
After forming an insulating film over the entire surface, a recess is formed between the two N1 type high concentration semiconductor layers by etching. Next, ions are implanted into the substrate below this recess to form an N-type channel layer. It was formed like this. Recess, source/drain N4''
A second layer is further formed on the entire surface of the type high concentration semiconductor layer and the N type channel layer.
An insulating layer is formed and activation annealing is performed. The second insulating layer is then etched to form a gate insulating film. This gate insulating film. It will be formed in the recess and the sidewall of the first insulating film. Thereafter, a gate electrode is formed in the recess, and source and drain electrodes are further formed to complete the semiconductor device. According to the present invention, the gate electrode is formed in a self-aligned manner, and the distance between the gate and the source/drain can be controlled by the thickness of the gate insulating film, so that parasitic resistance can be reduced. Further, by interposing the gate insulating film, the breakdown voltage of the Schottky gate can be improved. Furthermore, the profile peak portion of the N4'' type high concentration semiconductor layer is located above the N type channel layer, allowing current to flow through the internal layers of the semiconductor device, thereby achieving stable characteristics. [Example] The present invention will be described below. GaAsMESF semiconductor device manufacturing method
An example applied to ET will be described using FIGS. 1 to 11. First, embodiments of the invention shown in FIGS. 1 to 7I2I will be described. In FIG. 1, reference numeral 1 indicates a semi-insulating GaAs substrate. Using photoresist 2 as a mask, impurity ions such as Si are implanted into the GaAs on one main surface of this substrate, mainly the (100) plane, to form an N1 type. A high concentration semiconductor polishing layer 3 is formed. Next, in FIG. 2, S i02 , S i3 N
A first insulating film 4 such as No. 4 is formed on the entire surface. Then, using the photoresist 5 as a mask, the first RW4 in the center of the N1 type high concentration semiconductor layer 3 is opened as shown in the figure, and then the first
Using the insulating film 4 as a mask, the concave portion 6 of the N+ type bulky semiconductor layer 3 is etched. In this state, the

[7] Impurity ions such as Si are implanted to adjust the concentration profile to E/D. Therefore,
The area between the bottom surface of the recess 6 and the substrate 1 is as follows. This becomes an N-type channel layer 7. In this way, the recess 6 and
N-type channel layer 7 below recess 6 and N-type channel layer 7 on both sides thereof.
Type 1 high concentration semiconductor layers 3, 3 are formed. That is,
In this embodiment, the N type channel layer 7 is formed by re-implanting ions for E/D adjustment into the low concentration profile portion of the N+ type bulky doped semiconductor layer 3. Next, in FIG. 3, a second insulator I! of, for example, Si]N4 is applied to the entire surface. ;48 is formed. After this, activation annealing for ion implantation is performed.As will be described later, since the gate electrode is formed after the annealing, there is no need to use a high melting point metal even though the gate is formed by self-alignment, and various methods are used to form a Schottky junction. metals can be used. When the second insulating film 11j8 formed in FIG. (FIG. 4), it can be seen that the gate length can be controlled by the thickness of the gate insulation@9 through this process. Furthermore, in FIG. 5, a metal 10 forming a Schottky junction with GaAs is deposited, and a sixth layer is formed by photo-etching.
A gate electrode 11 is formed as shown in the figure. Incidentally, it is of course possible to use a beam lift-off method in this gate electrode processing step. Next, in FIG. 6, an insulating film 12 of 5i02 etc.
After depositing the source/drain electrodes 13.1, source/drain contact holes are opened and the source/drain electrodes 13.1 are formed using a lift-off method.
Form 4 and complete. Next, embodiments of the present invention shown in FIGS. 8 to 11 will be described. In FIG. 8, reference numeral 100 is a GaAs substrate as in FIG. The N++ high concentration semiconductor layers 103, 103 formed here will become source and drain regions, respectively, using the photoresist 102 as a mask. Namely. A photoresist 10 is applied to the region where the N-type channel layer is to be formed.
2, ion implantation of Si or the like is not performed. Next, in FIG. 9, 5i02. The first of Si3N* etc.
An insulating film 104 is formed over the entire surface. After that, using the photoresist 105 as a mask, the N" type high concentration semiconductor N10 is
An opening is made in the first insulating film 104 in a region sandwiched between 3 and 103 as shown in the figure. Then, using the first insulating film 104 as a mask, a recess 106 is formed in the substrate 101 by etching. In this state, impurity ions such as Si are implanted into the substrate 101 through the recess 106 to form an N-type channel layer 107. In this case, the ion implantation is directly implanted into the substrate 101-, so E/D controllability is good. In addition, in the ion implantation to form the N'''' type high concentration semiconductor layers 103, 103, since N type ions are deeply implanted, the impurity concentration on the surface of the source/drain region forming the ohmic ML is low. be. In this case, it is possible to make the alloy such as Δu Ge/Ni/ΔU of the ohmic electrode relatively deep, or to optimize the concentration profile by matching during ion implantation of the N-type channel NJ107. Further, in the step shown in FIG. 9, a part of the h++ high concentration semiconductor layer 103° 103 may sink into the lower part of the recess 106 due to the mask alignment margin. However, the first
The thickness of the gate insulating film explained in FIG. 0 prevents a short circuit with the gate electrode. In FIG. 10, the entire surface is covered with a second layer of Si3N4, etc.
An insulating film 108 is formed. after this. The steps of performing activation annealing for ion implantation, etching the second insulating film 108 to form a gate insulating film, and subsequent steps are the same as those described in FIGS. 4 to 7. The explanation will be omitted. FIG. 11 is a cross-sectional view showing the completed state, with reference numeral 10.
9 is a gate insulating film, and 111 is a gate i! ! The poles, reference numeral 112, are absolute aWA such as 5i02, reference numeral 113 is a source electrode, and reference numeral ]-14 is a drain electrode. [Effects] (1) The gate electrode is formed in a self-aligned manner, and the distance between the gate electrode and the source/drain can be controlled by controlling the thickness of the gate insulating film. Therefore, it is possible to improve the parasitic resistance between the gate and the source and the breakdown voltage of the Schottky barrier. In addition, the peak of the N1-type heavily doped semiconductor layer is above the N-type channel layer, resulting in a large gm and stable characteristics. (2) Since the gate electrode is formed after annealing, it is possible to use a gate metal with low heat resistance. Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. [Field of Application] The present invention is an ME of a compound semiconductor formed on a semi-insulating substrate.
Applicable to SFET, especially MESFE using GaAs
It is suitable for application to logic circuits based on T, LSIs such as SRAMs.

[Brief explanation of drawings]

1 to 7 are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 8 to 11 are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. 1.101...Semi-insulating substrate, 2,102,5°10
5... Photoresist, 3,103... N+ type bulky high concentration semiconductor layer 4,104... First insulating film. 6.106... Concave portion, 7.1.07... N-type channel layer, 8,108... Second insulating layer, 9,109...
- Gate insulating film, 11, 111... Gate insulating film. 12.112... Insulating layer, 13,113... Source electrode, 14,114... Drain electrode.

Claims (1)

[Claims] 1. After forming a highly concentrated semiconductor layer on one main surface of a semi-insulating substrate, a first insulating film is formed on the entire surface, and the central part of this highly concentrated semiconductor layer is covered with the first insulating film. A recess is formed by etching the film as a mask, and ions are implanted through the recess to form a channel layer of the same conductivity type as the high concentration semiconductor layer between the bottom of the recess and the substrate, and further, A second insulating film is formed on the entire surface and annealed, and etched to leave the second insulating film as a gate insulating film in the recess and the sidewall of the first insulating film, and then a gate electrode is formed in the recess. A method for manufacturing a semiconductor device, characterized in that: 2. After forming high-concentration semiconductor layers forming source and drain regions on one main surface of a semi-insulating substrate, a first insulating film is formed on the entire surface, and the region sandwiched between these high-concentration semiconductor layers is Etching is performed using the first insulating film as a mask to form a recess, and ion implantation is performed through this recess.
A channel layer of the same conductivity type as the high-concentration semiconductor layer is formed on a part of the substrate in contact with the bottom surface of the recess, and a second insulating film is further formed on the entire surface and annealed, thereby forming the recess and the first insulating film. A method of manufacturing a semiconductor device, comprising: etching the second insulating film to leave it as a gate insulating film on a side wall of the film, and then forming a gate electrode in the recess.