JPH0644605B2 - Method of manufacturing high breakdown voltage MOS field effect semiconductor device - Google Patents
Method of manufacturing high breakdown voltage MOS field effect semiconductor deviceInfo
- Publication number
- JPH0644605B2 JPH0644605B2 JP60007777A JP777785A JPH0644605B2 JP H0644605 B2 JPH0644605 B2 JP H0644605B2 JP 60007777 A JP60007777 A JP 60007777A JP 777785 A JP777785 A JP 777785A JP H0644605 B2 JPH0644605 B2 JP H0644605B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- breakdown voltage
- field effect
- voltage mos
- mos field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015556 catabolic process Effects 0.000 title claims description 37
- 230000005669 field effect Effects 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000012535 impurity Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 29
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は、高耐圧ＭＯＳ電界効果トランジスタとそれを
駆動する為の通常の低耐圧ＭＯＳ電界効果トランジスタ
で構成されたロジック回路が同一半導体基板上に形成さ
れた半導体装置（以下高耐圧ＭＯＳ・ＩＣと略す）の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention has a logic circuit composed of a high breakdown voltage MOS field effect transistor and an ordinary low breakdown voltage MOS field effect transistor for driving the same on the same semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device (hereinafter abbreviated as high breakdown voltage MOS IC) formed in the above.
＜従来の技術＞ 従来から知られている高及び低耐圧ＭＯＳ・ＦＥＴが同
一基板に形成された高耐圧ＭＯＳ・ＩＣの１例の断面図
を第３図に示す。第３図に於いて１はＰ型基板で、該基
板１にN+ソース領域２及び２′及びN+ドレイン領域３及
び３′が夫々形成されているが、高耐圧ＭＯＳ・ＦＥＴ
側のソース領域２の周囲には、自己整合プロセスによっ
てゲート・チャンネルのためのP+領域４が設けられ、ま
たドレイン領域３に接続した同一導電型の高抵抗層５が
設けられている。<Prior Art> FIG. 3 shows a cross-sectional view of an example of a conventionally known high breakdown voltage MOS.IC in which high and low breakdown voltage MOS.FETs are formed on the same substrate. In FIG. 3, reference numeral 1 is a P-type substrate on which N + source regions 2 and 2'and N + drain regions 3 and 3'are respectively formed.
Around the source region 2 on the side, a P + region 4 for the gate channel is provided by a self-alignment process, and a high resistance layer 5 of the same conductivity type connected to the drain region 3 is provided.
上記のような高耐圧ＭＯＳ・ＩＣに於いて基板１は高耐
圧ＭＯＳ・ＦＥＴのドレインと基板間の接合耐圧を高く
する為に低不純物濃度のものを使う必要がある。その場
合高抵抗層５とソース領域２の間でパンチ・スルー現象
による耐圧低下を伴うことがあり、これを防ぐ為にソー
ス領域２を囲むようにその周囲に自己整合プロセスによ
って高不純物濃度層４を設けている。In the above high withstand voltage MOS / IC, the substrate 1 needs to have a low impurity concentration in order to increase the junction withstand voltage between the drain of the high withstand voltage MOS / FET and the substrate. In that case, the breakdown voltage may be reduced due to the punch-through phenomenon between the high resistance layer 5 and the source region 2, and in order to prevent this, the high impurity concentration layer 4 is formed around the source region 2 by a self-alignment process so as to surround the source region 2. Is provided.
＜発明が解決しようとする問題点＞ しかし上記のように自己整合プロセスで作られた構造に
於いては、閾値電圧値（VTH）の制御が困難であるとい
う宿命的な欠点を持っている。一方、高抵抗層５の不純
物濃度は高耐圧ＭＯＳ・ＦＥＴのオン抵抗（RON）及び
耐圧の特性を決める上で極めて重要なファクターであ
り、その不純物濃度が高いとオン抵抗（RON）は小さく
なるものの高抵抗層５のチャンネル端での空乏層の拡が
りが充分でなく、高い耐圧が得られない。逆にその不純
物濃度が小さいとオン抵抗（RON）が大きくなりすぎる
とともに、高抵抗層５とドレイン領域３の境界付近の電
界が高まり耐圧も低下するという欠点がある。高耐圧Ｍ
ＯＳ・ＦＥＴのオン抵抗を小さくし、且つ高耐圧を得る
よう改善を図るには、高抵抗層５はドレイン領域３より
チャンネル領域に向けて徐々に濃度が小さくなるように
横方向に濃度分布を持たせる必要がある。その為に第４
図(c)〜(d)に示すように、基板１に対してマスク２５の
位置を順次ずらせて高抵抗層５の領域に複数回のイオン
注入を施し、階段状の濃度分布５，５′，５″を形成す
る方法が考案されている。しかしこの場合も工程数が増
えるという欠点がある。<Problems to be solved by the invention> However, the structure formed by the self-alignment process as described above has a fatal drawback that it is difficult to control the threshold voltage value (V TH ). . On the other hand, the impurity concentration of the high resistance layer 5 is a very important factor in determining the on-resistance (R ON ) and withstand voltage characteristics of the high breakdown voltage MOS • FET. If the impurity concentration is high, the on-resistance (R ON ) Although it becomes smaller, the depletion layer does not spread sufficiently at the channel end of the high resistance layer 5, and a high breakdown voltage cannot be obtained. On the other hand, if the impurity concentration is low, the on-resistance (R ON ) becomes too large, and the electric field near the boundary between the high resistance layer 5 and the drain region 3 increases and the breakdown voltage decreases. High breakdown voltage M
In order to reduce the on-resistance of the OS-FET and to obtain a high breakdown voltage, the high resistance layer 5 has a lateral concentration distribution in which the concentration gradually decreases from the drain region 3 toward the channel region. Need to have. Therefore, the fourth
As shown in FIGS. (C) to (d), the position of the mask 25 is sequentially shifted with respect to the substrate 1, ion implantation is performed a plurality of times in the region of the high resistance layer 5, and a stepwise concentration distribution 5, 5 ′ is obtained. , 5 "has been devised. However, this method also has the drawback of increasing the number of steps.
＜問題点を解決するための手段＞ 本発明は上記のような欠点をなくし、閾値電圧値の制御
を容易にし、且つ工程数を増やすことなく高抵抗層５の
横方向の不純物濃度を２段階にし、オン抵抗（RON）の
低下と耐圧特性の改善を図った高耐圧ＭＯＳ電界効果半
導体装置の製造方法を提供するものである。すなわち本
発明の半導体装置の製造方法は、半導体基板上のソース
部を囲む領域に基板と同じ導電型で、基板より高濃度の
不純物拡散領域とし、ドレイン部・チャネル間の領域に
ドレイン部と同じ導電型で、ドレイン部より低濃度の不
純物拡散領域とを設けたオフセット構造を有する高耐圧
ＭＯＳ電界効果トランジスタと該高耐圧ＭＯＳ電界効果
トランジスタより低い耐圧特性をもつ低耐圧ＭＯＳ電界
効果トランジスタとを同一半導体基板に形成してなる、
高耐圧ＭＯＳ電界効果半導体装置の製造方法において、
前記ドレイン部と同じ導電型で、ドレイン部より濃度の
低い不純物を注入して、前記高耐圧ＭＯＳ電界効果トラ
ンジスタのドレイン部・チャネル間に高抵抗領域として
不純物拡散領域を形成する工程と、該工程後、前記基板
と同じ導電型を有し、前記工程に於いて注入した不純物
より低い濃度の不純物を前記高耐圧ＭＯＳ電界効果トラ
ンジスタのソース部を囲む領域及び前記高抵抗領域に於
けるソース部側の一部領域に注入して、ソース部を囲む
不純物拡散領域を形成すると同時に前記高抵抗領域を２
段階の不純物濃度を有する高抵抗領域に形成する工程と
を有することを特徴とする。<Means for Solving Problems> The present invention eliminates the above-mentioned drawbacks, facilitates control of the threshold voltage value, and sets the lateral impurity concentration of the high resistance layer 5 in two steps without increasing the number of steps. In addition, the present invention provides a method for manufacturing a high breakdown voltage MOS field effect semiconductor device in which the on-resistance (R ON ) is reduced and the breakdown voltage characteristics are improved. That is, according to the method of manufacturing a semiconductor device of the present invention, an impurity diffusion region having the same conductivity type as the substrate and a higher concentration than that of the substrate is formed in the region surrounding the source portion on the semiconductor substrate, and the same as the drain portion in the region between the drain portion and the channel. A high withstand voltage MOS field effect transistor having a conductivity type and an offset structure provided with an impurity diffusion region having a lower concentration than the drain portion and a low withstand voltage MOS field effect transistor having a withstand voltage characteristic lower than that of the high withstand voltage MOS field effect transistor are the same. Formed on a semiconductor substrate,
In a method of manufacturing a high breakdown voltage MOS field effect semiconductor device,
A step of implanting an impurity having the same conductivity type as that of the drain part and having a lower concentration than that of the drain part to form an impurity diffusion region as a high resistance region between the drain part and the channel of the high breakdown voltage MOS field effect transistor; After that, an impurity having the same conductivity type as that of the substrate and having a concentration lower than that of the impurities injected in the step is surrounded by the source part of the high breakdown voltage MOS field effect transistor and the source part side in the high resistance region. To form an impurity diffusion region surrounding the source portion and at the same time the high resistance region 2
A step of forming a high resistance region having a stepwise impurity concentration.
第１図は本発明の半導体構造を示す断面図で、基板左側
領域に高耐圧ＭＯＳ・ＦＥＴが、右側領域に低耐圧ＭＯ
Ｓ・ＦＥＴが形成されるものとする。FIG. 1 is a sectional view showing a semiconductor structure of the present invention, in which a high breakdown voltage MOS.FET is located in the left side region of the substrate and a low breakdown voltage MO is located in the right side region.
S-FET shall be formed.
１はＰ型基板で、該基板１にN+ソース領域２及びN+ドレ
イン領域３が夫々形成されているが、高耐圧ＭＯＳ・Ｆ
ＥＴのソース領域とロジック回路を構成する低耐圧ＭＯ
Ｓ電界効果トランジスタのドレイン領域・チャンネル領
域・ソース領域の全域の囲むようにその周囲にP+領域４
及び４′が設けられ、またドレイン領域３に接続した同
一導電型の高抵抗層５及びそれより不純物濃度の低い高
抵抗層領域５′が設けられている。高抵抗層５′は高抵
抗層領域５に上記P+領域４を重ね合わせて不純物を補償
することによって形成する。Reference numeral 1 denotes a P-type substrate on which an N + source region 2 and an N + drain region 3 are formed, respectively.
Low breakdown voltage MO that constitutes the source region of ET and the logic circuit
The P + region 4 surrounds the entire drain region, channel region, and source region of the S field effect transistor.
And 4 ', and a high resistance layer 5 of the same conductivity type connected to the drain region 3 and a high resistance layer region 5'having a lower impurity concentration than that. The high resistance layer 5'is formed by superposing the P + region 4 on the high resistance layer region 5 to compensate for impurities.
＜作用＞ このような製造方法を用いることによって、 (1) 高耐圧ＭＯＳ・ＦＥＴの耐圧を高くする為に低不
純物濃度基板を用いても、高抵抗層とソース領域２及び
低耐圧ＭＯＳ電界効果トランジスタのドレイン・ソース
間で発生するパンチ・スルー現象による耐圧の低下を防
ぐ。<Operation> By using such a manufacturing method, (1) even if a low impurity concentration substrate is used to increase the breakdown voltage of the high breakdown voltage MOS • FET, the high resistance layer, the source region 2 and the low breakdown voltage MOS field effect are obtained. Prevents the breakdown voltage from decreasing due to the punch-through phenomenon that occurs between the drain and source of a transistor.
(2) 高抵抗層の不純物濃度を２段階にし、チャンネル
領域に接する高抵抗層５′は濃度を低くしているため、
空乏層が充分拡がって高耐圧が得られるとともに、ドレ
イン領域側の高抵抗層５は比較的不純物濃度が高い為、
その境界近傍に於ける電界強度を緩和し且つオン抵抗
（ＲON）の低減を図る。(2) The impurity concentration of the high resistance layer is set to two levels, and the high resistance layer 5'contacting the channel region has a low concentration.
Since the depletion layer is sufficiently expanded to obtain a high breakdown voltage, and the high resistance layer 5 on the drain region side has a relatively high impurity concentration,
The electric field strength near the boundary is relaxed and the on-resistance (R ON ) is reduced.
(3) 第３図の従来構造による自己整合プロセスを用い
た場合よりも、耐パンチ・スルー現象に対して強くなる
為チャンネル長を更に縮めることができ、相互コンダク
タンスｇｍのアップを図れる こと等、高性能な高耐圧ＭＯＳ・ＩＣを、１工程数を増
すことなく、安定的に作製することができる。(3) The channel length can be further shortened and the mutual conductance gm can be increased because it is more resistant to the punch-through phenomenon than the case where the self-alignment process according to the conventional structure of FIG. 3 is used. A high-performance, high-voltage MOS / IC can be stably manufactured without increasing the number of steps.
＜実施例＞ 第２図(a)〜(g)を用いて本発明の実施例を説明する。<Example> An example of the present invention will be described with reference to Figs. 2 (a) to (g).
半導体基板１には低不純物濃度のＰ型基板を用いその表
面に薄い酸化膜１８を介して31P+イオンをレジスト１９
をマスクとしてイオン注入した後、拡散を行なって高抵
抗層５を形成する（第２図(a)）。A P-type substrate having a low impurity concentration is used as the semiconductor substrate 1, and 31 P + ions are applied to the surface of the semiconductor substrate 1 through a thin oxide film 18 to resist 19
After ion implantation using as a mask, diffusion is performed to form a high resistance layer 5 (FIG. 2 (a)).
次に上記拡散工程で成長した酸化膜を１度エッチングで
剥った後再び薄い酸化膜２０を成長させ、レジスト２０
をマスクにして11B+イオンをイオン注入して拡散を行な
い、P+領域４と４′及び高抵抗層５の領域に重ね合わせ
てイオン注入した領域５′を形成する（第２図(b)）。
この時領域５′はＰ型にならないように上記31P+イオン
注入量及び11B+イオン注入量を選ぶ必要がある。又上記
11B+イオンの注入量は閾値電圧が最終的に目標の値にな
るように選ぶのが閾値電圧値を調整する為のチャンネル
・ドーピング工程を省く上で好ましい。Next, the oxide film grown in the above diffusion process is stripped once by etching, and then a thin oxide film 20 is grown again to form the resist 20.
11 B + ions are ion-implanted and diffused by using as a mask to form the ion-implanted region 5 ′ which is superposed on the P + regions 4 and 4 ′ and the region of the high resistance layer 5 (FIG. 2 (b )).
At this time, it is necessary to select the amount of 31 P + ion implantation and the amount of 11 B + ion implantation so that the region 5 ′ does not become P-type. Also above
It is preferable to select the implantation amount of 11 B + ions so that the threshold voltage finally reaches a target value in order to omit the channel doping step for adjusting the threshold voltage value.
次に再び、レジスト２２を部分的に覆い、11B+イオン注
入をしてP+のフィールド・ドープ領域６を形成する（第
２図(c)）。Next, the resist 22 is partially covered again, and 11 B + ions are implanted to form the P + field doped region 6 (FIG. 2 (c)).
次に拡散によって成長した厚い酸化膜１０を写真食刻技
術を用いて窓開けし、薄い酸化膜２４を成長させた上で
レジスト２３を部分的に覆い、31P+をイオン注入してデ
ィプレッション型トランジスタ閾値電圧を調整する為31
P+イオンをイオン注入する（第２図(d)）。Then, a window is opened in the thick oxide film 10 grown by diffusion using a photo-etching technique, a thin oxide film 24 is grown, the resist 23 is partially covered, and 31 P + is ion-implanted to depletion type. To adjust the transistor threshold voltage 31
Ion implantation of P + ions (Fig. 2 (d)).
その後多結晶シリコンを気相成長法によりディポジショ
ンし、エッチングによってその不要部分を除去してゲー
ト電極９及び９′，フローティング導電体１４を形成す
る。更にリンを自己整合的に拡散又はイオン注入によっ
て基板内にドーピングしソース領域２及び２′，ドレイ
ン領域３及び３′を形成する（第２図(e)）。After that, polycrystalline silicon is deposited by a vapor phase growth method, and unnecessary portions thereof are removed by etching to form gate electrodes 9 and 9'and a floating conductor 14. Further, phosphorus is doped into the substrate in a self-aligning manner by diffusion or ion implantation to form source regions 2 and 2'and drain regions 3 and 3 '(Fig. 2 (e)).
次に気相成長法により厚い絶縁膜１１をディポジション
し、ドレイン・コンタクト部とソース・コンタクト部を
エッチングによって開口する。その後全面にＡｌ等の導
電体を蒸着又はスパッタ或いはその他の方法でディポジ
ションし、その不要な部分を除去して、ソース電極８及
び８８′，ドレイン電極７及び７′，フローティング導
電体１４′を構成する（第２図(f)）。Next, the thick insulating film 11 is deposited by the vapor phase epitaxy method, and the drain contact portion and the source contact portion are opened by etching. After that, a conductor such as Al is deposited on the entire surface by vapor deposition, sputtering or other method, and the unnecessary portions are removed to form the source electrodes 8 and 88 ', the drain electrodes 7 and 7', and the floating conductor 14 '. Configure (Fig. 2 (f)).
更に気相成長法により厚い絶縁膜１２をディポジション
し、高耐圧ＭＯＳ・ＦＥＴのドレイン電極部，ソース電
極部等にスルー・ホールを開口した後再びＡｌ等の導電
体を全面にディポジションし、不要な部分を除去してソ
ース電極より延長したフィールド・プレート８″及びド
レイン電極より延展したフィールド・プレート７″又ロ
ジック回路を電位的に遮蔽するシールド・プレート１７
を構成する。最後に保護膜１３を形成して当高耐圧ＭＯ
Ｓ・ＩＣのプロセスは完了する（第２図(g)）。Further, a thick insulating film 12 is deposited by the vapor phase growth method, a through hole is opened in the drain electrode portion, source electrode portion, etc. of the high breakdown voltage MOS • FET, and then a conductor such as Al is deposited again on the entire surface. A field plate 8 "extending from the source electrode by removing unnecessary portions, a field plate 7" extending from the drain electrode, and a shield plate 17 for electrically blocking the logic circuit.
Make up. Finally, a protective film 13 is formed to form the high breakdown voltage MO.
The SIC process is completed (Fig. 2 (g)).
本発明の他の実施例として例えば厚い酸化膜１０を形成
する上に於いて選択酸化法を採用してもよいし又気相成
長法による絶縁膜を用いてもよい。本発明は主にシリコ
ン基板内の不純物のドーピングの構成にあり、高耐圧Ｍ
ＯＳ・ＦＥＴ、低耐圧ＭＯＳ電界効果トランジスタの素
子構造は本実施例に限られるものではなく、その他の構
造のものに於いても採用できることは言うまでもない。As another embodiment of the present invention, for example, in forming the thick oxide film 10, a selective oxidation method may be adopted, or an insulating film formed by a vapor phase growth method may be used. The present invention mainly consists in doping impurities in a silicon substrate, and has a high breakdown voltage M.
It goes without saying that the element structure of the OS.FET and the low breakdown voltage MOS field effect transistor is not limited to this embodiment, and can be adopted in other structures.
又更に高抵抗層５を形成する工程と同じ工程でＰ−チャ
ンネル低耐圧電界効果トランジスタを構成する為のＮ
wellを形成し、ロジック回路をＣ・ＭＯＳ（相補形ＭＯ
Ｓ）構成にすることもでき、ロジック回路の低消費電力
化を図ることも可能である。Further, in the same step as the step of forming the high resistance layer 5, N for forming the P-channel low breakdown voltage field effect transistor is formed.
The well is formed and the logic circuit is composed of C-MOS (complementary MO
It is also possible to adopt the S) configuration and to reduce the power consumption of the logic circuit.
＜発明の効果＞ 以上のように本発明によればこれまでに述べてきたよう
に特別工程数を増すことなく、 ＩＣを構成する各々のトランジスタの閾値電圧の制
御が容易になること 高耐圧ＭＯＳ・ＦＥＴの耐圧特性を改善しオン抵抗
（RON）の低減化が図れること ゲート長の縮小化が図れること 更に低電圧ロジック回路をＣ・ＭＯＳ構成にできそ
の低消費電力化が図れること 等種々の特徴を有し、高性能な高耐圧ＭＯＳ・ＩＣを安
定的に作成することができる。<Effects of the Invention> As described above, according to the present invention, it becomes easy to control the threshold voltage of each transistor forming an IC without increasing the number of special steps as described above.・ Improvement of withstand voltage characteristics of FET and reduction of on-resistance (R ON ). Reduction of gate length. Further, low voltage logic circuit can be composed of C / MOS to reduce its power consumption. It is possible to stably produce a high-performance high-voltage MOS / IC having the characteristics of.
第１図は本発明による一実施例の高耐圧ＭＯＳ・ＩＣの
基板断面図，第２図(a)乃至(g)は同実施例の製造工程を
説明するための基板断面図，第３図は従来の高耐圧ＭＯ
Ｓ・ＩＣの基板断面図，第４図(a)乃至(d)は従来の高耐
圧ＭＯＳ・ＦＥＴの高抵抗層の作成工程を説明するため
の基板断面図である。 １：半導体基板、２，２′：ソース領域、３，３′：ド
レイン領域、４：基板より高濃度でソース・ドレインよ
り低濃度の不純物領域、５：高抵抗層FIG. 1 is a sectional view of a substrate of a high breakdown voltage MOS IC according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (g) are sectional views of the substrate for explaining the manufacturing process of the same embodiment. Is the conventional high voltage MO
FIGS. 4 (a) to 4 (d) are cross-sectional views of a substrate for explaining a process of forming a high resistance layer of a conventional high breakdown voltage MOS.FET. 1: semiconductor substrate, 2, 2 ': source region, 3, 3': drain region, 4: impurity region of higher concentration than substrate and lower concentration than source / drain, 5: high resistance layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 7377−4Ｍ Ｈ０１Ｌ 29/78 ３０１ Ｄ (72)発明者 北出 秋夫 大阪府大阪市阿倍野区長池町22番22号 シ ヤープ株式会社内 (56)参考文献 特開 昭59−215766（ＪＰ，Ａ) 特開 昭53−68987（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Internal reference number for FI Technical indication 7377-4M H01L 29/78 301 D (72) Inventor Akio Kitade 22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture No. 22 Inside Sharp Corporation (56) References JP-A-59-215766 (JP, A) JP-A-53-68987 (JP, A)
Claims (1)
と同じ導電型で、基板より高濃度の不純物拡散領域と、
ドレイン部・チャネル間の領域にドレイン部と同じ導電
型で、ドレイン部より低濃度の不純物拡散領域とを設け
たオフセット構造を有する高耐圧ＭＯＳ電界効果トラン
ジスタと該高耐圧ＭＯＳ電界効果トランジスタより低い
耐圧特性をもつ低耐圧ＭＯＳ電界効果トランジスタとを
同一半導体基板に形成してなる、高耐圧ＭＯＳ電界効果
半導体装置の製造方法において、 前記ドレイン部と同じ導電型で、ドレイン部より濃度の
低い不純物を注入して、前記高耐圧ＭＯＳ電界効果トラ
ンジスタのドレイン部・チャネル間に高抵抗領域として
不純物拡散領域を形成する工程と、 該工程後、前記基板と同じ導電型を有し、前記工程に於
いて注入した不純物より低い濃度の不純物を前記高耐圧
ＭＯＳ電界効果トランジスタのソース部を囲む領域及び
前記高抵抗領域に於けるソース部側の一部領域に注入し
て、ソース部を囲む不純物拡散領域を形成すると同時に
前記高抵抗領域を２段階の不純物濃度を有する高抵抗領
域に形成する工程とを有することを特徴とする、高耐圧
ＭＯＳ電界効果半導体装置の製造方法。1. An impurity diffusion region of the same conductivity type as the substrate and having a higher concentration than that of the substrate, in a region surrounding a source portion on the semiconductor substrate,
A high withstand voltage MOS field effect transistor having an offset structure in which a region between the drain part and the channel has the same conductivity type as the drain part and an impurity diffusion region having a lower concentration than the drain part, and a withstand voltage lower than the high withstand voltage MOS field effect transistor. What is claimed is: 1. A method of manufacturing a high breakdown voltage MOS field effect semiconductor device, comprising: forming a low breakdown voltage MOS field effect transistor having characteristics on the same semiconductor substrate, wherein an impurity having the same conductivity type as the drain portion and a concentration lower than that of the drain portion is implanted. Then, a step of forming an impurity diffusion region as a high resistance region between the drain portion and the channel of the high breakdown voltage MOS field effect transistor, and having the same conductivity type as that of the substrate after the step, and implanting in the step. An impurity having a concentration lower than that of the above-mentioned impurities is added to a region surrounding the source portion of the high breakdown voltage MOS field effect transistor and the front region. Implanting into a partial region of the high resistance region on the source part side to form an impurity diffusion region surrounding the source part, and at the same time forming the high resistance region into a high resistance region having a two-step impurity concentration. A method of manufacturing a high breakdown voltage MOS field effect semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60007777A JPH0644605B2 (en) | 1985-01-19 | 1985-01-19 | Method of manufacturing high breakdown voltage MOS field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60007777A JPH0644605B2 (en) | 1985-01-19 | 1985-01-19 | Method of manufacturing high breakdown voltage MOS field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61168254A JPS61168254A (en) | 1986-07-29 |
| JPH0644605B2 true JPH0644605B2 (en) | 1994-06-08 |
Family
ID=11675102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60007777A Expired - Fee Related JPH0644605B2 (en) | 1985-01-19 | 1985-01-19 | Method of manufacturing high breakdown voltage MOS field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644605B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001274390A (en) * | 2000-01-18 | 2001-10-05 | Fuji Electric Co Ltd | High breakdown voltage device, manufacturing method thereof, and method for forming impurity diffusion region |
| US7923340B2 (en) * | 2007-02-14 | 2011-04-12 | Agere Systems Inc. | Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow |
| WO2012120802A1 (en) * | 2011-03-09 | 2012-09-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368987A (en) * | 1976-12-02 | 1978-06-19 | Fujitsu Ltd | Semiconductor device |
| JPS59215766A (en) * | 1983-05-24 | 1984-12-05 | Seiko Instr & Electronics Ltd | Metal oxide semiconductor integrated circuit device |
-
1985
- 1985-01-19 JP JP60007777A patent/JPH0644605B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61168254A (en) | 1986-07-29 |
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