JPH0793430B2 - Method for manufacturing MOS semiconductor device - Google Patents
Method for manufacturing MOS semiconductor deviceInfo
- Publication number
- JPH0793430B2 JPH0793430B2 JP63057556A JP5755688A JPH0793430B2 JP H0793430 B2 JPH0793430 B2 JP H0793430B2 JP 63057556 A JP63057556 A JP 63057556A JP 5755688 A JP5755688 A JP 5755688A JP H0793430 B2 JPH0793430 B2 JP H0793430B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate electrode
- base layer
- resist film
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000000034 method Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 7
- -1 boron ions Chemical class 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、一導電形の半導体基板に設けられる他導電形
のベース層およびその層の縁部近傍の表面にチャネル領
域をはさんで設けられる一導電形のソース層の何れもイ
オン注入を用いて形成する、例えば絶縁ゲート型バイポ
ーラトランジスタのようなMOS型半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention provides a base layer of another conductivity type provided on a semiconductor substrate of one conductivity type and a channel region on the surface near the edge of the layer. The present invention relates to a method for manufacturing a MOS semiconductor device such as an insulated gate bipolar transistor, in which any one conductivity type source layer is formed by ion implantation.
バイポーラトランジスタのベース電流をMOSFETで供給す
る構造をトランジスタと同一シリコン基板に形成するこ
とによって、大電流を比較的高速でスイッチングする伝
導度変調型FETあるいは絶縁ゲート型バイポーラトラン
ジスタ（以下IGBTと略す）が製造される。このIGBT製造
のウエハプロセスは、いわゆるたて型VDMOSFETとほぼ同
一である。第２図（ａ）〜（ｅ）はＮチャネル型IGBTの
製造のための従来のウエハプロセスの一部を示す。第２
図（ａ）はＮ形シリコン基板に不純物拡散によりN+層,P
層を形成し、N-層11,N+層12,P+層13からなるシリコン基
板１の上にゲート酸化膜２を介して多結晶シリコン層３
を堆積した状態を示す。この多結晶シリコン層３の上に
フォトレジストパターン４を形成（図ｂ）、このパター
ンをマスクにして多結晶シリコン層３をエッチングす
る。（図ｃ）。次いで、フォトレジスト膜４を除去した
あとほう素イオン５を注入し、N-層11にほう素注入領域
61を形成する（図ｄ）。次に温度を高めてほう素を拡散
させ、第２図（ｅ）のようにＰベース層６をN-層11内に
形成する。このＰベース層６にさらにひ素イオンを注入
し短時間のアニールにより第３図に示すようにN+ソース
層７を形成、このソース領域とＰベース層11とにソース
電極８を接触させ、ソース層７の露出面および多結晶シ
リコンゲート電極４を絶縁膜21で被覆する。By forming a structure in which the base current of the bipolar transistor is supplied by a MOSFET on the same silicon substrate as the transistor, a conductivity modulation type FET or an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) that switches a large current at a relatively high speed is provided. Manufactured. The wafer process for manufacturing this IGBT is almost the same as the so-called vertical VDMOSFET. FIGS. 2A to 2E show a part of a conventional wafer process for manufacturing an N-channel type IGBT. Second
Figure (a) shows the N + layer, P
Layer, and a polycrystalline silicon layer 3 is formed on a silicon substrate 1 composed of an N − layer 11, an N + layer 12, and a P + layer 13 via a gate oxide film 2.
Shows the state of depositing. A photoresist pattern 4 is formed on the polycrystalline silicon layer 3 (FIG. B), and the polycrystalline silicon layer 3 is etched using this pattern as a mask. (Fig. C). Then, after removing the photoresist film 4, boron ions 5 are implanted to the N − layer 11 for boron implantation region.
61 is formed (Fig. D). Next, the temperature is raised to diffuse boron, and the P base layer 6 is formed in the N − layer 11 as shown in FIG. Arsenic ions are further implanted into this P base layer 6 and annealed for a short time to form an N + source layer 7 as shown in FIG. 3. A source electrode 8 is brought into contact with this source region and the P base layer 11 The exposed surface of layer 7 and polycrystalline silicon gate electrode 4 are covered with an insulating film 21.
このようにして製造されたIGBTには、よく知られている
ようにN+ソース層7,Pベース層6,N-層11およびN+層12,P+
層13からなる寄生サイリスタを有するため、このサイリ
スタの導通によって破壊するいわゆるラッチング現象が
ある。IGBTは、伝導度変調を利用するため、正孔と電子
が共に流れる。第３図において電子はソース層７とN-層
11の間のＰベース層６の表面に近くのチャネル領域を、
そして正孔は図にIhで示したようにN+ソース層７の直下
のＰ層６の部分を流れる。この正孔電流Ihに沿っての抵
抗をRhとすると、Rh・Ih＝VhとN+ソース層７とＰ層６の
間の接合ビルトイン電圧VBとの間にVh≧VBが成立つと、
Ｐ層６からN+ソース層７への電流が生じ、寄生サイリス
タが導通してラッチングが発生する。Ihが大きくてもラ
ッチングが発生しないようにすることは、Rhをいかに小
さくしてVhを低下せしめるかにかかっている。そのため
の一つの対策としてＰベース層６の拡散深さを大きくす
る方法がある。これにより正孔電流Ihの横ぎる断面が大
きくなるため、ベース層６の抵抗Rhが小さくなる。しか
しながらベース層の拡散深さｒを大きくすると、MOSFET
のチャネル長ｌが大きくなるために同時にMOSFETの抵抗
が大きくなり、オン電圧の上昇となる。このような問題
は、たて型VDMOSFETにおける寄生バイポーラトランジス
タの動作防止においても同様に存在する。As is well known, the IGBT manufactured in this manner includes an N + source layer 7, a P base layer 6, an N − layer 11 and an N + layer 12, P +.
Since there is a parasitic thyristor made of the layer 13, there is a so-called latching phenomenon in which the thyristor is destroyed by conduction. Since the IGBT uses conductivity modulation, holes and electrons flow together. In FIG. 3, electrons are the source layer 7 and the N − layer.
The channel region near the surface of the P base layer 6 between 11
Then, the holes flow in the portion of the P layer 6 immediately below the N + source layer 7 as shown by I h in the figure. Assuming that the resistance along the hole current I h is R h , V h ≧ R h · I h = V h and the junction built-in voltage V B between the N + source layer 7 and the P layer 6 V h ≧ When V B holds,
A current is generated from the P layer 6 to the N + source layer 7, the parasitic thyristor becomes conductive, and latching occurs. Preventing latching from occurring even when I h is large depends on how small R h is to reduce V h . As one measure for this, there is a method of increasing the diffusion depth of the P base layer 6. As a result, the cross section of the hole current I h is increased, and the resistance R h of the base layer 6 is decreased. However, if the diffusion depth r of the base layer is increased, the MOSFET
Since the channel length 1 of the MOSFET becomes large, the resistance of the MOSFET becomes large at the same time, and the ON voltage rises. Such a problem also exists in preventing the operation of the parasitic bipolar transistor in the vertical VDMOSFET.
本発明の課題は、上述の問題を解消してベース層からソ
ース層への電流の流入に基づくラッチング現象が発生し
にくくし、かつMOSFETのオン電圧の上昇が防止されたMO
S型半導体装置を従来とほとんど同じ製造工程で製造す
る方法を提供することにある。An object of the present invention is to solve the above-mentioned problems, to prevent the latching phenomenon due to the inflow of current from the base layer to the source layer from occurring easily, and to prevent the rise of the on-voltage of the MOSFET.
An object of the present invention is to provide a method for manufacturing an S-type semiconductor device in almost the same manufacturing process as a conventional method.
上記の課題の解決のために、本発明は、一導電型の半導
体基板に設けられる他導電形のベース層およびそのベー
ス層の縁部近傍の表面にチャネル領域をはさんで設けら
れる一導電形のソース層を形成する際に、半導体基板上
に絶縁膜を介して形成されるゲート電極のパターンニン
グの際のエッチングマスクとして用いられ、オーバエッ
チングによりゲート電極の端よりひさし状に突出したレ
ジスト膜をマスクにして不純物イオンを注入し、注入さ
れた不純物を拡散してゲート電極の下に所定の幅のチャ
ネル領域が形成されるようにベース層を形成し、次いで
レジスト膜を除去したのちゲート電極をマスクにして別
の不純物イオンを注入し、短時間のアニールでソース層
を形成するものとする。In order to solve the above problem, the present invention provides a base layer of another conductivity type provided on a semiconductor substrate of one conductivity type and a conductivity type provided with a channel region on the surface near the edge of the base layer. Used as an etching mask when patterning the gate electrode formed on the semiconductor substrate via the insulating film when forming the source layer, and a resist film protruding like an eave from the edge of the gate electrode by over-etching. Using as a mask to implant impurity ions, diffuse the implanted impurities to form a base layer so that a channel region having a predetermined width is formed under the gate electrode, and then the resist film is removed and the gate electrode is removed. Is used as a mask to implant another impurity ion, and the source layer is formed by annealing for a short time.
ベース層のためのイオン注入をゲート電極の端よりひさ
し状に突出したレジスト膜をマスクとして行うため、注
入領域とゲート電極下のチャネル領域の端となる位置と
の距離が長くなり、その位置にベース層の端が来るよう
に拡散を行うと、ベース層の拡散深さが深くなってベー
ス層の抵抗をチャネル長を長くすることなく低下させる
ことができる。Since the ion implantation for the base layer is performed by using the resist film protruding like an eave from the end of the gate electrode as a mask, the distance between the implantation region and the position of the end of the channel region under the gate electrode becomes long, and If the diffusion is performed so that the end of the base layer comes, the diffusion depth of the base layer becomes deep and the resistance of the base layer can be reduced without increasing the channel length.
第１図（ａ）〜（ｅ）は本発明の一実施例のIGBT製造の
ためのウエハプロセスの一部を示す。第２図（ａ），
（ｂ）と同様にシリコン基板のN-層11の表面にゲート酸
化膜を介して堆積した多結晶シリコン層３の上にフォト
レジストパターンを形成した状態が第１図（ａ）であ
る。このあと多結晶シリコン層３をエッチングしてゲー
ト電極３を形成するが、エッチング時間を長くしてレジ
スト膜４の下への横方向エッチングも行い、レジスト膜
４をゲート電極３の上にひさし状に突出させた（図
ｂ）。このときの多結晶シリコン層のオーバエッチ量ｔ
が設計パラメータであり、エッチング時間等のエッチン
グ条件により制御される。このレジスト膜４をマスクに
してほう素イオン５に注入し、ほう素注入領域61を形成
した（図ｃ）。次いでレジスト膜を除去後、例えば1150
℃,20時間の熱処理によりゲート電極３の直下にチャネ
ル領域を形成する深さ約10μｍのＰベース層６の拡散を
行った（図ｄ）。さらに、ゲート電極および新たに形成
したフォトレジスト膜４をマスクにしてひ素イオン51を
注入して短時間のアニールにより0.2μｍ程度の薄いN+
ソース層７を形成した（図ｅ）。1 (a) to 1 (e) show a part of a wafer process for manufacturing an IGBT according to an embodiment of the present invention. Figure 2 (a),
Similar to FIG. 1B, FIG. 1A shows a state in which a photoresist pattern is formed on the polycrystalline silicon layer 3 deposited on the surface of the N − layer 11 of the silicon substrate via the gate oxide film. After that, the polycrystalline silicon layer 3 is etched to form the gate electrode 3, but the etching time is lengthened to perform lateral etching below the resist film 4 so that the resist film 4 is formed on the gate electrode 3 in an eaves-like shape. (Fig. B). At this time, the overetch amount t of the polycrystalline silicon layer
Is a design parameter and is controlled by etching conditions such as etching time. Using the resist film 4 as a mask, boron ions 5 are implanted to form a boron-implanted region 61 (FIG. C). Then, after removing the resist film, for example, 1150
By heat treatment at 20 ° C. for 20 hours, the P base layer 6 having a depth of about 10 μm for forming a channel region immediately below the gate electrode 3 was diffused (FIG. D). Further, arsenic ions 51 are implanted by using the gate electrode and the newly formed photoresist film 4 as a mask, and annealing is performed for a short time to thin N + of about 0.2 μm.
A source layer 7 was formed (Fig. E).
第４図はこのようにしてＰベース層６およびN+ソース層
７を形成したIGBTを示す。この場合Ｐ層６形状のための
ほう素注入領域の端はＡ点になる。すなわち、ゲート電
極３のマスクにしてほう素イオンを注入した場合の注入
領域の端Ｂ点より第１図（ｂ）に示したオーバエッチ量
ｔだけゲート電極から離れた位置になる。従ってゲート
電極３の下に第３図と同様なチャネル長ｌを得るような
拡散を行うと、拡散距離r1と一点鎖線62で示した第３図
の場合のＰ層の縁までの拡散距離ｒとの間には次式が成
立つ。FIG. 4 shows an IGBT having the P base layer 6 and the N + source layer 7 thus formed. In this case, the end of the boron-implanted region for the P layer 6 shape is point A. That is, the gate electrode 3 is used as a mask and is located away from the gate electrode by the overetch amount t shown in FIG. 1B from the end point B of the implantation region when boron ions are implanted. Therefore, if diffusion is performed under the gate electrode 3 so as to obtain the same channel length 1 as in FIG. 3, the diffusion distance r 1 and the diffusion distance to the edge of the P layer in the case of FIG. The following equation holds with r.
r1＝ｒ＋ｔ このときＰ層６とN-層11の間の平らな接合までの拡散深
さｄは次の式で与えられる。r 1 = r + t At this time, the diffusion depth d to the flat junction between the P layer 6 and the N − layer 11 is given by the following equation.
N+ソース層７直下のＰベース層６の抵抗が拡散深さに反
比例するとすれば、第４図のＰベース層６の正孔の流れ
に沿った抵抗Rh′と、Ｐ層６が線62までである従来のそ
のような抵抗Rhの間には次の関係が得られる。 Assuming that the resistance of the P base layer 6 directly under the N + source layer 7 is inversely proportional to the diffusion depth, the resistance R h ′ along the flow of holes of the P base layer 6 in FIG. Between conventional such resistances R h up to 62, we have the following relationship:
（２）式はｔ≪ｒとして近似したものである。さらに、
実際の拡散の進行の深さ方向が横方向よりも速いのでｔ
の値は（２）式より大きくなる。また、ソース層７とN-
層11のＰベース層６表面のチャネル領域の濃度を従来と
同じにするには、ほう素の注入濃度を従来より高くしな
ければならないので、実際のRh′は（２）式よりもかな
り小さくなることがわかる。（２）式によれば、ｒ＝10
μm,t＝２μｍとすると20％の抵抗減少となり、ラッチ
アップの発生する電流もこれに比例して20％増加する。
このような抵抗の減少はｔ、すなわち多結晶シリコンの
オーバエッチ量によって決まり、エッチング条件の制御
により再現性よく最適なｔを得ることは極めて容易であ
る。 Expression (2) is approximated as t << r. further,
Since the actual depth direction of diffusion is faster than the lateral direction, t
The value of is larger than that of equation (2). In addition, the source layer 7 and the N -
In order to make the concentration of the channel region on the surface of the P base layer 6 of the layer 11 the same as the conventional one, it is necessary to make the implantation concentration of boron higher than the conventional one. Therefore, the actual R h ′ is considerably larger than that of the equation (2). You can see that it will be smaller. According to the equation (2), r = 10
If μm, t = 2 μm, the resistance decreases by 20%, and the current generated by latch-up increases by 20% in proportion to this.
Such a decrease in resistance is determined by t, that is, the amount of overetching of polycrystalline silicon, and it is extremely easy to obtain an optimum t with good reproducibility by controlling the etching conditions.
本発明によれば、半導体基板へ異なる導電形のベース層
を形成する際のセルフアライメントのイオン注入をゲー
ト電極上のレジスト膜を残したままで行い、ソース層の
形成のためのイオン注入のマスクにはゲート電極を用い
ることにより、ゲート電極エッチング時のオーバエッチ
ングでレジスト膜をゲート電極より突出させることがで
きるため、ベース層のための拡散エッジがゲート電極か
ら遠ざかり、MOSFET部のチャネル長が長くすることなく
ベース層の拡散深さを深くすることができる。この結
果、ベース層の抵抗を下げ高い電流までラッチアップし
ないIGBTあるいはたて型VdMOSFETをつくることが可能に
なった。また、従来の製造方法の工程とほとんど差がな
いため、工数の増加がなく、コストも従来通りとなる。According to the present invention, self-alignment ion implantation for forming base layers of different conductivity types on a semiconductor substrate is performed with a resist film on a gate electrode left, and is used as an ion implantation mask for forming a source layer. By using the gate electrode, the resist film can be made to protrude from the gate electrode by over-etching during gate electrode etching, so the diffusion edge for the base layer moves away from the gate electrode, and the channel length of the MOSFET part increases. It is possible to increase the diffusion depth of the base layer without the need. As a result, it became possible to reduce the resistance of the base layer and make an IGBT or vertical VdMOSFET that does not latch up to a high current. Further, since there is almost no difference from the steps of the conventional manufacturing method, the number of steps is not increased and the cost is the same as the conventional one.
第１図は本発明の一実施例のIGBT製造工程の一部を順に
示す断面図、第２図は従来のIGBTの製造工程の一部を順
に示す断面図、第３図は従来の製造方法によるIGBTの要
部断面図、第４図は本発明の一実施例によるIGBTの要部
断面図である。 11:シリコン基板N-層、2:ゲート酸化膜、3:多結晶シリ
コン層（ゲート電極）、4:フォトレジスト膜、5:ほう素
イオン、51:ひ素イオン、6:Pベース層、7:N+ソース層。FIG. 1 is a sectional view sequentially showing a part of an IGBT manufacturing process of one embodiment of the present invention, FIG. 2 is a sectional view showing a part of a conventional IGBT manufacturing process in order, and FIG. 3 is a conventional manufacturing method. FIG. 4 is a sectional view of an essential part of an IGBT according to the present invention, and FIG. 4 is a sectional view of an essential part of an IGBT according to an embodiment of the present invention. 11: Silicon substrate N - layer, 2: Gate oxide film, 3: Polycrystalline silicon layer (gate electrode), 4: Photoresist film, 5: Boron ion, 51: Arsenic ion, 6: P base layer, 7: N + source layer.
Claims (1)
形のベース層および該ベース層の縁部近傍の表面にチャ
ネル領域をはさんで設けられる一導電形のソース層を形
成する際に、半導体基板上に絶縁膜を介して形成される
ゲート電極のパターニングのためにレジスト膜をパター
ニングし、このレジスト膜をマスクとしてゲート電極を
オーバエッチングしレジスト膜がゲート電極の端よりひ
さし状に突出するように形成し、ゲート電極の端よりひ
さし状に突出したレジスト膜をマスクにして不純物イオ
ンを注入し、注入された不純物を拡散してゲート電極の
下に所定のチャネル領域が形成されるようにベース層を
形成し、次いで前記レジスト膜を除去したのちゲート電
極をマスクにして別の不純物イオンを注入し、短時間の
アニールでソース層を形成することを特徴とするMOS型
半導体装置の製造方法。1. When forming a base layer of another conductivity type provided on a semiconductor substrate of one conductivity type and a source layer of one conductivity type provided across a channel region on the surface near the edge of the base layer. , A resist film is patterned for patterning a gate electrode formed on a semiconductor substrate through an insulating film, and the gate electrode is over-etched using this resist film as a mask so that the resist film protrudes like an eaves from the end of the gate electrode. Then, impurity ions are implanted using the resist film protruding from the edge of the gate electrode as an eaves-shaped mask, and the implanted impurities are diffused to form a predetermined channel region under the gate electrode. A base layer is formed on the substrate, then the resist film is removed, another impurity ion is implanted using the gate electrode as a mask, and a short-time anneal is performed to complete the Method of manufacturing a MOS type semiconductor device, which comprises forming a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63057556A JPH0793430B2 (en) | 1988-03-11 | 1988-03-11 | Method for manufacturing MOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63057556A JPH0793430B2 (en) | 1988-03-11 | 1988-03-11 | Method for manufacturing MOS semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01231377A JPH01231377A (en) | 1989-09-14 |
| JPH0793430B2 true JPH0793430B2 (en) | 1995-10-09 |
Family
ID=13059087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63057556A Expired - Lifetime JPH0793430B2 (en) | 1988-03-11 | 1988-03-11 | Method for manufacturing MOS semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793430B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244429A (en) * | 1992-12-24 | 1994-09-02 | Mitsubishi Electric Corp | Insulated-gate semiconductor device and manufacture thereof |
| CN102034707B (en) * | 2009-09-29 | 2014-01-01 | 比亚迪股份有限公司 | Method for manufacturing IGBT |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035573A (en) * | 1983-08-08 | 1985-02-23 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS628568A (en) * | 1985-07-04 | 1987-01-16 | Tdk Corp | Longitudinal type semiconductor device and manufacture thereof |
-
1988
- 1988-03-11 JP JP63057556A patent/JPH0793430B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01231377A (en) | 1989-09-14 |
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