JPH05251709A - Mos-fet for power having source-base short-circuitting part and producing method therefor - Google Patents

Abstract

PURPOSE: To form a source-base short-circuitting part for preventing a parasitic bipolar transistor from being turned on, regarding an MOS-FET for power produced by double diffusion technology. CONSTITUTION: An ohmic short-circuitting part, which is formed under the main surface of a semiconductor wafer, between a 1st diffusion (base) region 76 and a 2nd diffusion (source) region 88 is extended from the main surface through the 2nd diffusion region into the 1st diffusion region and formed from a metal electrode 102 in ohmic contact with the both regions. Preferably, the metal electrode is installed inside a V-shaped groove 106 which is, formed through the 2nd region to the 1st region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to power metal-oxide-semiconductor field effect transistors (MOS-FETs) manufactured by the double diffusion technique. More particularly, the present invention relates to a method of manufacturing such a transistor using a minimal number of masking steps, a method of forming an ohmic short between a source layer and a base layer in manufacturing such a transistor, and thus Regarding manufactured transistors.

Generally speaking, the known power MOS-F is known.
The ET consists of many (thousands in practice) unit cells formed on a single silicon semiconductor wafer. In that case, the dimensions of each element are on the order of 300 mils (7.6 mm) square, and every cell in each element is electrically connected in parallel. The width of each cell is typically 5 to 50 microns. As described in more detail below, power MO
An example of a known method for manufacturing S-FETs is the double diffusion technique, which first involves, for example, N
A common drain region of a shaped semiconductor material is provided.
A base region is formed inside the drain region by a first diffusion process, and then a source region is formed so as to be completely included in the base region by a second diffusion process. When the drain region is N-type, a P-type base region is formed by using the acceptor impurity in the first diffusion process, and an N ^{+ -type} source region is formed by using the donor impurity in the second diffusion process. It

The source, base and drain regions in the power MOS-FET structure correspond to the emitter, base and collector of the parasitic bipolar transistor, respectively. As is known, when such a parasitic bipolar transistor is turned on during the operation of the power MOS-FET, the blocking voltage of the power MOS-FET and dV /
The dt rated value is substantially reduced. Therefore, power MOS
In order to prevent the turn-on of the parasitic bipolar transistor during operation of the FET, it is customary to short the layers forming the source and base regions together by ohmic contact means.

Known power MOS-types currently manufactured.
Since up to 6 masking steps are required based on the structure of the FET, it is necessary to perform highly accurate alignment for several times in order to obtain a useful device. Especially when forming the source-base short circuit,
By selectively masking over a surface area of a portion of the base region between the first and second diffusion steps to form a diffusion barrier, impurities for the next source diffusion are formed in the base region of such area. Intrusion is prevented. Subsequent application of a metal coating for the source electrode will cause some of the source electrode to make ohmic contact also to the pre-masked area of the base region.

In such a known power MOS-FET manufacturing technique, the mask pattern for forming the source-base short-circuit portion must be accurately aligned in a special manufacturing process, and in the ON state. The short circuit portion which does not contribute to the conductivity also occupies a considerable portion of the surface area of each unit cell of the MOS-FET.

[0006]

SUMMARY OF THE INVENTION One of the objects of the present invention is to provide a double diffused power M which can be manufactured using a minimum number of masking steps.
To provide an OS-FET. Also, the MOS-FET manufactured by the conventional masking operation and the MOS-FE manufactured by the masking operation of the present invention.
Double-spread power MO useful for any of T
It is also an object of the present invention to provide a method of forming an integrated source-base short in an S-FET.

Briefly in accordance with one aspect of the present invention,
A double-diffused power MOS-FET including a unit cell formed on a semiconductor substrate including a drain region of one conductivity type (for example, N type) and having a main surface is provided.
On the other main surface, the drain terminal, which is usually made of a metal film, is electrically connected to the drain region. To form the base region, a first region having an opposite conductivity type (P type in this case) is formed in the drain region. Such a first region exhibits a finite lateral extent and has an outer periphery terminating in the main surface. Further, in order to form the source region, the second region showing the one conductivity type (N type in this case) is formed so as to be completely included in the inside of the base region. The depth is smaller than in the base region. The second region has an outer periphery that terminates in the main surface and is spaced apart inside the outer periphery of the base region. As a result, the base region and the source region that are both made of an N-type semiconductor material are formed in the main surface. It exists as a strip of the opposite conductivity type (P type in this case) with the drain region. The source terminal is electrically connected to the second region. A conductive gate electrode and a gate insulating layer are formed on the main surface so as to cover at least the band-shaped portion of the first region in the lateral direction, and a gate terminal is electrically connected to the gate electrode. .. Finally, an ohmic short circuit portion is formed below the main surface between the first region (base region) and the second region (source region).

According to one embodiment of the invention, the source terminal comprises a metal region, preferably aluminum, overlying the source region, and the ohmic short between the base region and the source region is for the source terminal. From the metal electrode of the second
At least one microalloy extending partially through the region of the first region and into the first region
Composed of spikes. Such a microalloy spike is formed by heating the semiconductor substrate after installing the metal electrode under appropriate conditions.

According to another embodiment, the V-groove is formed by preferential etching of the source and base regions. Such a V-shaped groove extends through the source region and its bottom partly extends into the base region. A metal electrode is installed in the V-shaped groove so as to cover the source region and makes ohmic contact with both the source region and the base region, thereby forming both the source terminal and the ohmic short circuit portion.

As can be seen from the above description and the following detailed description, the method of forming an integrated source-base short circuit according to the present invention and the short circuit formed thereby realize the self-alignment and the maximum. It is of great significance in that it simplifies the overall structure and manufacturing method of a MOS-FET by using a small number of masking steps. Briefly stated in accordance with another aspect of the invention, a method of making a double diffused power MOS-FET is provided. In such a method, first, a silicon semiconductor wafer substrate including a drain region of one conductivity type (for example, N type) and having a main surface is prepared. Next, a first insulating layer (or a gate insulating layer), a conductive gate electrode layer (for example, a high-concentration impurity-doped N ^{+ -type} polycrystalline silicon layer),
A second insulating layer and a third insulating layer are successively formed on the major surface, with the result that the third insulating layer is located at the top.

The important point here is that only a total of three masking steps are required. First, a first mask having windows for finally forming at least one base region and at least one source region is placed on the third insulating layer. Next, an opening defined by the window of the first mask is formed in at least the third insulating layer, the second insulating layer and the gate electrode layer by successive etching steps. During such etching, the gate electrode layer is undercut. Then, the first mask is removed.

Next, two impurity introduction steps are carried out, with the windows in the various layers serving as impurity barriers. More specifically, in the first impurity introduction step, an impurity (for example, P-type semiconductor material) suitable for forming a first region having a conductivity type opposite to that of the drain region through the opening defined by the first mask. A base region is formed by introducing an acceptor impurity) for generating a. The lateral extent of such base region is determined in part by the size of the opening defined by the first mask and also depends on the impurity introduction time and other process variables.

A source region is formed by the subsequent second impurity introduction step. That is, an impurity suitable for forming the second region exhibiting the one conductivity type (N type in this case) is introduced into the base region through the opening also defined by the first mask. The important thing here is
That is, it is not necessary to install an additional impurity barrier on any part of the base region. Since the source region is formed so as to be completely included in the base region, the first region (base region) has a strip portion having an opposite conductivity type between the source region and the drain region in the main surface. Will exist as The introduction of the source region also produces a silicon dioxide layer at least on the sidewalls of the opening through the gate electrode layer.

Next, the insulating layer on the surface of the source region is removed by a parallel beam in the area within the opening of the third insulating layer defined by the first mask. By using a parallel beam, such etching proceeds without removing the silicon dioxide layer on the sidewalls of the opening provided in the gate electrode layer. The subsequent second masking step limits the gate contact area to the device portion different from the location of the source region. The third insulating layer and the second insulating layer are successively removed by etching using the window of the second mask until the gate electrode layer of polycrystalline silicon is reached. Then, the second mask is removed.

Next, an electrode metal such as aluminum is placed on the wafer and then patterned using a third mask to form source and gate terminals. Finally, by heating the wafer to form an ohmic short between the first region and the second region, which respectively constitute the base region and the source region, the metal source electrode penetrates the source region. Forming at least one microalloy spike that extends partially into the base region.

According to another method according to the invention:
The entire device is manufactured in the same manner, except that a V-shaped groove is formed by performing preferential etching to form a source-base short circuit, and then an ohmic contact is made with both the source region and the base region. Source electrode material is placed in the V-shaped groove. More specifically, the V-shaped groove is formed by removing the insulating layer on the surface of the source region by the parallel beam and then performing preferential etching on the first region and the second region. This V-shaped groove is
It is such that it penetrates the second region and its bottom partly extends into the first region.

At this point, a second mask with a window defining the gate contact area was installed, and then a third mask.
The insulating layer and the second insulating layer are successively removed by etching, so that an opening for the gate electrode is formed.
Then, the second mask is removed. Finally, a source electrode layer and a gate electrode layer are formed by depositing an electrode metal on the wafer and then patterning using a third mask. Such a source electrode layer extends into the V-groove and makes ohmic contact with both the second region and the first region.

The method of forming the source-base short-circuited portion according to the present invention is used in combination with the minimum masking technique of the present invention, and is a double diffusion type power MOS-device having a self-aligned channel.
Although particularly advantageous when manufacturing FETs, it is also possible to apply such a method to power MOS-FETs manufactured by other techniques. Although novel features of the invention are set forth in the appended claims, the structure and content of the invention are best understood from the following detailed description when read with the accompanying drawings. Should be.

[0019]

DESCRIPTION OF THE PRIOR ART First, in order to make the present invention easier to understand, an example of a conventional double diffusion type power MOS-FET will be described in detail with reference to FIGS. In particular, the conventional MOS-FET manufacturing technique shown in FIGS. 1 and 2 requires a maximum of 6 masking steps, and in order to obtain a useful element, highly accurate alignment is required at that time. It should be noted that this needs to be done.

Referring first to FIG. 2, the completed conventional power MOS-FET consists of a large number (in practice thousands) of unit cells 16 formed on a single semiconductor wafer 18. Thus, the unit cells on each element are electrically connected in parallel. Such unit cell 16
Is, N-type or N ^- common drain region having a common metal electrode 22 made of the shape of the silicon semiconductor material and via the N ⁺ form a substrate 24 having a high impurity concentration and ohmic contact 2
It has 0.

The unit cell 16 also has individual source regions 26 and base regions 28 formed by the double diffusion technique described below. On the substrate surface 29, each base region 28 is present as a strip 30 of P-type semiconductor material between the N-type source region 26 and the drain region 20. Metal electrode 32 covers most of the device and is in ohmic contact with both source region 26 and base region 28. In this case, each base area 2
An extension 34 of the base region 28 reaching the surface of the semiconductor wafer is formed to facilitate contact with the semiconductor wafer 8. Such an extension 34 can be regarded as a short piece, which necessarily occupies a certain surface area. Thus, the metal electrode 32 serves not only as a common source electrode but also as a required source-base short-circuit portion.

A strip 3 of P-type semiconductor material in which a conductive gate electrode 36 separated by a gate insulating layer 38 forms at least a base region 28 in order to create a channel which enables an enhancement-type operation of the field-effect transistor.
0 is arranged on the surface 29 of the semiconductor wafer 18 so as to overlap in the lateral direction. Although many MOS-FETs are provided with a metal gate electrode, in the case of a power MOS-FET, a polycrystalline silicon layer having a high conductivity due to addition of a high concentration of impurities is used as a gate electrode for the sake of manufacturing convenience. It is customary. Also in this case, MOS-FET
Is saved. Although not apparent from the cross-sectional view of FIG. 2, the plurality of segments 36 of gate electrode material are comprised of a single perforated layer and are therefore electrically connected to each other.

The top surface of gate electrode segment 36 is protected by a suitable insulating material (eg, silicon dioxide layer 40 and silicon nitride layer 42). A gate contact window 44 is formed for the gate terminal, and a metal coating 46 is placed through the window to make ohmic contact with the gate electrode material (36). The upper surface of the completed device has a metal film 32 for the source / base and a metal film 4 for the gate.
It is almost completely covered with a metal coating, except for the insulating gap 48 between it and 6.

A large number of unit cells 16 are formed, and the number thereof is several thousands as described above. No particular plan view is shown here, but various suitable arrangements are known. For example, the individual cells 16 may be arranged in a dense hexagonal pattern, square, or rectangular strip. Even though there are thousands of unit cells 16, only a few gate contact windows 44 are formed. Since the gate current flowing is relatively small, extremely low resistance is not required for the gate electrodes connected to each other.

In terms of operation, each unit cell 1
6 is normally in a non-conductive state and has a relatively high breakdown voltage. When a positive voltage is applied to the gate electrode 36 via the metal film 46 for the gate terminal, an electric field spreading in the base region 28 via the gate insulating layer 38 is generated, whereby the electric field below the gate electrode 36 and the insulating layer 38 is generated. A thin N-type conductive channel is induced just below the located surface 29. As is known, the higher the gate voltage, the thicker the conductive channel, and therefore the higher the operating current that flows. Current flows horizontally near surface 29 between source region 26 and drain region 20 and then vertically through drain region 20 and substrate 24 to reach metal electrode 22.

Referring now to both FIG. 1 and FIG. 2, in a typical conventional manufacturing method, N / having a thickness and resistivity suitable to support the desired voltage.
The N ^{+ type} epitaxial wafer 18 is first prepared. Specifically, the wafer 18 includes an N ⁺ -type silicon substrate 24 having a thickness of about 15 mils (0.38 mm) and a resistivity of the order of 0.01 Ω · cm. The N-type impurity doped portion 20 of the wafer 18 finally forms the common drain region of the power MOS-FET.

The wafer 18, and more particularly the drain region 20, has a major surface 29 on which several layers are deposited in succession. That is, first, by heating in the presence of oxygen in the furnace, the gate insulating layer (oxide layer) 38 is formed on the surface 29 of the drain region 20. Next, a highly conductive gate electrode 36 is deposited, which may comprise, for example, a 1.1 micron layer of polycrystalline silicon doped with a high concentration of phosphorus.

Next, a second silicon dioxide layer 40 is formed on the polycrystalline silicon layer 36. In some cases,
Following that, a silicon nitride layer 42 is applied. After a uniform surface layer is formed on the wafer, a fine-shaped photoresist mask (not shown) is installed to limit the position of the P-type impurity diffusion for the base region, and the top surface is formed by a suitable etching technique. The four layers 42, 40, 36 and 38 are removed until they reach the surface 29 of the drain region 20. Thereafter, to form the P-type base region 28, a first diffusion step is performed which comprises diffusing an appropriate acceptor impurity into the drain region 20 to a depth of, for example, 3 microns. Further, at the same time as the P-type impurity diffusion, a temporary oxide layer 52 is formed on the wafer surface.

Next, in such a conventional method, a diffusion barrier consisting of a portion of the oxide layer 52 is formed prior to the second diffusion. To that end, the use of a finely shaped photoresist mask (not shown) that requires relatively precise alignment causes the oxide layer 52 produced during the first diffusion step to remain on only a portion of the base region. It is necessary to do so.

After removal of the photoresist mask, a second diffusion step consisting of diffusing the appropriate donor impurities into the base region is performed, thereby forming the N ^{+ -type} source region 26. At the same time, an oxide lip 54 is formed on the side edge of the gate electrode 36. Next, a silicon dioxide layer (not shown) is provided over the surface of the wafer, and a third mask is applied to define the contact area. While using such a third mask,
The oxide layer 52 on the extension 34 of the P-type base region 28 and the silicon dioxide layer just formed on the N ^{+ -type} source region 26 are removed by etching. In doing so, layers 42 and 40 are also removed, thereby forming gate contact window 44.

Next, metal (preferably aluminum) is vapor-deposited on the wafer, and then etching is performed using another mask to cover almost the entire area of the unit cell 16 except the insulating gap 48 surrounding the gate terminal 46. Overlying metal coatings 32 and 46 are provided. Based on such a conventional structure, the source electrode 32 has the source region 2
6 and ohmic contact with the P-shaped base region 28 via the extension 34 at the same time. In this way, the source-base short-circuit portion for preventing the turn-on of the parasitic bipolar transistor is formed.

As can be seen from the above description, in the conventional manufacturing method of the power MOS-FET having the short-circuit portion integrally formed between the source region and the base region, several masking steps, alignment and source are performed. A diffusion barrier is required.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION In the remaining FIGS. 3 to 11, a method according to the invention and a power MOS-FET manufactured thereby are shown. Referring first to FIG. 3, in order to fabricate a self-aligning double-diffused MOS-FET having an integrated source-base short, according to the present invention, first of all, an N / N ^{+ type} epitaxial is used. A wafer 60 is prepared. Such a wafer 60 is composed of an N ^{+ type} substrate 62 doped with a high concentration of impurities and a drain region 64 of one conductivity type (for example, N type) epitaxially grown thereon and has a main surface 66. Then the first insulating layer (or gate insulating layer)
68 is formed, which is the wafer 60 in the furnace.
Is preferably composed of a single silicon dioxide layer produced by heating in the presence of oxygen. Alternatively, for example, a silicon dioxide layer formed as described above and a silicon nitride layer formed on the silicon dioxide layer may be used.
The insulating layer 68 may be configured. Then, the conductive gate electrode layer 70 is provided. This is, for example, 1.1
It may consist of a highly conductive N ^{+ -type} layer formed by adding a high concentration of phosphorus to a micron polycrystalline silicon layer. In the case of such a structure, the gate electrode is not actually made of metal, but is electrically equivalent to that.

Next, a second insulating layer 72, preferably a single silicon dioxide layer, is formed on the polycrystalline silicon layer 70. The second insulating layer 72 is formed from 6000 to 7 in order to insulate the gate electrode 70 after completion and the source electrode 102 after completion as shown in FIG.
It typically has a thickness of 000 angstroms. After formation of the second insulating layer 72, a third insulating layer 74, preferably a single silicon nitride layer or, for example, a single aluminum oxide layer, is deposited on the second insulating layer 72. (The role of the third insulating layer 74 will be described later.) These four layers 68, 70, 72 and 74.
Are placed one after another and are present over the entire wafer surface.

Next, in accordance with conventional photoresist techniques, a first mask 77 with windows 78 to help ultimately define the source and base regions is removed by a third insulating layer 74.
Installed on top. The first mask 77 is a relatively fine mask, but accurate alignment is not necessary. This is because this is the first mask and the wafers up to this point consist exclusively of uniform layers. Of particular importance is that the first mask 78 is the only fine featured mask in the method of the present invention. It should be noted that FIG. 3 shows the wafer immediately after the first mask 77 is installed.

Next, referring to FIG. 4, a suitable method will be described. The third insulating layer 74, the second insulating layer 72, the polycrystalline silicon layer (gate electrode layer) 70, and the first insulating layer. As a result of the fact that 68 is successively removed by etching, the first
Openings 80, 82, 84 and 86 are formed in the areas defined by the windows 78 of the mask 77, respectively. In this case, the gate electrode layer 70 needs to be undercut. More specifically, the third insulating layer 7
If 4 consists of a single silicon nitride layer, this is removed by plasma etching. Then, if the second insulating layer 72 comprises a single silicon dioxide layer, it is removed by chemical etching. Next, the polycrystalline silicon layer 70 is removed by plasma etching, but the etching in this case is performed for a time sufficient to cause the polycrystalline silicon layer 70 to recede significantly along the lateral direction for the reason described below. Continued over. In practice, it is sufficient to undercut, for example, about 1.0 micron. Finally, if the first insulating layer 68 comprises a single silicon dioxide layer 68, this is removed by chemical etching. Then, if the photoresist layer (mask) 77 is removed, the wafer in the state shown in FIG. 4 is obtained.

Next, referring to FIG. 5, after a suitable cleaning operation,
The base region 76 of the transistor is introduced into the drain region 64, preferably by a first diffusion step. More specifically, the openings 80 defined by the first mask 77 are suitable impurities for forming the opposite conductivity type region,
Diffused into drain region 64 through 82, 84 and 86. In the case shown, the P-type semiconductor material for the base region 76 is obtained by diffusing the acceptor impurities. The first diffusion step to form the base region 76 is performed until a depth of about 3 microns is reached, for example. The lateral extent of the base region 76 depends in part on the dimensions of the openings 80, 82, 84 and 86 defined by the first mask 77 and also on other process variables such as time, temperature and pressure. .. The base region 76 has an outer periphery 79 that terminates in the main surface 66.

Next, the source region 88 of the transistor is introduced into the base region 76, preferably by a second diffusion step, without the need for a masking step with alignment. More specifically, the same openings 80, 82 and the same impurities suitable for forming the one conductivity type diffusion region are formed.
It is introduced through 84 and 86. In the case shown,
By diffusing the donor impurity, an N ^{+ type} source region 88 having a high impurity concentration is formed. The second diffusion step is performed until the depth reaches about 1.0 micron. The source region 88 thus formed is completely contained within the base region 76 formed by the first diffusion step, and the depth and lateral extension of the former are smaller than those of the latter. As a result, in the main surface 66, the base region 76 exists between the source region 88 (N ^{+ type} ) and the drain region 64 (N ^{− type} ) as a strip 90 of the opposite conductivity type (P type). become.

Further, during the second diffusion step to form the source region 88, a silicon dioxide layer 92 is formed on the surface of the source region 88 and also on the sidewalls 84 of the polycrystalline silicon layer 70. Extension 9 of silicon dioxide layer 92
3 is generated. The wafer at this stage is in the state shown in FIG. Next, as shown in FIG. 6, the silicon dioxide layer 92 (FIG. 5) on the surface of the source region 88 is removed, preferably by reactive ion etching or, for example, ion milling. To do so, a parallel beam 94 with a high selectivity for silicon dioxide over silicon is used.
Is used. According to an example of the parallel beam ion etching method, the wafer is excited by a high frequency power source to oscillate the etching ions perpendicularly to the wafer surface, thereby obtaining a directional effect. Parallel beam 9
When removing the silicon dioxide layer 92 by
Of the insulating layer 74 acts to protect the upper surface of the MOS-FET, and the edge of the opening 80 will form a shadow mask. As a result of the removal of silicon dioxide layer 92 by parallel beam 94, silicon dioxide layer 92 on sidewall 84 of polycrystalline silicon layer 70 is not removed.

Next, as shown in FIG. 7, a second mask 96 for defining the gate contact window is installed. Using such a mask 96, the third insulating layer 74 (if at least made of silicon nitride) is removed by plasma etching, and then the second insulating layer 72 is removed by chemical etching, resulting in a gate electrode. Openings 98 and 100 are formed as windows for. Thereafter, the second mask 96 is removed, and the wafer cleaning operation is performed.

Next, as shown in FIG. 8, an electrode metal (preferably aluminum) is placed on the device, preferably by vapor deposition, and then patterned to form the source electrode layer (terminal) 102 and the gate electrode layer (terminal). The terminal) 103 is formed. In the preferred method of the present invention, a third mask is required for such pattern formation. Further, the common drain electrode 105 is provided by the metal coating of the substrate 62, but in this case, pattern formation is unnecessary.

In order to form an ohmic short circuit between the source region 88 and the base region 76, the entire element is heat treated to produce a microalloy as shown in FIG. More specifically, a microalloy spike 104 is created that extends completely through the source region 88 and partially into the base region 76. It goes without saying that the process variables must be selected correctly to obtain the desired result. It should be noted that, for purposes of illustration and not limitation of the scope of the invention, for an N ^{+ type} source region 88 having a thickness of less than about 0.7 microns, a nitrogen atmosphere is needed to produce the desired degree of microalloy. It is sufficient to carry out heating at 45 ° C. for 1 hour.

To describe the mechanism of microalloy formation, the silicon in the source region 88 and the base region 76 dissolves in the aluminum of the source terminal 102, resulting in the microalloy spike 104 being formed downwards. .. The degree of microalloy formation can be varied by controlling several variables. Examples of such variables include (1) the type of metal used for the source electrode (terminal) 102 (pure aluminum or any aluminum-silicon alloy), (2) the temperature and time of heat treatment, and the atmosphere.
(3) substrate crystallographic orientation and surface state, and (4) source and base diffusion depth and concentration.

According to such a micro-alloy generation technique, as can be seen from FIG. 9, a required ohmic short circuit portion is formed between the source region 88 and the base region 76, so that it is necessary in the conventional MOS-FET. The short-circuit piece (FIG. 2) that has been used will be eliminated. As a result, not only the masking step for forming it becomes unnecessary, but also the size of the unit cell is reduced.

According to the present invention, the power M is also formed by forming a V-shaped groove using a known preferential etching technique.
A second method is also provided for forming a source-base short in the OS-FET. In the second method according to the present invention, the processing as described above with reference to FIGS. However, the wafer 60 is selected to exhibit a <100> crystallographic orientation.

Referring to FIG. 10 following FIG. 6 described above, the V-shaped groove 106 is formed by preferentially etching the source region 88 and the base region 76. Such a V-shaped groove 106 completely penetrates the source region 88 and its bottom 108 is partially in the base region 76.
It extends to the inside. Various preferential etchants are known, but any of them can be used in the practice of the invention. An example of a suitable etchant is potassium hydroxide and isopropanol mixed in a ratio of about 3: 1. This mixture is about 60 ℃
If kept at, corrodes silicon at a rate of 5 microns per hour. Other crystal orientation dependent etchants may be used in the practice of the invention. For example, Applied Physics Letters (Applied)
Physics Letters) Volume 26 195-1
Appropriate etchants are described in Don L. Kendall's article "Etching to Form Extremely Narrow Grooves in Silicon", page 98 (1975). There is.

According to the invention, no masking step is required for such etching. This is because, even after the parallel beam ion etching step of FIG. 6, a plurality of insulating layers, preferably silicon nitride or silicon dioxide as described above, protect the remaining areas. Then, although not shown in connection with such a V-groove etching method of the present invention, a second mask 96 is placed as in the case of FIG. 7, whereby a gate terminal window opening 98 and 100 is formed. afterwards,
The second mask 96 is removed.

Finally, as shown in FIG. 11, a metal coating is deposited on the device, preferably by vapor deposition. Then, the source electrode layer (terminal) and the gate electrode layer (terminal) are formed by performing pattern formation as described above with reference to FIG. As a result of the presence of the V-shaped groove 106,
The source electrode 102 has a source region 88 and a base region 7.
It makes ohmic contact with both 6's.

The self-alignment technique of the present invention has been described above. The above technique for forming a source-base short circuit in a power MOS-FET has been described above with reference to FIGS. 1 and 2. It goes without saying that the method can be applied to other methods similar to the method. While particular embodiments have been illustrated herein, it will be apparent to those skilled in the art that various other modifications are possible.
For example, if the base region 76 and the source region 88 are introduced into the drain region 64 of the power MOS-FET of FIG. 9 or 11 by the ion implantation method instead of the diffusion operation as described above, the silicon dioxide layer of FIG. 6
After removing 8 as shown in FIG. 4, it becomes unnecessary to apply a silicon dioxide layer 92 as shown in FIG. This is because the ion implantation method can penetrate the silicon dioxide layer 68 and introduce appropriate impurities into the drain region 64. Further, the source electrode and the drain electrode of the power MOS-FET can be provided by the sputtering technique instead of the vapor deposition technique as described above. Thus, it is to be understood that all such variations are encompassed by the appended claims without departing from the spirit and scope of the invention.

[Brief description of drawings]

1 is a conventional double-diffused power MOS-FET showing a manufacturing stage in which a diffusion barrier for the base short piece still exists.
Sectional view of.

FIG. 2 Substantially completed conventional double diffused power MO
Sectional drawing of S-FET.

FIG. 3 is a self-aligned power MOS-F according to the present invention.
Sectional drawing which shows the semiconductor wafer after performing an initial process in order to form an ET cell.

FIG. 4 is a cross-sectional view showing the state of the cell after the upper four layers are subsequently removed by etching and the first mask is removed.

FIG. 5 is a cross-sectional view showing a wafer after performing base diffusion and source diffusion.

FIG. 6 is a cross-sectional view showing a state where an oxide layer formed on a source region is removed by a parallel beam.

FIG. 7 is a cross-sectional view showing a state where a gate electrode is exposed by a second masking step and subsequent etching.

FIG. 8 is a cross-sectional view showing a metal film for a source terminal and a gate terminal, which is installed by using a third masking step.

FIG. 9 is a side sectional view showing a source-base short-circuit portion integrally formed by the microalloy generation technique of the present invention.

FIG. 10 is a side sectional view showing a V-shaped groove formed by preferential etching according to another embodiment of the present invention.

FIG. 11 is a side sectional view showing a cell having a source-base short-circuit portion integrally formed by installing a metal coating in a V-shaped groove.

[Explanation of Codes] 60 Wafer 62 Substrate 64 Drain Region 66 Main Surface 68 Gate Insulating Layer (First Insulating Layer) 70 Gate Electrode Layer (Polycrystalline Silicon Layer) 72 Second Insulating Layer 74 Third Insulating Layer 76 First region (base region) 77 First mask 78 First mask window 79 Outer periphery of first region 80 Opening of third insulating layer 82 Opening of second insulating layer 84 Opening of gate electrode layer 86 Opening of first insulating layer 88 Second region (source region) 90 Band 92 Silicon dioxide layer 93 Extension 94 Parallel beam 96 Second mask 98 Opening of third insulating layer 100 Opening of second insulating layer 102 Source Terminal 103 Gate Terminal 104 Micro Alloy Spike 105 Drain Terminal 106 V-Shaped Groove 108 Bottom

Claims (15)

[Claims] 1. A semiconductor substrate including a drain region of one conductivity type and having a main surface, (b) a drain terminal electrically connected to the drain region, and (c) in the drain region. A first diffusion region of opposite conductivity type that is formed to form a base region and that has a finite lateral extent and that has an outer periphery that terminates in the major surface; and (d) inside the first diffusion region. Fully included and said first
Forming a source region having a lateral extent and depth smaller than that of the diffusion region, terminating in the main surface, and being spaced apart inside the outer periphery of the first diffusion region. A second one of the one conductivity type having an outer periphery, wherein the first diffusion region exists as the strip of the opposite conductivity type between the source region and the drain region in the main surface. Diffusion region, (e) a source terminal electrically connected to the second diffusion region,
(F) a gate insulating layer disposed on the main surface so as to cover at least the strip-shaped portion of the first diffusion region, (g)
A conductive gate electrode disposed on the gate insulating layer so as to laterally cover at least the strip portion of the first diffusion region, and (h) a gate terminal electrically connected to the gate electrode. And (i) an ohmic short-circuit portion formed below the main surface, between the first diffusion region and the second diffusion region, and further, the second diffusion region and the second diffusion region. A V-groove formed by preferentially etching the first diffusion region and having a bottom portion partially extending into the first diffusion region, wherein both the source terminal and the ohmic short are provided in the first diffusion region; A double electrode formed in the V-shaped groove so as to cover the second diffusion region and formed by a metal electrode in ohmic contact with both the second diffusion region and the first diffusion region. Diffusion type power MOS -FE
T. 2. The double diffused power MOS-FET according to claim 1, wherein the metal electrode is made of aluminum. 3. A double diffused power MOS-FET of the type including a plurality of unit cells formed on a single semiconductor substrate and electrically connected in parallel to each other,
(A) a semiconductor substrate including a common drain region of one conductivity type and having a main surface, (b) a common drain terminal electrically connected to the drain region, (c) formed in the drain region A first diffusion region group of opposite conductivity type, which forms a base region corresponding to each of the unit cells, and which has a finite lateral expansion and has an outer periphery terminating in the main surface, (d) The first to do
Of the diffusion regions are formed to have a lateral extent and a depth smaller than that of the corresponding first diffusion region, the source region corresponding to each of the unit cells. Has an outer periphery that terminates in the main surface and is spaced apart inside the outer periphery of the corresponding first diffusion region, and the corresponding first diffusion region in the main face corresponds to A second diffusion region group of the one conductivity type, the second diffusion region group of the one conductivity type being present as a strip portion of the opposite conductivity type between the source region and the drain region, (e) with respect to the second diffusion region group, A common source terminal electrically connected, (f) a gate insulating layer arranged on the main surface so as to cover at least the strip of the first diffusion region group, (g) at least the first diffusion Area group above To cover Jo portion laterally, the common gate electrode of the arranged conductive to the gate insulating layer,
(H) a gate terminal electrically connected to the common gate electrode, and (i) the first diffusion region and the second diffusion region of each of the unit cells formed below the main surface. An ohmic short between the diffusion region and the second diffusion region and the first diffusion region, each of which is formed by preferential etching and the bottom of which is partially corresponding. A second V-groove extending into the first diffusion region, wherein both the common source terminal and the ohmic short are installed in the V-groove so as to cover the second diffusion region; A double diffusion type power MOS-FET, which is formed by a metal electrode in ohmic contact with both the diffusion region and the first diffusion region. 4. The double diffused power MOS-FET according to claim 3, wherein the metal electrode is made of aluminum. 5. (A) A drain region of one conductivity type is included,
A silicon semiconductor wafer substrate having a main surface and exhibiting <100> crystal orientation is prepared, and (B) a first surface is provided on the main surface.
For sequentially forming an insulating layer, a conductive gate electrode layer, a second insulating layer and a third insulating layer, and (C) finally defining at least one base region and at least one source region. The first mask having a window is attached to the third mask.
(D) at least the third insulating layer, the second insulating layer and the gate electrode layer are successively etched to form an area defined by the window of the first mask. Forming an opening therein and undercutting the gate electrode layer, (E) removing the first mask, and (F) passing through the opening defined by the first mask and of opposite conductivity type. Introducing an impurity suitable for forming a region into the drain region to define a base region having a lateral extent partially dependent on the size of the opening defined by the first mask. Forming a first region of opposite conductivity type,
(G) By introducing an impurity suitable for forming the region of one conductivity type into the base region through the opening which is also limited by the first mask, the inside of the base region is completely removed. Forming a source region such that it is within said major surface so that said first region is present between said source region and said base region as said opposite conductivity type strip. Forming a second region of (H) forming a silicon dioxide layer on at least the sidewall of the opening penetrating the gate electrode layer, and (I) penetrating the gate electrode layer on the sidewall of the opening. Removing the insulating layer on the surface of the source region in the area within the opening of the third insulating layer defined by the first mask without removing , (J) A V-shape that penetrates the second region and has its bottom partly extending into the first region by preferentially etching the second region and the first region. Forming a groove and (K) installing a second mask having a window to define at least one gate contact area on a portion of the wafer different from the position of the source region; By sequentially etching the third insulating layer and the second insulating layer to form an opening reaching the gate electrode layer in the area defined by the window of the second mask,
(M) removing the second mask, then (N) depositing an electrode metal on the wafer, and patterning with the third mask to form source and gate terminals, which And the source terminal extends into the V-shaped groove to make ohmic contact with both the second region and the first region. Method of manufacturing FET. 6. The first insulating layer is etched following the step of sequentially etching the third insulating layer, the second insulating layer and the gate electrode layer. The method described. 7. The method of claim 6, wherein a silicon dioxide layer is formed on the surface of the source region following the step of introducing impurities into the base region to form a second region. 8. The method of claim 5, wherein the first insulating layer comprises a single silicon dioxide layer. 9. The method of claim 5 or 8 wherein said second insulating layer comprises a single silicon dioxide layer. 10. The method according to claim 5, wherein the third insulating layer comprises a single silicon nitride layer. 11. The method of claim 5, wherein the step of removing the insulating layer by a parallel beam comprises removing the insulating layer by reactive ion etching with a parallel beam. 12. The step of introducing an impurity into the drain region to form a first region and the step of introducing an impurity into the base region to form a second region diffuses the respective impurities. The method of claim 5, comprising: 13. A semiconductor substrate having (a) a drain region of one conductivity type and having a main surface, (b) a drain terminal electrically connected to the drain region, and (c) in the drain region. A first region of opposite conductivity type formed to form a base region and having a finite lateral extent and having an outer periphery terminating in said major surface; (d) completely within said first region. The source region is formed to have a lateral extent and a depth smaller than that of the first region, the source region being included and terminating in the major surface and being spaced apart from the outer periphery of the first region. The one conductivity type having an outer periphery located in the main surface such that the first region exists between the source region and the drain region as a strip of the opposite conductivity type. The second area of, ( e) a conductive gate electrode and a gate insulating layer arranged on the main surface so as to cover at least the band-shaped portion of the first region in the lateral direction, and (f)
Double diffused power MOS of the type including elements of the gate terminal electrically connected to the gate electrode
In a method of forming a short circuit between a source layer and a base layer of an FET, (A) forming a source terminal by placing an electrode metal on the substrate so as to cover the source region, and then (B). By heating the substrate,
Producing at least one microalloy spike extending from the source terminal through the second region and partially into the first region, such that between the first region and the second region A method of forming an ohmic short circuit portion on the substrate. 14. The method of claim 13, wherein the semiconductor substrate comprises silicon and the source terminal comprises aluminum. 15. (a) A semiconductor substrate including a drain region of one conductivity type, having a main surface, and exhibiting <100> crystal orientation, (b) electrically connected to the drain region. A drain terminal, (c) a first region of opposite conductivity type formed in the drain region to form a base region and having a finite lateral extent and having an outer periphery terminating in the major surface; ) Completely contained within said first region and formed to have a lateral extent and depth smaller than said first region to form a source region and terminate in said major surface and said Having a perimeter located separately inside the perimeter of the first region,
A second region of one conductivity type, wherein the first region exists as a strip of the opposite conductivity type between the source region and the drain region in the main surface;
(E) A conductive gate electrode and a gate insulating layer arranged on the main surface so as to cover at least the band-shaped portion of the first region in the lateral direction, and (f) electrically with respect to the gate electrode. In a method of forming a short circuit between a source layer and a base layer of a double diffused power MOS-FET of the type that includes connected gate terminal elements,
(A) A V-shaped groove that penetrates the second region and has its bottom partly extending into the first region by preferentially etching the second region and the first region. And then (B) depositing an electrode metal on the substrate and patterning with a mask to form a source terminal and a gate terminal, whereby the source terminal is placed in the V-shaped groove. A method comprising stretching to make ohmic contact with both the second region and the first region.