JPH01235277A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPH01235277A JPH01235277A JP6254588A JP6254588A JPH01235277A JP H01235277 A JPH01235277 A JP H01235277A JP 6254588 A JP6254588 A JP 6254588A JP 6254588 A JP6254588 A JP 6254588A JP H01235277 A JPH01235277 A JP H01235277A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- electrode
- source region
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 239000000956 alloy Substances 0.000 claims abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に電力スイッチング素子
として用いられる縦型パワー電界効果トランジスタ（Ｍ
ＯＳ ＦＥＴ）に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to a vertical power field effect transistor (M
OS FET).
従来、この種の縦型ＭＯ８ＦＥＴは第２図に示す様にド
レイン領域として作用するＮ型半導体基板１にＰ型ベー
ス領域２を有し、その中に環状のＮ型ソース領域３を備
え、ベース領域２の周辺上にゲート酸化膜５を介してポ
リシリコンのゲート電極４が設けられ、アルミニウムの
ソース電極６はソース領域３とベース領域２と接続して
いる。Conventionally, this type of vertical MO8FET has a P-type base region 2 in an N-type semiconductor substrate 1 which acts as a drain region, as shown in FIG. A polysilicon gate electrode 4 is provided on the periphery of the region 2 via a gate oxide film 5, and an aluminum source electrode 6 is connected to the source region 3 and the base region 2.
特にソース電極６はソース領域３と合金層８を介して抵
抗性接触している。この時ソース領域３の深さが約１ミ
クロンと合金層８を深さよりも深くソース電極３がベー
ス領域２と抵抗性接触するためにバックゲート領域７が
設けられている。そのためソース領域３を幅広くとる構
造となっていた。In particular, the source electrode 6 is in resistive contact with the source region 3 via the alloy layer 8 . At this time, the back gate region 7 is provided so that the depth of the source region 3 is about 1 micron, which is deeper than the depth of the alloy layer 8, and the source electrode 3 comes into resistive contact with the base region 2. Therefore, the structure has been such that the source region 3 is wide.
上述した従来の縦型ＭＯ８ＦＥＴはソース電極６がベー
ス領域２と抵抗性接触を取るためバックゲート領域７が
設けられているのでソース領域６が幅広くなり素子寸法
が小さくできないという欠点がある。 。The above-mentioned conventional vertical MO8FET has a drawback that the back gate region 7 is provided so that the source electrode 6 makes resistive contact with the base region 2, so the source region 6 becomes wide and the device size cannot be reduced. .
本発明の縦型ＭＯ８ＦＥＴは、ソース電極となるアルミ
ニウムがアルミスパイクする深さより浅いソース領域を
有している。The vertical MO8FET of the present invention has a source region that is shallower than the depth of the aluminum spike formed by the aluminum serving as the source electrode.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
１はドレイン部となるＮ−型シリコン基板、２はチャネ
ル部となるＰ型ベース領域、３はソーストなるＮ＋型層
、これらＰ型層２及びＮ＋型層３はゲートポリシリコン
４をマスクとして不純物２重拡散を行うことによりセル
ファライン（自己整合的）にチャネル長さを規定するこ
とができる。Ｎ＋型層のソース領域３をアルミニウムの
ソース［極６がアルミスパイクするよりも例えばヒ素を
不純物として浅く、約０．４μｍに形成する。ソース電
極６はソース領域３の表面接合部より０．５μｍ以上望
ましくは１μｍ以上離しておく必要がある。1 is an N- type silicon substrate which becomes a drain part, 2 is a P-type base region which becomes a channel part, 3 is an N+ type layer which becomes a source, and these P-type layer 2 and N+-type layer 3 are impurity-doped using gate polysilicon 4 as a mask. By performing double diffusion, the channel length can be defined in a self-aligned manner. The source region 3 of the N+ type layer is formed to be shallower, about 0.4 μm, using an impurity of arsenic, for example, than the aluminum spike electrode 6 is made of aluminum. The source electrode 6 must be separated from the surface junction of the source region 3 by at least 0.5 μm, preferably at least 1 μm.
ソース電極６はアルミスパイク等の合金化層８をソース
領域３と形成するが、この合金化層８によってソース電
極６はベース領域と抵抗性接触するため、第２図の従来
例のバックゲート領域７を省略できる。このため、ソー
ス領域３を薄くできることとあいまってソース領域３の
小型化が達成でき、素子全体の小型化を実現できる。The source electrode 6 is formed by forming an alloyed layer 8 such as an aluminum spike with the source region 3. Because the alloyed layer 8 makes the source electrode 6 resistive contact with the base region, the back gate region of the conventional example shown in FIG. 7 can be omitted. Therefore, the source region 3 can be made thinner, the source region 3 can be made smaller, and the entire device can be made smaller.
なお、本実施例をＰチャネル型に適用しても同様の効果
が得られる。Note that similar effects can be obtained even if this embodiment is applied to a P-channel type.
以上説明したように本発明はソース領域をソース電極の
アルミニウムがアルミスパイクする深さより浅く形成す
ることでバックゲート領域を省くことができ、素子寸法
を小さくすることができる。またチャネル長さを同一に
設定するとベース領域も浅くなりより小さな素子寸法と
することができる。As explained above, in the present invention, by forming the source region to be shallower than the depth at which the aluminum of the source electrode spikes, the back gate region can be omitted and the device size can be reduced. Furthermore, if the channel lengths are set to be the same, the base region will also be shallower, allowing for smaller device dimensions.
第１図は本発明の縦型ＭＯ３ＦＥＴの縦断面図、第２図
は従来の縦型ＭＯ３ＦＥＴの縦断面図である。
１・・・・・・Ｎ型半導体基板、２・・・・・・Ｐ型ベ
ース領域、３・・・・・・Ｎ型ソース領域、４・・・・
・・ゲートポリシフン、５・・・・・・ゲート酸化膜、
６・・・・・・ソースアルミ電極、７・・・・・・Ｐ型
バックゲート領域、８・・・・・・アロイ層。
代理人 弁理士 内 原 音FIG. 1 is a vertical cross-sectional view of a vertical MO3FET of the present invention, and FIG. 2 is a vertical cross-sectional view of a conventional vertical MO3FET. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2... P-type base region, 3... N-type source region, 4...
...Gate polysiphon, 5...Gate oxide film,
6... Source aluminum electrode, 7... P-type back gate region, 8... Alloy layer. Agent Patent Attorney Oto Uchihara
Claims (1)
アルミニウムがシリコンと合金層を形成する深さより浅
く形成されたソース領域を含むことを特徴とする縦型電
界効果トランジスタ。A vertical field effect transistor comprising a source region formed at a depth shallower than the depth at which aluminum, which serves as a source electrode, forms an alloy layer with silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6254588A JPH01235277A (en) | 1988-03-15 | 1988-03-15 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6254588A JPH01235277A (en) | 1988-03-15 | 1988-03-15 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01235277A true JPH01235277A (en) | 1989-09-20 |
Family
ID=13203311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6254588A Pending JPH01235277A (en) | 1988-03-15 | 1988-03-15 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01235277A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002289853A (en) * | 2001-03-28 | 2002-10-04 | Rohm Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2002314078A (en) * | 2001-04-17 | 2002-10-25 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| JP2002373988A (en) * | 2001-06-14 | 2002-12-26 | Rohm Co Ltd | Semiconductor device and manufacturing method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58138076A (en) * | 1982-01-04 | 1983-08-16 | ゼネラル・エレクトリツク・カンパニイ | Power mos-fet with shortcircuit between source and base and method of producing same |
| JPS6184867A (en) * | 1984-09-27 | 1986-04-30 | ゼネラル・エレクトリック・カンパニイ | Manufacture of igfet |
-
1988
- 1988-03-15 JP JP6254588A patent/JPH01235277A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58138076A (en) * | 1982-01-04 | 1983-08-16 | ゼネラル・エレクトリツク・カンパニイ | Power mos-fet with shortcircuit between source and base and method of producing same |
| JPS6184867A (en) * | 1984-09-27 | 1986-04-30 | ゼネラル・エレクトリック・カンパニイ | Manufacture of igfet |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002289853A (en) * | 2001-03-28 | 2002-10-04 | Rohm Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2002314078A (en) * | 2001-04-17 | 2002-10-25 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| JP2002373988A (en) * | 2001-06-14 | 2002-12-26 | Rohm Co Ltd | Semiconductor device and manufacturing method therefor |
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