CA1216968A - Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short - Google Patents
Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said shortInfo
- Publication number
- CA1216968A CA1216968A CA000461632A CA461632A CA1216968A CA 1216968 A CA1216968 A CA 1216968A CA 000461632 A CA000461632 A CA 000461632A CA 461632 A CA461632 A CA 461632A CA 1216968 A CA1216968 A CA 1216968A
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- Prior art keywords
- region
- implant
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- shorting
- source
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
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- 239000005630 Diquat Substances 0.000 description 3
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/6634—Vertical insulated gate bipolar transistors with a recess formed by etching in the source/emitter contact region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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Abstract
INSULATED-GATE SEMICONDUCTOR DEVICE
WITH IMPROVED BASE-TO-SOURCE
ELECTRODE SHORT AND METHOD OF FABRICATING SAID SHORT
Abstract of the Disclosure Insulated-gate semiconductor devices, such as MOSFETs or IGTs, include an implant shorting region adjoining both base and source regions with the implant shorting region being conductively coupled to the source electrode so as to implement a base-to-source electrode short. The implant shorting region can be formed without a specially-aligned mask by utilizing the gate electrode as an implant mask.
WITH IMPROVED BASE-TO-SOURCE
ELECTRODE SHORT AND METHOD OF FABRICATING SAID SHORT
Abstract of the Disclosure Insulated-gate semiconductor devices, such as MOSFETs or IGTs, include an implant shorting region adjoining both base and source regions with the implant shorting region being conductively coupled to the source electrode so as to implement a base-to-source electrode short. The implant shorting region can be formed without a specially-aligned mask by utilizing the gate electrode as an implant mask.
Description
~Z~
-1- RD-15,042 INSULATED-GATE SEMICONDUCTOR DEyIcE
WITH IMPROVED BASE-TO-SOURCE
-BackgrQund and 5u~mary of the Invention The present invention relates to an insulated gate semi-conductor device having a base-to-source electrode short and to a method of fabricating such short.
Insulated-gate semiconductor devicesare devices employing a gate, or control electrode, lnsulatingly spaced from semiconductor material, for altering the conductivity of the semiconductor material beneath the gate. Typical insulated-gate devices include Metal-Oxide-Semiconductor Field-Effect Transistors tMosFETs)~ which are well-kno.~n devices, and Insulated Gate Transistors (IGTs), tformerly designated "Insulated Gate Rectifiers") such as described in an article by B.J. Baliga et al., "The Insulated Gate Rectifier tIGR):
~ New Power Switching Device,'IDEM tDecember 1982) pages 264-207.
Both MOSFETs and IGTs are typically comprised of a multitude of repeated, individual "cells", with device current-carrying capability increasina as cell size is made smaller.
A base-to-source electrode short is typically employed in MOSFETs and IGTs and, most commonly, comprises a portion of the source electrode electrically shorting together a "P", or moderately-doped, P-conductivity type, base region and an "N+", or highly-doped, N-conductiyity type, source region. This helps to ensure that the base-to-source P-N junction between the P base regiGn and the N+ source region does not become forward biased (due to hole current in the P+ region, -Eor example~ to such an extent that the N~
~' h ~ 96~
RD-15,042 source commences electron injection into the P base region, across the base-to-source P-N junction. Such electron injection is deleterious to both .UOSFETs and IGTs. I~ an IGT~ for example, such electron injection re~ults in the device latching into an "on", or current-conducting state, as in a thyristsr, with attendant loss oi' gate control over device current.
Even when using the foregoing base-to-source electrode short of the prior art, hole current in the P
10 base reglon may still cause a voltage drop along the base-to-source P-N junction which is sufficient to result in undesired electron injection by the N~ sourGe region.
One prior art technique directed to minimizing the hole current voltage drop in the P base region, and thus the 15 likelihood of undesired electron injection by the N+
source region, is to form, through the use of a specially aligned mask, a "P+", or highly-doped,P-conductivity type, shorting region in a selected portion of the P
base region adjacent the base-to-source P-N junction.
20 Hole current that flows in the P~ shorting region accordingly creates only a low voltage drop therein and is thus less like1y to result in undesired electron injection by the N+ source region.
A drawback o~ the foregoing technique for 25 minlmizing the hole current voltage drop along the base-to-short P N junction is in the requirement for a specially-aligned mask in forming the P~ shorting region. This significantly adds to fabrication expense and necessitates a larger cell size, resulting in a reduced current-carrying capability for the device.
Accordingly, it is an object of the present invention to provide an insulated-gate semiconductor device with a highly effective base-to~source eleclrode short.
~LZ~6~68 - 3 - RD 15,042 A further object of the invention is to provide an insulated-gate semiconductor device having a base-to-source electrode short and having a reduced cell size compared -to prior art devices.
Another object of the invention is to provide a semiconductor device having a base-to-source electrode short that can be fabricated with only a marginal increase in fabrication complexity and cost.
A still further object of the invention is to provide a method of fabricating an improved shorting region in a semiconductor device having a base-to-source electrode short.
In accordance with a preferred form of the invention, there is pxovided a semiconductor device with an improved base-to-source electrode short.
The device comprises a semiconductor wafer having a substantially-planar upper surface and including:
an N voltage-supporting layer; a P base region overlying the N+ voltage-supporting layer and having a portion terminating in proximity to the wafer upper surface;
and an N+ source region overlying the P base region.
The semiconduc-tor device includes a gate above the wafer and insulatingly spaced therefrom and a source electrode situated above the wafer and conductively coupled to the N+ source region. A P+ implant shorting region is included in the wafer with at least the major portion of the upper surface thereof being situated beneath the plane of the wafer upper surface~ The implant shorting region adjoins the N+ source and base regions, has a higher conductivity than the P
base region and is conductively coupled to the source electrode so as to complete the short between the P base region and the source electrode.
In accordance with a further, preferred form of the invention, there is provided a method of fabri-~ Z~ ~96~3 RD-15,042 ~4--cating an implant shorting region in an insulated-gate semiconductor device. The method includes the step o~
providing a semiconductor wa~er having a substan-tially-, pla~ar upper surface and including, in successively adjoini~g relationship, an N~ source region, a P base regio~, and an N voltage-supporting layer. A gate insulatingly spaced from the wafer is formed atop the waier. ~he gate is utilized as an integral part of an implant mask while implanting into the wafer a P~
implant shorting region at a sufficiently high energy level that the P~ implant shorting region is located, at least in major part, beneath the wafer upper surface and ad30ining both the M~ source and P base regions. A
source electrode is conductively connected to the N~
source region and the P+ implant shorting region.
Brief Description of the Drawin~s The features of the invention deemed to be novel are defined inthe appended claims. The invention itself, however~ as to both organization and method of operation, together with further objects and advantages thereof, ~ill be better understood by referring to the ~ollowing description in connection with the accompanying dra~ing gigures, in which Fig. 1 is a schematic~ cross~sectional view of a prior art semiconductor device;
Fig. 2 is a schematic cross-sectional view of a ~abrication step o~ a semiconductor device in accordance with the present invention;
Fig. 3 is a detailed view of a portion of the semiconductor device of Fig. ~ together with a dopant profile graph for such de~ail view;
Fig. 4 is a schematic, cross-sectional view of a further processing step o~ the semiconductor device in accordance with the invention;
69~8 RD-15,042 Fig. 5 is a ~chematic, cross-sectional view of the completed semiconductor device of the invention;
Fig. 6 is a schematic, cross-sectional view o~ a processing step of a further semiconductor device in accordan~e with the present invention;
Fig. 7 ls a view similar to Fig. 6 showing a further processing step for the device of Fig. 6;
Fig. 8 is a schematic, cross sectional view oi the semiconductor device o~ Figs. 6 and 7 when completed;
Fig. 9 is a schematic, tridimensional view in cross section oi a modification of the semiconductor device of Figs. 6-8 with a portion of the source electrode broken away to facilitate viewing of details of the modifi.ed device;
Fig. 10 is a schematic, tridimensional view in cross section oL another semiconductor device in accordance with the present invention, with a portion of the source electrode broken away to facilitate viewing of interior details of the device; and Fig. 11 is a schematic, cross-sectional view of a semiconductor device in accordance with a still further embodiment of the present invention.
~escription of the Preferred Embodiments To aid in understanding the electrical ~unction performed by the implant shorting region of the present invention, a prior art semiconductor device is illustrated and described in connection with Fig. 1, which depicts a cross-section of a semiconductor device lOo Device 10 includes a semiconductor wafer 1~ with substantially planar upper and lower surfaces 14 and 16, respectively. A gate 18, such as polysilicon highly doped with ~-conductivity type dopant impurities, L65~
RD-15~042 is insulatingly spaced ~rom wafer 12 by the lower portio~ of insulation layer 20, which is illus~rated in simplified form as comprising one layer, but which may include, in actuality, one or more layers of silicon dioxide and silicon nitride, by way of example.
Also included in device 10 are an upper or source electrode 22 and a lower or drain electrode 24.
Wafer l2 includes a P base region 26, which when viewed ~rom above, may be rectangular, circular, or elongated, by way of example. Gate 1~ overlies portion 26' of P base 26 and, thus, when viewed from above, has the same sh;lne~ in plan view, as the peri-phery of P base 26. Overlying P base region 26 is an N~ source region 28 that for~ a P-~ junction 29 ~here-with. N~ source region 28 adjoins source electrode 22 and typically ~orms a closed loop within P base region 26 of the same shape as the periphery of P base region 26 whe~ vie~ed from ab~ve; accordingly, the right hand N+ region is part of the loop of N+ source region 28.
An N voltage-supporting region 30 underlies P base region 26 and, in turn 7 overlies a lowermost region 32, which, in turn, overlies drain electrode 24. Region 32 as illustrated, may be highly-doped to P conductivity type or to N-conductivity type, the former resulting in device 10 constituting an I~T an~ the latter resulting in ~evice constituting a ~D~ET~ The electrode ~ource device l0 typically comprises ~ cell th~t is repeated m~ny times in a completed device 10, with the cells hsaring a common gate 18, a com~on source elec-trode 2~, and a cam~n drain electrode 24.
The operation of ~evice 10 as an IGT, that is, with lower~ost region 32 being of P-conductivity type, is now considered. With gate 18 biased with a sufficient-ly high voltage (with respect to source electrode 22), portion 26' of P base region 26, adjacent to gate 13, ~6~G~
RD-15,042 becomes depleted of holes (or positive charge current carriers) and populated with electrons so as to form what is kno~n as an "inversion" channel that is con-ductive to electrons. Then, with drain electrode 24 biased more positiYely than source electrod0 22, electron current 3~ (shown schematlcally) flows from source electrode 22 to N voltage-supporting region 30 via N~ source region 28 and the inversion channel in portlon 26'. Holes are injected into N voltage-supporting layer 30 b~ P~ lowermost region 32 via a hole current path 34 when P-N junction 33, e~tant between these layers~ becomes sufficien~ly forward biased (about 0.5 volts for silicon). A portion of hole current 34 recombines with electron current 32 where their paths intersect (~or example, at location 36), and this recombination accounts for the bulk of device current, However, a fraction of hole current 34, as represented by hole current path 38 (shown schematically), does not recombine with elec~rons from ~o electron current path 32 but instead flows to source electrode 22 via P L~ase region 26. Hole current 38 causes a~oltage drop along P-N junction 29, between locations A and B, and i~ this voltage exceeds about 0~5 volts for silicon devices, N~ source region 28 is induced to inject electrons into P base region 26, and device 10 thereupon latches into an on state, in the same way as a thyristor 3 with attendant loss of control of device current by gate 18.
To reduce the voltage drop along P-N junction 29 caused by hole current 38, a P~ shorting region 42 9 shown in phantom, is provided in wafer 12 in accordance with the prio. art. Region ~2 is highly conduc t ive to holes, and, consequcntly, the voltage drop along P-N
junction 29 ~rom location C to location B i5 extremely ;e'36E~
RD-15,042 low. The implementation of P~ shorting region ~2 has two significant disadvantages, howevcr. First a specially~aligned mask (not shown) is typically used in the process of ~abricating P~ shorting region 42.
Second, P base region 26 mu~t be sufficiently large to accommodate alignment tolerance for the ~oregoing mas~, resulting in a larger cell size and lower current-carrying capability in device 10. These disadvantages are avoide~ by the present invention, which is described in Fig. 2 and the succeeding drawings figures~
Considering now ~igure 2, there is illustra-ted i~ cross-section one step in the fabrication process of a s~miconductor device 50 in accordance with the present invention. Device 50 includes a wafer o~ semi-conductor material 52, such as silicon, a gate 58 such as polysilicon highly doped with N-conductivity type impurities, and an insulating layer 60 9 the lower portion of which insulatingl~ spaces gate 58 from wafer 52.
Insulating layer 60 is illustrated in simpli~ied form as comprising only one layer, but may, in actuality ~omprise one or more layers of silicon dioxide and - silicon nitride, by way of example. Wafer 52 includes a lowermost region 6~, which may be of P-conductivity type (~or an I&T) or N conductivity type (for a hIOSFET);
an N voltage-supporting layer 64 overlying lowermost layer 62; and a P base region 68 overlying N voltage-supporting layer 64 and having a portion 68' terminating in proximity to gate 58 and~ which, as viewed from above, may be rectangular, circular or elongated, by way of example. Wafer 52 further includes an N~ source region 70 overlying P base region 68, with the upper-most portion o~ region 70 terminating at wafer upper sur~ace 54. ~ith P base portion ~8' terminatin~ at wa~er upper surface 54, as illustrated, device 50 RD-15,042 ~9--constitutes a normally-off device in that the gate 58 must be biased in order to turn on device 50. If, in an alternative embodiment, an N-conductivity region (not shown) were interposed between P base portion 68' and wafer upper surface 54 and were interconnected with both N voltage-supporting reglon 64 and N~ source region 70, device 50 would constitute a normally-on device, that is, electron current would flow through such N-conductivity regiorl unless gate 58 were appropriately biased so as to deplete the N-conductivity type region of electrons.
In accordance with the present invention, P~
implant shorting region 72 is formed in wafer 52 by implantlng a P-conductivity type dopant through wafer upper surface 54 while utilizing gate 58 and the portion of insulating layer 60 thereabove as an implant mask.
Accordingly, without the need for a specially-aligned mask, P+ implant shorting region 72 can be readily formed and~ advantageously permits a small sized P base region 68 as viewed ~rom abo~e since P base region 68 need not be made large in order to accommodate an alignment tolerance for a specially-aligned mask. Consequently, device 50 can have a smaller cell size,resulting in greater current-carrying capability thereof. P+ imp~ant shorting region 72 is situated between N+ source region 70 and P base region 68. P~ shor~ing region 72 may extend downwardly into P base region 68 more so than as illustrated (Figure 2), resulting ~n a relatively wide margin of tolerance in selecting a suitable implant energy for forming such implant shorting reglon.
An exemplary procedure for forming P+ im~lant shor-ting region 72 is now described in connection wi~h Figure 3, which depicts in an enlarged detail view the ~2~
~D-15,042 center portion of P~ implant shorting regioa 72 o~ Fig.
-1- RD-15,042 INSULATED-GATE SEMICONDUCTOR DEyIcE
WITH IMPROVED BASE-TO-SOURCE
-BackgrQund and 5u~mary of the Invention The present invention relates to an insulated gate semi-conductor device having a base-to-source electrode short and to a method of fabricating such short.
Insulated-gate semiconductor devicesare devices employing a gate, or control electrode, lnsulatingly spaced from semiconductor material, for altering the conductivity of the semiconductor material beneath the gate. Typical insulated-gate devices include Metal-Oxide-Semiconductor Field-Effect Transistors tMosFETs)~ which are well-kno.~n devices, and Insulated Gate Transistors (IGTs), tformerly designated "Insulated Gate Rectifiers") such as described in an article by B.J. Baliga et al., "The Insulated Gate Rectifier tIGR):
~ New Power Switching Device,'IDEM tDecember 1982) pages 264-207.
Both MOSFETs and IGTs are typically comprised of a multitude of repeated, individual "cells", with device current-carrying capability increasina as cell size is made smaller.
A base-to-source electrode short is typically employed in MOSFETs and IGTs and, most commonly, comprises a portion of the source electrode electrically shorting together a "P", or moderately-doped, P-conductivity type, base region and an "N+", or highly-doped, N-conductiyity type, source region. This helps to ensure that the base-to-source P-N junction between the P base regiGn and the N+ source region does not become forward biased (due to hole current in the P+ region, -Eor example~ to such an extent that the N~
~' h ~ 96~
RD-15,042 source commences electron injection into the P base region, across the base-to-source P-N junction. Such electron injection is deleterious to both .UOSFETs and IGTs. I~ an IGT~ for example, such electron injection re~ults in the device latching into an "on", or current-conducting state, as in a thyristsr, with attendant loss oi' gate control over device current.
Even when using the foregoing base-to-source electrode short of the prior art, hole current in the P
10 base reglon may still cause a voltage drop along the base-to-source P-N junction which is sufficient to result in undesired electron injection by the N~ sourGe region.
One prior art technique directed to minimizing the hole current voltage drop in the P base region, and thus the 15 likelihood of undesired electron injection by the N+
source region, is to form, through the use of a specially aligned mask, a "P+", or highly-doped,P-conductivity type, shorting region in a selected portion of the P
base region adjacent the base-to-source P-N junction.
20 Hole current that flows in the P~ shorting region accordingly creates only a low voltage drop therein and is thus less like1y to result in undesired electron injection by the N+ source region.
A drawback o~ the foregoing technique for 25 minlmizing the hole current voltage drop along the base-to-short P N junction is in the requirement for a specially-aligned mask in forming the P~ shorting region. This significantly adds to fabrication expense and necessitates a larger cell size, resulting in a reduced current-carrying capability for the device.
Accordingly, it is an object of the present invention to provide an insulated-gate semiconductor device with a highly effective base-to~source eleclrode short.
~LZ~6~68 - 3 - RD 15,042 A further object of the invention is to provide an insulated-gate semiconductor device having a base-to-source electrode short and having a reduced cell size compared -to prior art devices.
Another object of the invention is to provide a semiconductor device having a base-to-source electrode short that can be fabricated with only a marginal increase in fabrication complexity and cost.
A still further object of the invention is to provide a method of fabricating an improved shorting region in a semiconductor device having a base-to-source electrode short.
In accordance with a preferred form of the invention, there is pxovided a semiconductor device with an improved base-to-source electrode short.
The device comprises a semiconductor wafer having a substantially-planar upper surface and including:
an N voltage-supporting layer; a P base region overlying the N+ voltage-supporting layer and having a portion terminating in proximity to the wafer upper surface;
and an N+ source region overlying the P base region.
The semiconduc-tor device includes a gate above the wafer and insulatingly spaced therefrom and a source electrode situated above the wafer and conductively coupled to the N+ source region. A P+ implant shorting region is included in the wafer with at least the major portion of the upper surface thereof being situated beneath the plane of the wafer upper surface~ The implant shorting region adjoins the N+ source and base regions, has a higher conductivity than the P
base region and is conductively coupled to the source electrode so as to complete the short between the P base region and the source electrode.
In accordance with a further, preferred form of the invention, there is provided a method of fabri-~ Z~ ~96~3 RD-15,042 ~4--cating an implant shorting region in an insulated-gate semiconductor device. The method includes the step o~
providing a semiconductor wa~er having a substan-tially-, pla~ar upper surface and including, in successively adjoini~g relationship, an N~ source region, a P base regio~, and an N voltage-supporting layer. A gate insulatingly spaced from the wafer is formed atop the waier. ~he gate is utilized as an integral part of an implant mask while implanting into the wafer a P~
implant shorting region at a sufficiently high energy level that the P~ implant shorting region is located, at least in major part, beneath the wafer upper surface and ad30ining both the M~ source and P base regions. A
source electrode is conductively connected to the N~
source region and the P+ implant shorting region.
Brief Description of the Drawin~s The features of the invention deemed to be novel are defined inthe appended claims. The invention itself, however~ as to both organization and method of operation, together with further objects and advantages thereof, ~ill be better understood by referring to the ~ollowing description in connection with the accompanying dra~ing gigures, in which Fig. 1 is a schematic~ cross~sectional view of a prior art semiconductor device;
Fig. 2 is a schematic cross-sectional view of a ~abrication step o~ a semiconductor device in accordance with the present invention;
Fig. 3 is a detailed view of a portion of the semiconductor device of Fig. ~ together with a dopant profile graph for such de~ail view;
Fig. 4 is a schematic, cross-sectional view of a further processing step o~ the semiconductor device in accordance with the invention;
69~8 RD-15,042 Fig. 5 is a ~chematic, cross-sectional view of the completed semiconductor device of the invention;
Fig. 6 is a schematic, cross-sectional view o~ a processing step of a further semiconductor device in accordan~e with the present invention;
Fig. 7 ls a view similar to Fig. 6 showing a further processing step for the device of Fig. 6;
Fig. 8 is a schematic, cross sectional view oi the semiconductor device o~ Figs. 6 and 7 when completed;
Fig. 9 is a schematic, tridimensional view in cross section oi a modification of the semiconductor device of Figs. 6-8 with a portion of the source electrode broken away to facilitate viewing of details of the modifi.ed device;
Fig. 10 is a schematic, tridimensional view in cross section oL another semiconductor device in accordance with the present invention, with a portion of the source electrode broken away to facilitate viewing of interior details of the device; and Fig. 11 is a schematic, cross-sectional view of a semiconductor device in accordance with a still further embodiment of the present invention.
~escription of the Preferred Embodiments To aid in understanding the electrical ~unction performed by the implant shorting region of the present invention, a prior art semiconductor device is illustrated and described in connection with Fig. 1, which depicts a cross-section of a semiconductor device lOo Device 10 includes a semiconductor wafer 1~ with substantially planar upper and lower surfaces 14 and 16, respectively. A gate 18, such as polysilicon highly doped with ~-conductivity type dopant impurities, L65~
RD-15~042 is insulatingly spaced ~rom wafer 12 by the lower portio~ of insulation layer 20, which is illus~rated in simplified form as comprising one layer, but which may include, in actuality, one or more layers of silicon dioxide and silicon nitride, by way of example.
Also included in device 10 are an upper or source electrode 22 and a lower or drain electrode 24.
Wafer l2 includes a P base region 26, which when viewed ~rom above, may be rectangular, circular, or elongated, by way of example. Gate 1~ overlies portion 26' of P base 26 and, thus, when viewed from above, has the same sh;lne~ in plan view, as the peri-phery of P base 26. Overlying P base region 26 is an N~ source region 28 that for~ a P-~ junction 29 ~here-with. N~ source region 28 adjoins source electrode 22 and typically ~orms a closed loop within P base region 26 of the same shape as the periphery of P base region 26 whe~ vie~ed from ab~ve; accordingly, the right hand N+ region is part of the loop of N+ source region 28.
An N voltage-supporting region 30 underlies P base region 26 and, in turn 7 overlies a lowermost region 32, which, in turn, overlies drain electrode 24. Region 32 as illustrated, may be highly-doped to P conductivity type or to N-conductivity type, the former resulting in device 10 constituting an I~T an~ the latter resulting in ~evice constituting a ~D~ET~ The electrode ~ource device l0 typically comprises ~ cell th~t is repeated m~ny times in a completed device 10, with the cells hsaring a common gate 18, a com~on source elec-trode 2~, and a cam~n drain electrode 24.
The operation of ~evice 10 as an IGT, that is, with lower~ost region 32 being of P-conductivity type, is now considered. With gate 18 biased with a sufficient-ly high voltage (with respect to source electrode 22), portion 26' of P base region 26, adjacent to gate 13, ~6~G~
RD-15,042 becomes depleted of holes (or positive charge current carriers) and populated with electrons so as to form what is kno~n as an "inversion" channel that is con-ductive to electrons. Then, with drain electrode 24 biased more positiYely than source electrod0 22, electron current 3~ (shown schematlcally) flows from source electrode 22 to N voltage-supporting region 30 via N~ source region 28 and the inversion channel in portlon 26'. Holes are injected into N voltage-supporting layer 30 b~ P~ lowermost region 32 via a hole current path 34 when P-N junction 33, e~tant between these layers~ becomes sufficien~ly forward biased (about 0.5 volts for silicon). A portion of hole current 34 recombines with electron current 32 where their paths intersect (~or example, at location 36), and this recombination accounts for the bulk of device current, However, a fraction of hole current 34, as represented by hole current path 38 (shown schematically), does not recombine with elec~rons from ~o electron current path 32 but instead flows to source electrode 22 via P L~ase region 26. Hole current 38 causes a~oltage drop along P-N junction 29, between locations A and B, and i~ this voltage exceeds about 0~5 volts for silicon devices, N~ source region 28 is induced to inject electrons into P base region 26, and device 10 thereupon latches into an on state, in the same way as a thyristor 3 with attendant loss of control of device current by gate 18.
To reduce the voltage drop along P-N junction 29 caused by hole current 38, a P~ shorting region 42 9 shown in phantom, is provided in wafer 12 in accordance with the prio. art. Region ~2 is highly conduc t ive to holes, and, consequcntly, the voltage drop along P-N
junction 29 ~rom location C to location B i5 extremely ;e'36E~
RD-15,042 low. The implementation of P~ shorting region ~2 has two significant disadvantages, howevcr. First a specially~aligned mask (not shown) is typically used in the process of ~abricating P~ shorting region 42.
Second, P base region 26 mu~t be sufficiently large to accommodate alignment tolerance for the ~oregoing mas~, resulting in a larger cell size and lower current-carrying capability in device 10. These disadvantages are avoide~ by the present invention, which is described in Fig. 2 and the succeeding drawings figures~
Considering now ~igure 2, there is illustra-ted i~ cross-section one step in the fabrication process of a s~miconductor device 50 in accordance with the present invention. Device 50 includes a wafer o~ semi-conductor material 52, such as silicon, a gate 58 such as polysilicon highly doped with N-conductivity type impurities, and an insulating layer 60 9 the lower portion of which insulatingl~ spaces gate 58 from wafer 52.
Insulating layer 60 is illustrated in simpli~ied form as comprising only one layer, but may, in actuality ~omprise one or more layers of silicon dioxide and - silicon nitride, by way of example. Wafer 52 includes a lowermost region 6~, which may be of P-conductivity type (~or an I&T) or N conductivity type (for a hIOSFET);
an N voltage-supporting layer 64 overlying lowermost layer 62; and a P base region 68 overlying N voltage-supporting layer 64 and having a portion 68' terminating in proximity to gate 58 and~ which, as viewed from above, may be rectangular, circular or elongated, by way of example. Wafer 52 further includes an N~ source region 70 overlying P base region 68, with the upper-most portion o~ region 70 terminating at wafer upper sur~ace 54. ~ith P base portion ~8' terminatin~ at wa~er upper surface 54, as illustrated, device 50 RD-15,042 ~9--constitutes a normally-off device in that the gate 58 must be biased in order to turn on device 50. If, in an alternative embodiment, an N-conductivity region (not shown) were interposed between P base portion 68' and wafer upper surface 54 and were interconnected with both N voltage-supporting reglon 64 and N~ source region 70, device 50 would constitute a normally-on device, that is, electron current would flow through such N-conductivity regiorl unless gate 58 were appropriately biased so as to deplete the N-conductivity type region of electrons.
In accordance with the present invention, P~
implant shorting region 72 is formed in wafer 52 by implantlng a P-conductivity type dopant through wafer upper surface 54 while utilizing gate 58 and the portion of insulating layer 60 thereabove as an implant mask.
Accordingly, without the need for a specially-aligned mask, P+ implant shorting region 72 can be readily formed and~ advantageously permits a small sized P base region 68 as viewed ~rom abo~e since P base region 68 need not be made large in order to accommodate an alignment tolerance for a specially-aligned mask. Consequently, device 50 can have a smaller cell size,resulting in greater current-carrying capability thereof. P+ imp~ant shorting region 72 is situated between N+ source region 70 and P base region 68. P~ shor~ing region 72 may extend downwardly into P base region 68 more so than as illustrated (Figure 2), resulting ~n a relatively wide margin of tolerance in selecting a suitable implant energy for forming such implant shorting reglon.
An exemplary procedure for forming P+ im~lant shor-ting region 72 is now described in connection wi~h Figure 3, which depicts in an enlarged detail view the ~2~
~D-15,042 center portion of P~ implant shorting regioa 72 o~ Fig.
2, together with adjacent N~ source region 70 and P base region 68, Fig. 3 further depicts a dopant concentration profile ~or ~oth P-conductivity and N-conductivity type dopants, with the indicated depth being the depth into wa~er 52 from wa-fer upper surface 54. Boron constitutes the pre~erred P-conductivity type dopant used to form P+ implant shorting regio~ 72 and also P base region 68, while phosphorus constitutes the preferred N-conductivity type dopant used to form N+ source region 70. The boron dopant should overcome the phosphorus dopant at a location within the original N+ source region 70, as at location 75, so that P+ implant shorting region 68 directly ad~oins N~ source region 70.
The boron doping profile of P~ implant shorting region 72 as shown in Fig. 3 can be achieved, with the phosphorus dopant profile as shown~ for example, by implanting boron dopant at a high implant energy of l90K electron volts, for example, with a dopant concen-tration of 2 x 10 5 dopant atoms per cubic cm., at least ~or a silicon device. The reason that the implant energy should be high is to prevent P+ implant shorting region 72 from extending laterally into portion 68' of P base region 68 after the dopant for region 72 is "driven" or di~iused by a subsequent heating step of wa~er 5~c Thus~ the required bias voltage on gate 58 for inverting portion 68' of P base region 68 is not af~ected by the formation o~ P+ implant shorting region 72, Additionally~ it is desirable that the total thickness o~ gate 58 (Figo 2) and the portion of insulatin~ layer 60 (Fig. 2) atop gate 58 be sufficient to prevent the boron dopant from reaching the portion of insulating layer 60 beneath gate 58. This preserves unchan~ed b~ the boron implantation the required bias RD-15,042 --1.1--voltage on gate 58 for inverting portion 68' of P base regio~ 68.
A~ter formation of P+ implant shorting region 72~ the thus~ormed device 50, as illustrated in Fig.
5 . 4, is provided wlth source metallization 749 shown in phantom, such as aluminum. In accordance with an aspect o~ the present invention, the source metallization 74 is then sinteredata sufficiently high temperature for a sufficient period of ~ime to result in the formation of a metal-semiconductor eutectic composition 76, shown in phæntom. This composition 76 includes downwardly-extending splkes 78, conductively connecting P+ implant shorting region 72 to source metallization 74 and also connecting N~ source region 70 to source metallization 74.
By way of example, when using aluminum for source electrode 74 and silicon Eor wafer 52, a suitable sintering tlme for ~orming eutectic composition 76 is about 30 to 90 minutes with a sintering temperature in the range from about 500C to 550C. Spikes 78 of eutectic compo5ition 76 preferably do not penetrate through P+ shorting region 72 and into P base region 68, since this would detrimentally lower ~he breakdown voltage of device 50~
Device 50 when completed appears as shown in Fig. 5, and includes beneath lowermost region 62 a drain electrode 80, which may be ~ormed at any conven-ient point in the fabrication process for device 50, as will be apparent to those skilled in the ar~.
Turning now to Fig. 6, a semiconductor device 90 in accordance wlth a further embodiment of the invention is illustrated after a P~ implant shorting region 72' has been formed. The thus-Eormed device 90 corresponds to device 50 of Fig. 2 after P~ implant shorting region 72 has been formed therein; accordingly, portions of device 90 and of device 50 having like ~Z31L~i~68 RD~15,042 re~erence numerals consti.tute like parts.
In accordance with the processing step illus-trated in Fig~ 6 9 a shallow etch o~ a portion of N~
source region 701 removes an area of semiconductor 5 . material 92, shown in phantom, from wafer upper surface 54' to at least the upper portion of P+ implant short-ing region 72'. By way of example, a directional etch process, such as reactive ion etching, removing between about 0.25 and l.0 micrometers of semiconductor materlal 92; for example, would be suitable. If, however, a directional etch is not used and also if source metallization (not shown) is to make contact to N+
source region 70' only at wall 94, a shallower etch depth o~ between about 0.25 and 0.4 micrometers would be preferred~ This is to prevent extensive lateral etching o~ ~ source region 70' at wall location 9~, which might result in dif~iculty in applying source metalli~ation to wall 94 of N+ source 70'.
A~ter comple~ion of the etch step o~ .Fig. 6, device 90 is metallized as shown in Fig. 7 witb source metallization 96, shown in phantom, which adjoins N+
source 701 at wall S4 and also the upper portion of P+
implant shorting region 72'. Drain metallization .~, shown in phantom and adjoining lowermost region 62~ ay be provided at this time or at another convenient time in the process of ~abricating device 90, as will be apparent to those skilled in the art. The com~leted semiconductor device 90 is illustrated in Fig. 8.
A preferre~ modification of semiconductor device 90 o~ Fig. 8 is illustrated in ~he tridimensional view o~ Fig. 9. Although shown partially broken away for clarity, source electrode 96 contac-ts N+ source 70' at wall . 94, but addi-tionally contacts source region 70' at portion lO0 o~ N~ source region 70', which is ~ ~Z~6~6~3 ~D-15,042 not etched in the etch step of Fig. 6. Portion 100 o~
N-~ source region 70' may be provided in a convenient manner b-y using as an etching mask in the etch step of Figure 6 a grld of parallel lines (~or example, 4 micro-meters wide with 4 micrometers spacing), that are oriented generally orthogonal to the longitudinal axis o~ rectangular opening 102 (Fig. 9) in gate 58'.
Turning now to Fig. 10, there is shown ~ semi-conductor device 110 in accordance with another embodi-ment of the invention~ with like reference numerals as betwee~ device 110 (Fig. 10) and device 90' (~ig. g) referring to llke parts. In device 110, source electrode 96' contacts N~ source region 70" only a portion 100'.
This portion 100' is suitably formed by using as an implanting mask (when implanting P+ regions 72", 112 and 114) a grid of parallel lines (for examplel 4 micro-meters wide with 4 micrometers spacing~, that are oriented generally ortho~onal to the longitudinal axis o~ rectangular opening 102' in gate 58". Source electrode 96' is conductively coupled to P~ implant shorting region 7~1 via a highly conductive path comprising P4 implant regions 112 and 114, which are formed at lesser implant energies than region 72".
Whlle t~o P+ implants (112 and 114) are illustrated, a single implant or more than two implants may be used with the criterion being that these implants provide a highly conductive path between source electrode 96' and P~ implant shorting region 72".
In Fig. 11 there is shown a semiconductor device 200 incorporating ~eatures o~ the presen~
invention together with a feature of the prior art semiconductor device of Fig. 1. Like reference numerals as between device 200 (Fig. 11) and device 10 (Fig. 1) refer to like parts. Device 200 includes a P+ implant ~ ~ 23.696~
RD-15,0~2 shorting region 202 in accordance with the present i~vention, and, additionally, a P~ shorting region 42' in accordance with the prior art device 10.
The center 206 of P+ implant shorting region 202 as view~d from above the device is shown as being in contact with wa~er upper surface 14', which may result, for example, ~rom P~ implant shorting region 202 being implanted through a thick oxide (not shown) previously located directly above center region 206. Such thick oxlde may be a thermally-grown oxide covering the open-in~ of a mask ~not shown) used in forming P~
shorting region 42' and also ~r~ source region 28'.
Although the cell size of device 200 is typically as large as the cell size of device 10, wher~
device 200 comprises an IGT (with lowermost region 32' being of P-conductivity type), it is less likely to latch i~to an on state as compared with prior art IGT
device 10. This is because hole current (not shown) that ilows from P base 26' to source electrode 22' encounters more highly conductlve P-conductivity type material (i.e. 9 both regions ~2t and ~02~ than does hole current 38 of ~lg. 1 in its path from P base 26 to source electrode 22 (i.e~, only region 42).
In a preferred modification of semiconductor device 200 (Fig~ 11), P+ shorting region 421 is made shallower than is the case ~or corres~onding P~ shorting region 42 of prior art device 10 (Fig. 1), or is entirely omitted (not shown). This is a permissable modification of device 200 since P~ implant shorting region 202 together with source electrode 271 , which is contacted by region 202 at w~fer upper surface 1~', are adequate to implement a base-to-source electrode short in device 200. A beneficial consequence of making P~ shorting region 42' shallower or o~ omitting it ~ ~6~68 RD-15,042 entirely ~rom device 200 is th~t device 200 can then be made wlth a smaller cell size.
The ~ore~oing describes semiconduc~or device~ with improved base-to-source electrode shorts that provlde superior devlce performance while being slmple to ~abricate and permitting Q smaller device-c~ll siz~.
While the inYention has been described with respect -to speci~ic embodiments by way of illustration~
many modi~ications and changes will occur to those skilled in the art. For example, complementary semi-conductor devices could be fabricated wherein P-con-ductivity type material is used instead o~ N~conduc-tivity type material, and vice-versa. It is~ therefore, to be understood that the appended claims are intended to cover the ~oregoing and all such modi~ications and changes as ~all within the true spirit and scope of the inv~ntion.
The boron doping profile of P~ implant shorting region 72 as shown in Fig. 3 can be achieved, with the phosphorus dopant profile as shown~ for example, by implanting boron dopant at a high implant energy of l90K electron volts, for example, with a dopant concen-tration of 2 x 10 5 dopant atoms per cubic cm., at least ~or a silicon device. The reason that the implant energy should be high is to prevent P+ implant shorting region 72 from extending laterally into portion 68' of P base region 68 after the dopant for region 72 is "driven" or di~iused by a subsequent heating step of wa~er 5~c Thus~ the required bias voltage on gate 58 for inverting portion 68' of P base region 68 is not af~ected by the formation o~ P+ implant shorting region 72, Additionally~ it is desirable that the total thickness o~ gate 58 (Figo 2) and the portion of insulatin~ layer 60 (Fig. 2) atop gate 58 be sufficient to prevent the boron dopant from reaching the portion of insulating layer 60 beneath gate 58. This preserves unchan~ed b~ the boron implantation the required bias RD-15,042 --1.1--voltage on gate 58 for inverting portion 68' of P base regio~ 68.
A~ter formation of P+ implant shorting region 72~ the thus~ormed device 50, as illustrated in Fig.
5 . 4, is provided wlth source metallization 749 shown in phantom, such as aluminum. In accordance with an aspect o~ the present invention, the source metallization 74 is then sinteredata sufficiently high temperature for a sufficient period of ~ime to result in the formation of a metal-semiconductor eutectic composition 76, shown in phæntom. This composition 76 includes downwardly-extending splkes 78, conductively connecting P+ implant shorting region 72 to source metallization 74 and also connecting N~ source region 70 to source metallization 74.
By way of example, when using aluminum for source electrode 74 and silicon Eor wafer 52, a suitable sintering tlme for ~orming eutectic composition 76 is about 30 to 90 minutes with a sintering temperature in the range from about 500C to 550C. Spikes 78 of eutectic compo5ition 76 preferably do not penetrate through P+ shorting region 72 and into P base region 68, since this would detrimentally lower ~he breakdown voltage of device 50~
Device 50 when completed appears as shown in Fig. 5, and includes beneath lowermost region 62 a drain electrode 80, which may be ~ormed at any conven-ient point in the fabrication process for device 50, as will be apparent to those skilled in the ar~.
Turning now to Fig. 6, a semiconductor device 90 in accordance wlth a further embodiment of the invention is illustrated after a P~ implant shorting region 72' has been formed. The thus-Eormed device 90 corresponds to device 50 of Fig. 2 after P~ implant shorting region 72 has been formed therein; accordingly, portions of device 90 and of device 50 having like ~Z31L~i~68 RD~15,042 re~erence numerals consti.tute like parts.
In accordance with the processing step illus-trated in Fig~ 6 9 a shallow etch o~ a portion of N~
source region 701 removes an area of semiconductor 5 . material 92, shown in phantom, from wafer upper surface 54' to at least the upper portion of P+ implant short-ing region 72'. By way of example, a directional etch process, such as reactive ion etching, removing between about 0.25 and l.0 micrometers of semiconductor materlal 92; for example, would be suitable. If, however, a directional etch is not used and also if source metallization (not shown) is to make contact to N+
source region 70' only at wall 94, a shallower etch depth o~ between about 0.25 and 0.4 micrometers would be preferred~ This is to prevent extensive lateral etching o~ ~ source region 70' at wall location 9~, which might result in dif~iculty in applying source metalli~ation to wall 94 of N+ source 70'.
A~ter comple~ion of the etch step o~ .Fig. 6, device 90 is metallized as shown in Fig. 7 witb source metallization 96, shown in phantom, which adjoins N+
source 701 at wall S4 and also the upper portion of P+
implant shorting region 72'. Drain metallization .~, shown in phantom and adjoining lowermost region 62~ ay be provided at this time or at another convenient time in the process of ~abricating device 90, as will be apparent to those skilled in the art. The com~leted semiconductor device 90 is illustrated in Fig. 8.
A preferre~ modification of semiconductor device 90 o~ Fig. 8 is illustrated in ~he tridimensional view o~ Fig. 9. Although shown partially broken away for clarity, source electrode 96 contac-ts N+ source 70' at wall . 94, but addi-tionally contacts source region 70' at portion lO0 o~ N~ source region 70', which is ~ ~Z~6~6~3 ~D-15,042 not etched in the etch step of Fig. 6. Portion 100 o~
N-~ source region 70' may be provided in a convenient manner b-y using as an etching mask in the etch step of Figure 6 a grld of parallel lines (~or example, 4 micro-meters wide with 4 micrometers spacing), that are oriented generally orthogonal to the longitudinal axis o~ rectangular opening 102 (Fig. 9) in gate 58'.
Turning now to Fig. 10, there is shown ~ semi-conductor device 110 in accordance with another embodi-ment of the invention~ with like reference numerals as betwee~ device 110 (Fig. 10) and device 90' (~ig. g) referring to llke parts. In device 110, source electrode 96' contacts N~ source region 70" only a portion 100'.
This portion 100' is suitably formed by using as an implanting mask (when implanting P+ regions 72", 112 and 114) a grid of parallel lines (for examplel 4 micro-meters wide with 4 micrometers spacing~, that are oriented generally ortho~onal to the longitudinal axis o~ rectangular opening 102' in gate 58". Source electrode 96' is conductively coupled to P~ implant shorting region 7~1 via a highly conductive path comprising P4 implant regions 112 and 114, which are formed at lesser implant energies than region 72".
Whlle t~o P+ implants (112 and 114) are illustrated, a single implant or more than two implants may be used with the criterion being that these implants provide a highly conductive path between source electrode 96' and P~ implant shorting region 72".
In Fig. 11 there is shown a semiconductor device 200 incorporating ~eatures o~ the presen~
invention together with a feature of the prior art semiconductor device of Fig. 1. Like reference numerals as between device 200 (Fig. 11) and device 10 (Fig. 1) refer to like parts. Device 200 includes a P+ implant ~ ~ 23.696~
RD-15,0~2 shorting region 202 in accordance with the present i~vention, and, additionally, a P~ shorting region 42' in accordance with the prior art device 10.
The center 206 of P+ implant shorting region 202 as view~d from above the device is shown as being in contact with wa~er upper surface 14', which may result, for example, ~rom P~ implant shorting region 202 being implanted through a thick oxide (not shown) previously located directly above center region 206. Such thick oxlde may be a thermally-grown oxide covering the open-in~ of a mask ~not shown) used in forming P~
shorting region 42' and also ~r~ source region 28'.
Although the cell size of device 200 is typically as large as the cell size of device 10, wher~
device 200 comprises an IGT (with lowermost region 32' being of P-conductivity type), it is less likely to latch i~to an on state as compared with prior art IGT
device 10. This is because hole current (not shown) that ilows from P base 26' to source electrode 22' encounters more highly conductlve P-conductivity type material (i.e. 9 both regions ~2t and ~02~ than does hole current 38 of ~lg. 1 in its path from P base 26 to source electrode 22 (i.e~, only region 42).
In a preferred modification of semiconductor device 200 (Fig~ 11), P+ shorting region 421 is made shallower than is the case ~or corres~onding P~ shorting region 42 of prior art device 10 (Fig. 1), or is entirely omitted (not shown). This is a permissable modification of device 200 since P~ implant shorting region 202 together with source electrode 271 , which is contacted by region 202 at w~fer upper surface 1~', are adequate to implement a base-to-source electrode short in device 200. A beneficial consequence of making P~ shorting region 42' shallower or o~ omitting it ~ ~6~68 RD-15,042 entirely ~rom device 200 is th~t device 200 can then be made wlth a smaller cell size.
The ~ore~oing describes semiconduc~or device~ with improved base-to-source electrode shorts that provlde superior devlce performance while being slmple to ~abricate and permitting Q smaller device-c~ll siz~.
While the inYention has been described with respect -to speci~ic embodiments by way of illustration~
many modi~ications and changes will occur to those skilled in the art. For example, complementary semi-conductor devices could be fabricated wherein P-con-ductivity type material is used instead o~ N~conduc-tivity type material, and vice-versa. It is~ therefore, to be understood that the appended claims are intended to cover the ~oregoing and all such modi~ications and changes as ~all within the true spirit and scope of the inv~ntion.
Claims (13)
1. An insulated-gate semiconductor device with an improved base-to-source electrode short, comprising:
a semiconductor wafer having a substantially planar upper surface;
a voltage-supporting layer of one conductivity type included in said wafer;
a base region of opposite conductivity type included in said wafer, overlying said voltage-supporting layer, and having a portion terminating in proximity to or at said upper surface;
a source region of said one conductivity type included in said wafer and overlying said base region;
a gate insulatingly spaced above said wafer;
a source electrode situated above said wafer and conductivity coupled to said source region; and an implant shorting region of said opposite conductivity type included in said wafer and having an upper surface with the major portion of said upper surface being situated beneath the plane of said wafer upper surface, said implant shorting region adjoining both said source and base regions, said implant shorting region having a higher conductivity than said base region and being conductively coupled to said source electrode, said implant short permitting a smaller cell size and a greater current carrying capability.
a semiconductor wafer having a substantially planar upper surface;
a voltage-supporting layer of one conductivity type included in said wafer;
a base region of opposite conductivity type included in said wafer, overlying said voltage-supporting layer, and having a portion terminating in proximity to or at said upper surface;
a source region of said one conductivity type included in said wafer and overlying said base region;
a gate insulatingly spaced above said wafer;
a source electrode situated above said wafer and conductivity coupled to said source region; and an implant shorting region of said opposite conductivity type included in said wafer and having an upper surface with the major portion of said upper surface being situated beneath the plane of said wafer upper surface, said implant shorting region adjoining both said source and base regions, said implant shorting region having a higher conductivity than said base region and being conductively coupled to said source electrode, said implant short permitting a smaller cell size and a greater current carrying capability.
2. The semiconductor device of claim 1 wherein the entire upper surface of said shorting region is situated below the upper surface of said wafer and further comprising a conductive metal-semiconductor eutectic composition conductively interconnecting said source electrode and said implant shorting region.
3. The semiconductor device of claim 1 wherein said source electrode adjoins said implant shorting region and portions of said source region at respective locations beneath the plane of said wafer upper surface.
4. The semiconductor device of claim 3 wherein said source electrode further adjoins said source region at the plane of said wafer upper surface.
5. The semiconductor device of claim 1 further comprising at least one further implant region of said opposite conductivity type included in said wafer, said at least one further implant region having an upper surface contiguous with said wafer upper surface and a lower surface adjoining said implant shorting region, said source electrode adjoining said further implant region at said wafer upper surface and further adjoining said source region at said wafer upper surface.
6. The semiconductor device of claim 1 further comprising a second shorting region in said wafer laterally adjoining said base region and at least the major portion thereof adjoining both said implant shorting region and said voltage-supporting layer.
7. The semiconductor device of claim 6 further comprising:
a minority-carrier injection region in said wafer of said opposite conductivity type and underlying said voltage-supporting layer; and a drain electrode underlying said minority-carrier injection region.
a minority-carrier injection region in said wafer of said opposite conductivity type and underlying said voltage-supporting layer; and a drain electrode underlying said minority-carrier injection region.
8. The semiconductor device of claim 1 wherein said source region and said voltage-supporting layer comprise seimconductor material of N-conductivity type and said base and implant shorting regions comprise semiconductor material of P-conductivity type.
9. The semiconductor device of claim 8 wherein said wafer comprises silicon semiconductor material.
10. A method of fabricating an implant shorting region in an insulated-gate semiconductor device, comprising the steps of:
providing a semiconductor wafer having a substantially planar upper surface and including, in successively adjoining arrangement, a source region of one conductivity type, a base region of opposite conductivity type, and a voltage-supporting region of said one conductivity type;
forming atop said wafer a gate insulatingly spaced from said wafer;
utilizing said gate as an integral portion of an implant mask while implanting into said wafer an implant shorting region of said opposite conductivity type and of higher conductivity than said base region, said implanting being conducted at a sufficiently high energy level such that said implant shorting region is formed, at least in major part, beneath said wafer upper surface and adjoining both said source and base regions; and conductively connecting a source electrode to said source and implant shorting regions.
providing a semiconductor wafer having a substantially planar upper surface and including, in successively adjoining arrangement, a source region of one conductivity type, a base region of opposite conductivity type, and a voltage-supporting region of said one conductivity type;
forming atop said wafer a gate insulatingly spaced from said wafer;
utilizing said gate as an integral portion of an implant mask while implanting into said wafer an implant shorting region of said opposite conductivity type and of higher conductivity than said base region, said implanting being conducted at a sufficiently high energy level such that said implant shorting region is formed, at least in major part, beneath said wafer upper surface and adjoining both said source and base regions; and conductively connecting a source electrode to said source and implant shorting regions.
11. The method of fabricating an implant shorting region in accordance with claim 10 wherein said step of conductively connecting a source electrode to said source region and implant shorting regions comprises forming a metal-semiconductor eutectic compo-sition interconnecting said source electrode and said source and implant shorting regions.
12. The method of forming an implant shorting region in accordance with claim 10 wherein said step of conductively connecting a source electrode to said source and implant shorting regions comprises etching through said source region to said implant shorting region and depositing a metal layer on said source and implant shorting regions.
13. The method of forming an implant shorting region in accordance with claim 10 wherein said step of conductively connecting a source electrode to said source and implant shorting regions comprises the
13. The method of forming an implant shorting region in accordance with claim 10 wherein said step of conductively connecting a source electrode to said source and implant shorting regions comprises the
Claim 13 continued:
further steps of:
utilizing said gate as an integral portion of an implant mask while implanting into said wafer at least one further, highly conductive implant region of said opposite conductivity type, said further implant region conductively connecting said implant shorting region to said wafer upper surface; and depositing a metal layer on selected portions of said source region and on said further implant region.
further steps of:
utilizing said gate as an integral portion of an implant mask while implanting into said wafer at least one further, highly conductive implant region of said opposite conductivity type, said further implant region conductively connecting said implant shorting region to said wafer upper surface; and depositing a metal layer on selected portions of said source region and on said further implant region.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US52919883A | 1983-09-06 | 1983-09-06 | |
| US529,198 | 1983-09-06 | ||
| DE19843435612 DE3435612A1 (en) | 1983-09-06 | 1984-09-28 | Surface-semiconductor device and method for the fabrication thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1216968A true CA1216968A (en) | 1987-01-20 |
Family
ID=25825184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000461632A Expired CA1216968A (en) | 1983-09-06 | 1984-08-23 | Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA1216968A (en) |
| DE (1) | DE3435612A1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4587713A (en) * | 1984-02-22 | 1986-05-13 | Rca Corporation | Method for making vertical MOSFET with reduced bipolar effects |
| FR2570880A1 (en) * | 1984-09-27 | 1986-03-28 | Rca Corp | METHOD FOR MANUFACTURING ISOLATED GRID FIELD EFFECT TRANSISTOR AND TRANSISTOR THUS OBTAINED |
| EP0227894A3 (en) * | 1985-12-19 | 1988-07-13 | SILICONIX Incorporated | High density vertical dmos transistor |
| JPH02267944A (en) * | 1989-03-15 | 1990-11-01 | Siemens Ag | Power mos-fet |
| JP2551152B2 (en) * | 1989-06-29 | 1996-11-06 | 富士電機株式会社 | MOS control thyristor |
| DE4121375A1 (en) * | 1991-06-28 | 1993-01-14 | Asea Brown Boveri | DISABLED POWER SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
| DE4244272A1 (en) * | 1992-12-28 | 1994-06-30 | Daimler Benz Ag | Field effect controlled semiconductor device |
| DE4435458C2 (en) * | 1994-10-04 | 1998-07-02 | Siemens Ag | Semiconductor component controllable by field effect |
| JP3708998B2 (en) * | 1994-11-04 | 2005-10-19 | シーメンス アクチエンゲゼルシヤフト | Manufacturing method of semiconductor device controllable by electric field effect |
| DE19842488A1 (en) * | 1998-09-16 | 2000-03-30 | Siemens Ag | Semiconductor device and semiconductor structure with contacting |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1133869B (en) * | 1979-10-30 | 1986-07-24 | Rca Corp | MOSFET DEVICE |
| DE3240162C2 (en) * | 1982-01-04 | 1996-08-01 | Gen Electric | Method of fabricating a double-diffused source-based short-circuit power MOSFET |
| US4417385A (en) * | 1982-08-09 | 1983-11-29 | General Electric Company | Processes for manufacturing insulated-gate semiconductor devices with integral shorts |
-
1984
- 1984-08-23 CA CA000461632A patent/CA1216968A/en not_active Expired
- 1984-09-28 DE DE19843435612 patent/DE3435612A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| DE3435612A1 (en) | 1986-04-03 |
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