CN113410307B - Field effect transistor structure, manufacturing method thereof and chip device - Google Patents
Field effect transistor structure, manufacturing method thereof and chip device Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
The invention relates to a field effect transistor structure, a manufacturing method thereof and a chip device, wherein the transistor comprises a drain electrode epitaxial layer positioned at the bottom, a source electrode layer positioned at the top, and a source electrode extension inverted fin and a grid electrode which are embedded in the drain electrode epitaxial layer; the grid electrode is arranged between the source electrode extended inverted fins, and symmetrical channels which are connected in parallel from the source electrode layer to the inside of the drain electrode epitaxial layer are formed on two sides of the grid electrode; in a preferred example, symmetrical domain resistors which are connected in parallel from a source electrode layer to a drain electrode epitaxial layer are further formed above the channel on two sides of the grid electrode; in a preferred example, the drain electrode epitaxial layer forms a floating-gate inverted-type junction under the gate at the bottom part corresponding to the gate; in a preferred example, the drain epitaxial layer forms a shield gate bottom floating inverted pole type bottom pillar junction at the bottom part corresponding to the source extension inverted fin. The invention creates a double-inverted-half-fin floating super-junction gate field effect transistor structure, and has the gain effect of uniformizing or helping to uniformize the electron current of the back drain electrode and the top source electrode of the substrate.
Description
The priority basis of the present invention includes: application No. 202110414351.7, application No. 2021.04.16, invention application entitled "field effect transistor structure and method of manufacturing the same, chip device".
Technical Field
The present invention relates to the field of semiconductor transistor technology, and more particularly, to a field effect transistor structure, a method for manufacturing the same, and a chip device.
Background
The field effect transistor structure is used as a key important device of a semiconductor chip, and various structures mainly comprise FinFET fin type field effect transistors, JFET junction type field effect transistors, surface field effect transistors, tunneling type field effect transistors, trench gate field effect transistors, split gate field effect transistors and super junction field effect transistors. The FinFET structure, JFET junction structure, surface field effect transistor structure, and tunneling field effect transistor structure all have source and drain contacts designed on the same surface of the semiconductor substrate, and as wafer thinning and device miniaturization trends develop, the problem of wafer backside leakage current is increasingly a difficult problem that needs to be faced and overcome. The JFET and the tunnel fet have serious leakage current problems due to the channel layer being designed in the active region of the semiconductor substrate, and the FinFET fin transistor has a channel layer designed on the protruding fin-shaped gate by additional deposition, which is relatively light in leakage current problems, but the device structure and process are relatively complicated. The channel layer of the FinFET fin type transistor is formed by an epitaxial mode on the surface of an oxide layer, obviously, the single crystal structure which is not provided with the channel layer formed in an endogenous mode is not formed, and therefore the stability of the electrical performance of the channel layer is not as good as that of a JFET junction field effect transistor, a surface field effect transistor and a tunneling field effect transistor. The limitation of silicon limit exists in a trench gate (trench gate) field effect transistor, so that the power density of a device which occupies a larger wafer area by realizing the same on-resistance cannot be improved. Although the split gate field effect transistor and the super junction field effect transistor can break through the silicon limit, the process is complex and the process control window is narrow; in addition, the device is easy to have the phenomenon of poor current concentration reliability, so that the performance and the reliability of the device are difficult to be obtained simultaneously.
Prior art FinFET fin transistors are found in CN103985712A, CN106981517A, CN106887461A, all having a gate fin protruding from the substrate. JFET JFETs in the prior art can be found in CN1507070A, CN108257955A, without a gate protruding from the substrate and with a channel layer defined by a doped region pattern within the substrate. The planar field effect transistor in the prior art can be seen in CN107534060A, has no grid protruding from the substrate, and occupies a large surface area. In the prior art, the tunnel fet is shown in CN110797387A and CN110943121A, which are a variation of the FinFET fin transistor, two fin structures form an epitaxial patterned layer in an epitaxial manner, the sidewalls of the fin structures cover and bury the gate layer, the gate function of the original fin structure is changed into a channel function, and the tops of the two fin structures on the same surface are respectively used as a source and a drain.
Disclosure of Invention
The invention mainly aims to provide a field effect transistor structure, and mainly aims to solve the problems of uneven source electronic current distribution, incompatible product performance and reliability and incompatible product performance and processing difficulty of a field effect transistor by using an innovative transistor architecture. The transistor architecture is named as Double inverted half fin Floating super Junction gate field effect transistor (DRFJ).
The present invention also provides a method for manufacturing a field effect transistor structure, which is used to manufacture a field effect transistor structure with uniform distribution of electron current at the electrode.
A third objective of the present invention is to provide a semiconductor chip device including a field effect transistor structure with DRFJ architecture.
The main purpose of the invention is realized by the following technical scheme:
a field effect transistor structure is proposed, comprising:
the drain electrode substrate is provided with a processing surface and a corresponding back surface, the processing surface is provided with first grooves which are parallel to each other, the inner walls of the first grooves are subjected to insulation processing, source electrode extension inverted fins are arranged in the first grooves, and the depth of the first grooves does not exceed the thickness of the drain electrode epitaxial layer;
an active layer formed in the drain electrode epitaxial layer, wherein second grooves are formed between the first grooves by the active layer, the inner walls of the second grooves are subjected to insulation treatment, a grid electrode is arranged in the second grooves, and the second depth of the second grooves is enough to penetrate through the active layer and is smaller than the first depth of the first grooves;
the inner dielectric layer is formed on the active layer and the grid electrode, so that the grid electrode is of an embedded structure; forming a third trench aligned with the first trench from the inner dielectric layer, wherein the inner wall of the third trench is not subjected to insulation treatment, and the width and depth of the third trench are sufficient to directly expose the edge of the active layer from the side and expose the top of the source extended inverted fin from the bottom;
the barrier layer is formed at the bottom of the third groove to cover the exposed area of the drain electrode epitaxial layer at the bottom of the third groove; and a source layer formed on the processing surface and filled in the third trench to conduct the source extended inverted fin, wherein an inversion layer of the active layer is injected in a thickness direction to define a channel length of the field effect transistor, instead of defining the channel length of the field effect transistor in a length direction of the active layer in the prior art, so as to provide a plurality of short-distance parallel transistor channels vertically oriented to the processing surface.
By adopting the technical scheme, the third groove aligned with the first groove is formed by the inner dielectric layer, the inner wall of the third groove is not subjected to insulation treatment, the width and the depth of the third groove are enough to directly expose the edge of the active layer on the side and expose the top of the source electrode extension inverted fin at the bottom, so that the bottom of the source electrode layer is connected with the source electrode extension inverted fin in a conduction mode, and the two sides of the source electrode layer are connected with the active layer in a conduction mode; further enabling the source electrode extended inverted fin to have the function of an electron flow isolation gate; the source layer is conducted with the active layer on two sides of the third groove, the active layer can be conducted to the drain substrate along the outline of two sides of the gate insulation treatment, so that the channel length of the field effect transistor can be defined in the inversion layer injection thickness direction of the active layer, specifically, a transistor channel can be planned on the outline of each side of the gate insulation treatment, and parallel channels which are vertical and parallel relative to the treatment surface are formed on two sides of the embedded gate due to the fact that the gate embedding depth breaks through the active layer to reach the inside of the drain epitaxial layer; the back surface of the drain substrate can be used as a contact of a drain pad, the movement of electron current is from the processing surface to the back surface of the drain epitaxial layer, in the process, half gates of channels on one side are opened after the shunting of two sides of the third groove and gate insulation processing, and the half gates are dispersed on the back surface of the drain substrate under the field effect of the shunting of the source extended inverted fin and the isolation gate, so that the conduction of channels on two sides of two half-gate transistors under two adjacent source shunts between the back surface of the drain substrate and the source extended inverted fin is realized, the defect of the leakage current on the back surface of the original substrate is converted into beneficial and meaningful drain output, and the situation that the electron current such as a fuse effect is concentrated in a local area on the back surface of the drain substrate is avoided.
And the source layer and the source extension inverted fin are separately designed and structurally conducted in the manufacturing process, the source layer only needs to be filled with the third groove with larger width in the process, the first groove with smaller width does not need to be filled, and the material selection of the source extension inverted fin has more freedom, so that the difficulty of filling the groove in the process filling hole is overcome, the thermal expansion adaptability of the drain epitaxial layer is improved, and the metal diffusion effect on the drain epitaxial layer is reduced.
In addition, a schottky barrier is introduced between a source electrode and a drain electrode of the field effect transistor structure, the schottky barrier has a lower forward voltage drop (VFsd) compared with a traditional PN junction, the forward voltage drop (VFsd) is less than 0.6V, the forward voltage drop (VFsd) of the traditional PN junction is often greater than 0.6V, and the PN junction has a charge storage effect, so that large reverse charges (Qrr) are generated, and the large forward voltage drop (VFsd) and the large reverse recovery charges (Qrr) can cause the problems of large loss of the device in the using process, high peak Voltage (VDS) and the like.
The invention may further be configured in a preferred example to: the third trench penetrates the active layer, the barrier layer being located at a bottom corner of the third trench; the barrier layer includes: the light doped region is positioned on the drain electrode epitaxial layer, the barrier metal layer is positioned on the light doped region, and a Schottky barrier is formed at a contact region of the light doped region and the barrier metal layer.
By adopting the preferable technical characteristics, when the lightly doped region with the semiconductor characteristic is contacted with the barrier metal layer with the metal characteristic, the semiconductor energy band at the interface is bent to form a Schottky barrier, and the Schottky barrier has lower interface voltage, so that the device is effectively protected.
The invention may in a preferred example be further configured to: the active layer is formed by internalization of the processing surface of the drain electrode epitaxial layer; the width of the third groove is larger than that of the first groove;
the active layer is a multilayer structure comprising: the transistor comprises a channel layer positioned at the bottom, a current balance layer positioned on the channel layer, and a source electrode field layer positioned on the current balance layer; the depth of the third trench is such that the third trench passes through the source-region layer and the current-balance layer.
By adopting the above preferred technical features, the source electrode layers in two adjacent third trenches are conducted on the inner dielectric layer to enlarge the source contact, and the inner dielectric layer electrically insulates the top of the gate electrode from the extended source electrode layer. When the active layer is formed by internalization of the processing surface of the drain electrode epitaxial layer, the crystal lattices of the active layer and the drain electrode epitaxial layer are matched, the defect of an interface gap is avoided, the channel structure of the transistor and the drain electrode epitaxial layer form an integral structure, and the electrical property stability of the transistor is superior to that of an epitaxially grown active layer or channel layer; the width of the third groove is larger than that of the first groove, so that the top of the source electrode extension inverted fin is effectively opened at the bottom of the third groove, the third groove has the function of a contact hole, the defect that the source electrode layer and the source electrode extension inverted fin cannot be conducted due to the fact that the third groove is not aligned with the first groove is reduced, and finally the effect that the third groove and the source electrode extension inverted fin have the same electric field potential in use is achieved.
In addition, a current balance layer is formed between the source electrode field layer and the channel layer by utilizing the multi-layer structure of the active layer, the thickness of the current balance layer has resistance functions on two sides of the gate electrode after insulation treatment so as to provide a plurality of short-distance parallel resistors which are vertically arranged on the treatment surface, and the parallel resistors are respectively connected between the corresponding parallel transistor channels and the source electrode field layer in a conduction mode, so that the burning of the individual parallel transistor channels under larger electron flow is avoided, and the fuse effect is eliminated.
The invention may in a preferred example be further configured to: the bottom of the first groove is subjected to thick oxidation treatment, so that the insulation thickness of the first groove is larger at the bottom of the inner wall than at the side part of the inner wall.
By adopting the preferable technical characteristics, the insulation thickness of the first groove is larger at the bottom of the inner wall than at the side part of the inner wall, and the oxidation isolation stacking block is formed at the bottom of the inner wall of the first groove, so that the formation of electron tunneling between the bottom of the source extension inverted fin and the drain epitaxial layer is avoided, the avalanche breakdown resistance of the groove bottom and the gate oxide modification resistance of ion implantation in the post process are improved, the field effect at the bottom of the source extension inverted fin is reduced, and the shunt field effect of the shunt isolation gate is formed on two sides of the source extension inverted fin in the drain epitaxial layer.
The invention may in a preferred example be further configured to: and a deep implantation region is formed in the drain electrode epitaxial layer at a position corresponding to the bottom of the first groove so as to form a floating inverted-pole type bottom junction at the bottom of the shielding grid.
By adopting the preferable technical characteristics, the floating reverse pole type column bottom junction at the bottom of the shielding grid is utilized to be penetrated out from the bottom of the source electrode extension inverted fin, so that the charge balance of the floating reverse pole type column to the adjacent pole type column is increased, the depth of the first groove and the thickness of the bottom insulating layer can be reduced in the manufacturing process, and the filling formation of the source electrode extension inverted fin is facilitated.
The invention may further be configured in a preferred example to: and an implanted region is formed on the drain electrode epitaxial layer at the position corresponding to the bottom of the second groove so as to form a floating inverted-pole junction under the gate.
By adopting the preferable technical characteristics, the floating inverted-pole junction under the grid is penetrated out from the bottom of the grid, so that the bottom of the grid insulating layer is prevented from being damaged by a bottom concentrated electric field, the reliability of the grid insulating layer is improved, and the breakdown withstand voltage reduction caused by the concentration of the bottom grid oxide electric field is avoided.
The invention may further be configured in a preferred example to: by utilizing the electric field effect of the gate, the electron flow from the source layer is shunted by the side edge of the third groove to move to the drain substrate between the first grooves along one symmetrical side of the side wall profile of the second groove, and is uniform on the back surface of the drain epitaxial layer or a drain metal pad arranged on the back surface.
By adopting the preferable technical characteristics, the electron current is shunted from the top surface to the bottom surface at two sides of the third groove on the processing surface and is uniformly separated between the first grooves of the drain electrode epitaxial layer by utilizing the electric field effect of the grid electrode.
The main purpose of the invention is realized by the following technical scheme:
a method for fabricating a field effect transistor structure is proposed, for fabricating a field effect transistor structure which may be combined according to any of the above-mentioned technical solutions, the method comprising:
providing a drain electrode substrate, wherein the drain electrode substrate is provided with a processing surface provided by a drain electrode epitaxial layer and a corresponding back surface, and first grooves which are parallel to each other are formed by etching the processing surface;
forming a first oxidation isolation layer in the processing surface and the first groove to enable the inner wall of the first groove to be subjected to insulation processing; arranging a source extension inverted fin in the first groove in a deposition filling mode, and removing the source extension inverted fin and the part of the first oxidation isolation layer on the processing surface, wherein the depth of the first groove does not exceed the thickness of the drain electrode epitaxial layer; forming second grooves between the first grooves by etching the processing surface, wherein the second depth of the second grooves is smaller than the first depth of the first grooves;
forming a second oxidation isolation layer in the processing surface and the second groove to enable the inner wall of the second groove to be subjected to insulation processing; arranging a grid in the second groove in a deposition filling mode;
forming an active layer under the processing surface of the drain electrode epitaxial layer in an energy injection mode, wherein the thickness and the depth of the active layer are within a range which can be penetrated by the second depth of the second groove;
forming an inner dielectric layer on the active layer and the grid electrode in a deposition covering mode, so that the grid electrode is of an embedded structure;
etching the inner dielectric layer to form a third groove aligned with the first groove, wherein the inner wall of the third groove is not subjected to insulation treatment, the width and the depth of the third groove are enough to directly expose the edge of the active layer on the side and expose the top of the source electrode extension inverted fin at the bottom;
forming a barrier layer at the bottom of the third trench, wherein the barrier layer covers the drain epitaxial layer at the bottom exposed region of the third trench, and a Schottky barrier is formed in the barrier layer;
and forming a source layer in the third groove to conduct the source extension inverted fin, wherein the inversion layer injection thickness direction of the active layer defines the channel length of the field effect transistor.
By adopting the technical scheme, the source extension inverted fin is prefabricated, the process difficulty of filling a source extension material in the groove of the drain epitaxial layer in the semiconductor manufacturing process is reduced, and the double inverted fin inter-half gate field effect transistor is finally manufactured; a Schottky barrier is introduced between the source electrode and the drain electrode, so that the generation of reverse charges is effectively avoided, the loss of the device is small, the peak value of peak voltage is low, and the device is not easy to damage.
The invention may in a preferred example be further configured to:
after the step of providing the drain substrate, further comprising: forming a shielding grid bottom floating inverted pole type column bottom junction at the part, corresponding to the bottom of the first groove, of the drain electrode epitaxial layer in an ion implantation mode; specifically, the drain epitaxial layer is a conductive semiconductor wafer;
in the step of forming the first oxidation barrier layer, the method comprises: forming the first oxidation isolation layer in a thermal oxidation or precipitation mode; forming a side wall protection layer in the first groove; anisotropically etching the side wall protection layer to form an opening at the bottom of the first groove; then forming an oxidation isolation stacking block in the opening of the side wall protection layer; selectively etching and removing the side wall protection layer to expose the first oxidation isolation layer, wherein the thickness of the first oxidation isolation layer and the oxidation isolation superposition block at the bottom of the inner wall is larger than that of the first oxidation isolation layer at the side part of the inner wall; specifically, the first oxide isolation layer is made of silicon oxide, and the sidewall protection layer is made of silicon nitride;
in the step of arranging the source extension inverted fin, the method for removing the source extension inverted fin and the first oxidation isolation layer on the processing surface comprises chemical mechanical polishing or/and back etching; preferably, the material of the source extended inverted fin comprises conductive polysilicon;
in the step of forming the second trench, the preceding steps included are: forming a mask layer on the processing surface to cover the processing surface and the top of the source electrode extension inverted fin; preferably, after the second trench is formed, a gate-lower floating-up inversion-type junction is formed in the drain epitaxial layer at a position corresponding to the bottom of the second trench in an ion implantation manner;
in the step of forming the second oxidation isolation layer, the second oxidation isolation layer is specifically a gate oxide layer, and the gate oxide layer is formed on the inner wall of the second trench and the processing surface in a thermal oxidation or thermal oxidation plus deposition mode; before the formation of the gate oxide layer, firstly forming a sacrificial gate oxide layer on the inner wall of the second groove, and then removing the sacrificial gate oxide layer and cleaning the drain electrode epitaxial layer;
in the step of arranging the grid electrode, the method for removing the part of the grid electrode on the processing surface comprises chemical mechanical polishing or/and back etching; preferably, the material of the grid electrode comprises conductive polysilicon containing doped ions;
in the step of forming the active layer, the active layer is formed by internalization of the treated surface of the drain epitaxial layer; the active layer comprises a channel layer positioned at the bottom, a current balance layer positioned on the channel layer and a source electrode field layer positioned on the current balance layer;
in the step of forming the third trench, the third trench is of an enlarged slot structure, the inner wall of the third trench keeps a gap with the inner wall of the second trench, the width of the third trench is greater than that of the first trench, and the depth of the third trench is greater than the sum of the thicknesses of the active layer and the inner dielectric layer; when the third groove is formed, the top of the first oxidation isolation layer protrudes out of the bottom of the third groove;
the step of forming the barrier layer includes: forming a lightly doped region in the region of the drain electrode epitaxial layer between the protruding part of the first oxidation isolation layer and the active layer in an ion implantation mode; depositing a barrier metal layer on the top of the lightly doped region in a deposition mode, wherein the barrier metal layer is made of Ti, ni, mo and NiPt, and a Schottky barrier is formed in a contact region between the barrier metal layer and the lightly doped region after annealing;
forming a barrier layer in a deposition mode after forming a Schottky barrier, wherein the barrier layer covers the inner dielectric layer, the active layer, the barrier metal layer and the protruding parts of the first oxidation isolation layer, and the barrier layer is made of Ti, tiN and W;
in the step of forming the source layer, the source layer is made of metal; after the step of forming the source layer, annealing the source layer, and performing back thinning and back metallization on the back surface of the drain substrate.
The corresponding technical effects as described above can be achieved by using the above-described corresponding features by adopting the above-described preferred technical features.
The main purpose of the invention is realized by the following technical scheme:
a semiconductor chip device is provided, comprising: the field effect transistor structure possibly combined by any technical scheme comprises a drain epitaxial layer positioned below a processing surface, a source layer positioned on the processing surface, a barrier layer positioned between the first oxidation isolation layer and the active layer, and a source extension inverted fin and a gate embedded in the drain epitaxial layer, wherein a Schottky barrier is formed in the barrier layer; the grid electrode is arranged between the source electrode extension inverted fins, and symmetrical channels which are connected in parallel from the source electrode layer to the inside of the drain electrode epitaxial layer are formed on two sides of the grid electrode; preferably, symmetrical field resistors connected in parallel from the source layer to the drain epitaxial layer are further formed above the channel on both sides of the gate; preferably, the drain epitaxial layer forms a floating-gate inverted-pole junction below the gate at the position corresponding to the bottom of the gate; preferably, the drain epitaxial layer forms a shield gate bottom floating inverted pole type bottom junction at the bottom part corresponding to the source extension inverted fin.
By adopting the technical scheme, a plurality of vertical parallel channels defined in the thickness direction of the active layer are established by utilizing the source layer positioned on the processing surface and the grid embedded in the drain epitaxial layer, and the electron current can be uniformly output (or input) on the back surface. When the semiconductor chip device is arranged on the carrier plate, the drain contact connection is completed, so that the connection operation of one electrode position can be saved, and the problem of the leakage current on the back surface of the chip does not need to be considered along with the fact that the chip is thinner and thinner.
In summary, the present invention includes at least one of the following technical effects that contribute to the prior art:
1. a trench-type contact hole such as a third trench is formed on the isolation gate (specifically, the source extension inverted fin) where the first trench is located for filling the source layer, and one or more of the following effects are achieved: a. the third groove serving as the contact hole is positioned on the source electrode extending inverted fin serving as the isolation grid, and compared with a structure in which the contact hole is arranged between the isolation grids, the contact hole area of the third groove can be increased, so that the heat dissipation performance and the current performance of the device are improved, and meanwhile, the SOA (safe operating area) can be correspondingly improved by more than 10%; b. the third groove serving as a contact hole is arranged on the source electrode extending inverted fin serving as the shunt isolation gate, the size of the contact hole is kept, and meanwhile, the distance between the third groove and the gate can be increased, so that the safety margin in the manufacturing process can be increased, and the processing yield can be increased; c. compared with a planar contact hole generally designed in the prior art, the third trench serving as the contact hole can improve the reliability of UIS (Unclamped Inductive Switching) of the device; d. the contact hole is helped to extend the inverted fin short circuit in the source electrode of the whole isolation gate area to be connected with the source electrode of the device, compared with the original structure that only part of the area is short-circuited with the source electrode, the shielding gate of the whole device can simultaneously achieve charge balance without time delay among areas, and therefore the UIS of the device can be improved by more than 20%; e. a Schottky barrier is introduced between a source electrode and a drain electrode, the Schottky barrier has a lower forward voltage drop (VFsd) compared with a traditional PN junction, the forward voltage drop (VFsd) is less than 0.6V, the forward voltage drop (VFsd) of the traditional PN junction is often more than 0.6V, and the PN junction has a charge storage effect, so that the problems of large reverse charge (Qrr), large forward voltage drop (VFsd) and large reverse recovery charge (Qrr) can cause large loss of a device in the using process, high peak Voltage (VDS) and the like can be solved;
2. technical effects of the current balance layer with respect to the multi-layered structure active layer in configuration include: a. the addition of the layer is equivalent to that a resistor is introduced into each half-gate transistor corresponding to the source electrode in an equivalent circuit, so that the current of each transistor unit can be balanced, and the uniform and reliable temperature rise of the device can be increased; b. the reliability of parallel application of the device is improved;
3. technical effects on the configuration regarding the thick oxidation of the bottom of the isolation gate include: the thickness of a thermal oxidation layer at the bottom corner of the first trench is only 60-70% of the side wall due to different lattice structures, so that when an in-vivo field plate charge balance device is reversely blocked, an electric field is completely concentrated at the bottom of the isolation gate and a PN junction region, the addition of the oxidation isolation superposition block and the isolation gate floating counter region (such as a P region of an N-type field effect tube) is beneficial to further improving the bottom electric field, and the reliability of bottom thermal oxidation can be improved by introducing thick oxygen of the isolation gate;
4. the technical effects on the configuration of the floating inverted-pole type column bottom junction (specifically, the floating P column at the bottom of the isolation gate of the N-type field effect transistor) include: a. the charge balance region introduced into the column bottom junction and matched with the bulk field plate structure can realize the charge balance of EPI together, and better device performance can be obtained when the same blocking voltage is realized; b. the processing method is simplified, the processing difficulty is reduced, and the groove etching depth, the thermal oxidation time and the temperature can be reduced compared with a complete bulk field plate junction transistor structure; the growth test and ion implantation times of the epitaxial layer can be reduced relative to a complete isolation gate structure only with a groove;
5. the technical effects on the configuration of the floating-under-gate inverted junction (specifically, the floating-under-gate P region of the N-type field effect transistor) include: a. the grid oxygen reliability is improved, the electric field is totally concentrated at the bottom of the grid electrode and a PN junction area during reverse blocking, in order to reduce the probability that the Miller capacitor PN junction is closer to the bottom of the grid oxygen, but the closer the grid oxygen electric field is, the stronger the grid oxygen electric field is, the reliability of the device is influenced, and the breakdown characteristic is reduced; b. the UIS performance is improved, the electric field concentration at the bottom of the grid during UIS causes breakdown to influence the UIS, and the introduction of the floating-down reverse-pole junction under the grid reduces the electric field intensity and increases the UIS performance; C. reducing the Miller capacitance.
Drawings
FIG. 1 is a partial cross-sectional gate structure of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 2 is a schematic diagram of a drain substrate provided in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 3 is a schematic diagram illustrating the formation of first trenches parallel to each other by etching from the processing surface of the drain epitaxial layer during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
fig. 4 is a schematic diagram illustrating the formation of a floating bottom-gate type bottom-pillar junction at the bottom of a first trench by ion implantation in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 5 is a schematic illustration showing the formation of a first oxide isolation layer on the processing surface and within the first trench during the fabrication of a field effect transistor structure in accordance with some preferred embodiments of the present invention;
fig. 6 is a schematic diagram illustrating the formation of a source-extended fin in the first trench during the fabrication of the fet structure according to some preferred embodiments of the present invention;
fig. 7 is a schematic diagram illustrating the removal of the source-extended-fin and the first oxide isolation layer on the processing surface during the fabrication of the fet structure according to some preferred embodiments of the present invention;
FIG. 8 is a schematic illustration showing the formation of a mask layer on a processing surface during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 9 is a schematic diagram illustrating a second trench etched from the processing surface and forming an under-gate floating-inversion type junction at the bottom of the second trench in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 10 is a schematic view of forming a second oxide isolation layer in the processing surface and in the second trench during the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 11 is a schematic diagram illustrating the placement of a gate in a second trench during the fabrication of a field effect transistor structure according to some preferred embodiments of the invention;
FIG. 12 illustrates the formation of an active layer by energy implantation under the processing surface during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 13 is a schematic diagram illustrating the separation of an active layer into a channel layer and a field layer during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 14 is a schematic diagram illustrating a field layer region being divided into a current balance layer and a source field layer during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 15 is a schematic illustration showing the formation of an inter-dielectric layer over the active layer and over the gate during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 16 is a schematic diagram illustrating the formation of a third trench by inter-layer dielectric etching during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
fig. 17 is a schematic view illustrating formation of a schottky barrier in the third trench during fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 18 is a schematic diagram illustrating the formation of a barrier layer in a third trench during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
fig. 19 is a schematic illustration showing the formation of a source layer in the third trench during the fabrication of the fet structure according to some preferred embodiments of the present invention;
FIG. 20 is a schematic diagram illustrating the flow of electron current in the in-use state of the field effect transistor structure fabricated in accordance with some preferred embodiments of the present invention;
FIG. 21 is a partial cross-sectional view of a field effect transistor structure in accordance with a first alternative embodiment of the present invention;
fig. 22 is a schematic partial structure view of a second variation of a fet structure in a cross-cut gate according to the present invention;
fig. 23 is a schematic partial structure diagram of a fet structure according to a third variation of the present invention, in a cross-gate structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of embodiments for understanding the inventive concept of the present invention, and do not represent all embodiments, nor do they explain a unique embodiment. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention under the understanding of the inventive concept of the present invention are within the protection scope of the present invention.
It should be noted that, if the present invention relates to directional indications (such as up, down, left, right, front, back, 8230; \8230;), the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture, and if the specific posture is changed, the directional indications are correspondingly changed. In order to facilitate understanding of the technical solutions of the present invention, the field effect transistor structure, the manufacturing method thereof, and the chip device of the present invention will be described and explained in further detail below, but the scope of the present invention is not limited thereto. In the following embodiments, N-channel transistors are used, and may be adjusted to P-channel transistors in different example variations, and it should be understood by those skilled in the art that the source and drain referred to in the description are relative concepts, not absolute concepts, and in specific applications of the variation, the source referred to in the description may be used as a drain connection, the drain referred to in the description may be used as a source connection, and when the source referred to in the description is used as a source connection, the drain referred to in the description is necessarily used as a drain connection; the source described in the specification is connected as a drain, and the drain described in the specification is inevitably connected as a source. For the convenience of understanding the technical solution of the present application, the specification and the protection scope still use "source" and "drain", and actually are not limited to the source and the drain, but use the first electrode and the second electrode representing two different electric potentials. In addition, the term "counter electrode" as used herein means an electrode opposite to a base electrode, and for example, if the base electrode of a source/drain electrode is N-type, the counter electrode is P-type, and vice versa.
Fig. 1 is a partial cross-sectional gate structure of a field effect transistor structure according to some preferred embodiments of the present invention, fig. 2 to 17 are respective process steps of a field effect transistor structure according to some preferred embodiments of the present invention, and fig. 18 is a schematic in-use state of a field effect transistor structure according to some preferred embodiments of the present invention. The accompanying drawings illustrate various embodiments having a common component, and the various embodiments having differences or differences will be described with particularity. Therefore, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the following individual technical features or any combination thereof can be characterized in the same embodiment or whether a plurality of technical features mutually exclusive can be respectively characterized in different variation embodiments.
Referring to fig. 1, a field effect transistor structure disclosed in the present embodiment of the invention mainly includes a drain substrate 1, a source extended inverted fin 20, an active layer 30, a gate 40, a barrier layer 101, and a source layer 60, so as to realize the basic function of an electron current switch of the field effect transistor. The present embodiment is represented by an N-channel transistor, and those skilled in the art should be able to adjust the transistor to a P-channel transistor in the variation.
The drain substrate 1 is provided with a processing surface 11 and a corresponding back surface 12, wherein the processing surface 11 is provided with a first groove 13, the first groove 13 is parallel to the back surface, the inner wall of the first groove 13 is subjected to insulation processing, a source extending inverted fin 20 is arranged in the first groove 13, and the depth of the first groove 13 does not exceed the thickness of the drain epitaxial layer 10. The drain substrate 1 is a semiconductor wafer in a semiconductor process, and is a diced chip base layer in a product, the base material of the drain substrate 1 is usually silicon, and may also be silicon carbide, III-V or II-VI compound, and has conductivity after being doped with an electron-providing substance or a hole-providing substance, and the doped region is in an active region of the chip, either overall or in bulk, for example, heavy N-type doping. The drain substrate 1 is typically of monocrystalline structure, in particular N + monocrystalline silicon for an N-type transistor. The drain epitaxial layer 10 is a functional layer epitaxially grown from the drain substrate 1, and generally has the same crystal orientation as the drain substrate 1, and is also a single crystal structure, and is lower in conductivity than the drain substrate 1 in the case of an N-type transistor, specifically, N-single crystal silicon. One function of the drain epitaxial layer 10 is to provide a level of sharp variation in doping concentration between the drain epitaxial layer 10 and the drain substrate 1 to facilitate semiconductor fabrication of the vertical channel field effect transistor. The processing surface 11 is a processing surface of a semiconductor process, and the back surface 12 is a surface opposite to the processing surface 11. The first trenches 13 are formed by the processed surface 11, meaning that the first trenches 13 open towards the processed surface 11, the bottom of the first trenches 13 is towards the back surface 12, and the first trenches 13 do not penetrate the drain epitaxial layer 10. Although only two first grooves 13 are illustrated in the figure, the number of the grooves is more than two in reality, the number of the grooves can be adjusted, and the structure in fig. 1 can be repeatedly expanded on the left side and the right side; the preferred groove shape is a plurality of parallel straight bars on the processing surface 111, but may be various curved shapes having the same interval in parallel. The upper source extended inverted fin 20 is used to maintain the same field voltage as the source, the source extended inverted fin 20 is conductive, and the material is preferably polycrystalline conductive silicon or other conductive semiconductor material, which has the same or similar thermal expansion adaptability with the drain epitaxial layer 10; in other examples, it may also be a conductive material used in semiconductor processing, such as: tungsten, copper, aluminum, tungsten is commonly used. The source extension inverted fin 20 may have a single-layer structure as shown in fig. 1 or a multi-layer stacked structure.
The active layer 30 is formed on the processing surface 11 of the drain epitaxial layer 10, the active layer 30 is formed with second trenches 31 located between the first trenches 13, the inner walls of the second trenches 31 are insulated, the gate electrode 40 is disposed in the second trenches 31, and the second depth of the second trenches 31 is sufficient to penetrate the active layer 30 but smaller than the first depth of the first trenches 13. A portion of the active layer 30 (the channel layer) is turned on and off by the electric field of the gate electrode 40 to form a flow of electrons. In the preferred embodiment, the active layer 30 is formed by the drain epitaxial layer 10 internally, for example, by performing an ion implantation of a counter-type or an ion implantation of a homo-type on the drain epitaxial layer 10, and the active layer 30 and the drain epitaxial layer 10 have an integrally adapted lattice structure; in a variation, the active layer 30 is epitaxially grown from the surface of the drain epitaxial layer 10, so the active layer 30 can be formed in the processing surface 11 or on the processing surface 11. The bottom of the second trench 31 is higher than the bottom of the first trench 13, i.e., the bottom of the second trench 31 is closer to the processing surface 11 than the first trench 13. The gate 40 is shaped on the processing surface 11 to follow the shape of the source extended fin 20 to maintain the same spacing between them. The gate 40 is conductive, and the material is preferably polycrystalline conductive silicon or other conductive semiconductor material, which has the same or similar thermal expansion adaptability with the drain epitaxial layer 10; other conductive materials used in semiconductor processing may also be employed in other examples, such as: tungsten, copper, aluminum, tungsten is commonly used. The structure of the gate electrode 40 may be a single layer structure as shown in fig. 1 or a multi-layer stacked structure. The bottom shape of the gate 40 and the bottom shape of the source extended fin 20 may not be the same; for example, the bottom of the gate 40 is a downward protruding arc-shaped section, and the bottom of the source extended inverted fin 20 is an upward concave section, specifically, the bottom of the second oxide isolation layer 92 and the bottom of the first oxide isolation layer 91 plus the oxide isolation stacking block 93 are combined to form the following structures: the electric field intensity and the tolerance to the electric field of the bottom insulating layer are improved. For another example, the dimension of the floating inversion type bottom stud junction 70 corresponding to the width of the trench can be larger than the dimension of the floating inversion type bottom stud junction 80 under the gate, so that the width of the floating inversion type bottom stud junction 70 can exceed the width of the first trench 13.
An inter-dielectric layer 50 is formed on the active layer 30 and the gate 40, so that the gate 40 is an embedded structure; a third trench 51 aligned with the first trench 13 is formed from the inter-dielectric layer 50, the inner wall of the third trench 51 is not insulated, and the width and depth of the third trench 51 are sufficient to directly expose the edge of the active layer 30 and the bottom to expose the top of the source-extended inverted fin 20. The inter-dielectric layer 50 is insulating and separates the gate electrode 40 from the source electrode layer 60, and the material of the inter-dielectric layer 50 may be PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass), and the liquid coating method thereof ensures the thickness of the inter-dielectric layer 50, so as to effectively separate the source electrode from the gate electrode. Although only one inner dielectric layer 50 is illustrated, it may be a multi-layered stacked insulating structure in various variations. The third trench 51 is used as a contact hole for electrically connecting the source extended reversed fin 20 and the source layer 60 or/and the field layer electrically connecting the active layer 30 and the source layer 60, and the window width of the contact hole (the width of the third trench 51) should be larger than the width of the first trench 13 to enlarge the contact area; the depth of the third trench 51 cannot damage or penetrate the active layer 30 to avoid electrical short between the source and the drain. The embedded gate 40 can be electrically pulled out of the embedded region by its own end extension or connecting lead, or the gate connecting line can be pulled out by a conductive plug penetrating the inter-dielectric layer 50 outside the source region, so that the field potential of the gate 40 can be adjusted independently.
The barrier layer 101 is formed at the bottom of the third trench 51, and covers the exposed region of the drain epitaxial layer 10 at the bottom of the third trench 51. The barrier layer 101 includes a lightly doped region 102 on the drain epitaxial layer 10 and a barrier metal layer 103 on the lightly doped region 102, and a contact region of the lightly doped region 102 and the barrier metal layer 103 forms a schottky barrier. Compared with the conventional PN junction, the Schottky barrier between the source and the drain has lower forward voltage drop and lower forward voltage drop (VFsd), reverse charges (Qrr) can be effectively avoided, the loss of the device is low, the peak value of peak Voltage (VDS) is low, and the device is not easy to damage due to overvoltage. The material of the barrier metal layer 103 is preferably Ti, ni, mo, or NiPt.
A barrier layer 104 is formed on the barrier metal layer 103, the barrier layer 104 covers the protrusion portions of the inter-dielectric layer 50, the active layer 30, the barrier metal layer 103, and the first oxide isolation layer 91, and the material of the barrier layer 104 is preferably Ti, tiN, or W.
The source layer 60 is formed in the third trench 51 and covers the barrier layer 104 to turn on the source extended fin 20, and the inversion layer implantation thickness direction of the active layer 30 defines the channel length of the fet, instead of defining the channel length of the fet in the length direction of the active layer 30 as in the prior art, to provide multiple and short parallel transistor channels standing on the processing surface 11. In this embodiment, the source layer 60 covers the entire surface of the cell region on the processing surface 11 and fills the third trench 51, and the source layer 60 conducts the domain layer of the active layer 30 in addition to the source extension fin 20. The source layer 60 is conductive, preferably made of aluminum or other conductive metal material, and additionally has the function of a metal pad, so as to omit the manufacture of the metal pad; in other examples, the source layer 60 may be made of other conductive materials used in semiconductor processes, such as: tungsten, copper, polycrystalline conductive silicon. The structure of the source layer 60 may be a single layer structure as shown in fig. 1 or a stacked multilayer structure. The thickness direction of the inversion layer injection is specifically the thickness direction of the communication layer 32.
The basic principle of the embodiment is as follows: by forming the third trench 51 aligned with the first trench 13 from the inner dielectric layer 50, the inner wall of the third trench 51 is not insulated, and the width and depth of the third trench 51 are sufficient to directly expose the edge of the active layer 30 laterally and expose the top of the source extended inverse fin 20 at the bottom, so that the bottom of the source layer 60 is connected to the source extended inverse fin 20 and both sides of the source layer 60 are connected to the active layer 30, and the source extended inverse fin 20 has the function of an electron flow isolation gate; the source layer 60 conducts the active layer 30 on both sides of the third trench 51, and the active layer 30 can be conducted to the drain epitaxial layer 10 along the profile of both sides of the gate 40 insulated by the active layer 30, so that the channel length of the field effect transistor can be defined in the inversion layer injection thickness direction of the active layer 30, specifically, a transistor channel can be planned on each side profile of the gate 40 insulated by the gate 40, and parallel channels vertical and parallel to the processing surface 11 are formed on both sides of the embedded gate 40 due to the embedded depth of the gate 40 which breaks through the active layer 30 to the inside of the drain epitaxial layer 10; the back surface 12 of the drain substrate 1 can be used as a contact of a drain metal pad, the movement of electron current is from the processing surface 11 to the back surface 12 of the drain substrate 1, in the process, the half gate 40 of one side channel is opened after the shunting of the two sides of the third trench 51 and the insulation processing of the gate 40, and is dispersed on the back surface 12 of the drain substrate 1 under the field effect of the shunting of the source extended inverted fin 20 and the isolation gate, so that the conduction of the channels on the two sides of the two half gate transistors under the two adjacent source shunts is realized between the back surface 12 of the drain substrate 1 and the source extended inverted fin 20, the defect of the leakage current on the back surface 12 of the substrate originally is converted into beneficial and meaningful drain output, and the concentration of electron current such as a fuse effect on a local area of the back surface 12 of the drain substrate 1 is avoided.
Therefore, the circuit structure of the field effect transistor of the present application is to provide two half-gate channel structures (corresponding to the thickness of the channel layer 32 of the active layer 30 along each side of the gate 40) between two shunt isolation gates (corresponding to the source-extended fin 20), the source layer 60 shunts on the shunt isolation gates, the shunted electron flows are collected in the drain epitaxial layer 10 together with the adjacent shunted electron flows through the respective half-gate channel structures, and are uniformly distributed on the back surface of the drain substrate 1, for example, the electron flow a passing through the left third trench 51 reaches the left side of the middle half-gate as a/2, the electron flow B of the right third trench 51 reaches the right side of the middle half-gate as B/2, the electron flow reaching the back surface 12 of the drain substrate 1 between the corresponding left and right third trenches 51 is a/2 plus B/2, the back surface electron flow between the other adjacent third trenches 51 is B/2 plus C/2, and C is the electron flow of the next adjacent third trench 51, thereby achieving the back surface electron flow uniformity, and the back surface electron flow is no longer a technical problem.
Moreover, by utilizing the separation design and the structural conduction in the process of manufacturing the source layer 60 and the source extension inverted fin 20, the source layer 60 only needs to fill the third trench 51 with a larger width in the process, and does not need to fill the first trench 13 with a smaller width, and the material selection of the source extension inverted fin 20 has more freedom, so as to overcome the difficulty of filling the trench in the process, improve the thermal expansion adaptation degree with the drain epitaxial layer 10, and reduce the metal diffusion effect on the drain epitaxial layer 10.
In addition, a Schottky barrier is introduced between a source electrode and a drain electrode, the Schottky barrier has a lower forward voltage drop (VFsd) compared with a traditional PN junction, the forward voltage drop (VFsd) is less than 0.6V, the forward voltage drop (VFsd) of the traditional PN junction is often greater than 0.6V, and the PN junction has a charge storage effect, so that a large reverse charge (Qrr) exists, and the large forward voltage drop (VFsd) and the large reverse recovery charge (Qrr) can cause the problems of large loss and high peak Voltage (VDS) of a device in the using process.
Regarding the source layer 60 and the third trench 51 for filling the source layer 60, in a preferred example, the source layer 60 is further formed on the barrier layer 105; the width of the third trench 51 is larger than the width of the first trench 13. By the source layer 60 also formed on the barrier layer 105, the source layers 60 in adjacent two third trenches 51 are conducted to each other on the inter-dielectric layer 50 to enlarge the source contact, and the inter-dielectric layer 50 electrically insulates the top of the gate 40 from the extended source layer 60. By utilizing the width of the third trench 51 being greater than the width of the first trench 13, the top of the source-extended flip-chip 20 is effectively opened at the bottom of the third trench 51, and the third trench 51 has a contact hole function, so as to reduce the defect that the source layer 60 and the source-extended flip-chip 20 cannot be conducted due to the misalignment of the third trench 51 with respect to the first trench 13, and finally achieve the same electric field potential for the two in use. In another variation, the width of the third trench 51 may be smaller than that of the first trench 13, and the conduction between the source layer 60 and the source-extended inverted fin 20 can be achieved only by connecting the smaller third trench 51 in a plurality of contact holes with enlarged apertures in a partial region, which is different from the difficulty in implementing the process. In an example, the width of the first trench 13 is 0.2-3.0 um, the width of the second trench 31 is 0.21-4.0 um, and the width of the third trench 51 is 0.2-0.7 um. And the bottom height of the second trench 31 is between the bottom height of the first trench 13 and the bottom height of the third trench 51; in the example, the height of the bottom of the second trench 31 is different from that of the bottom of the first trench 13, and the depth of the first trench 13 from the processing surface 11 is 1.5-10 um.
In the embodiment of the active layer 30, since the active layer 30 is formed by internalization of the processed surface 11 of the drain epitaxial layer 10, the active layer 30 and the drain epitaxial layer 10 are lattice-matched, and there is no defect of an interface gap, and the channel structure of the transistor and the drain epitaxial layer 10 are integrated into a single structure, which is superior to an epitaxially grown active layer or channel layer in electrical stability. In another variation, the active layer 30 may be epitaxially formed, and the channel layer formed by either the intrinsic or the epitaxial method is a single crystal structure, and the channel performance is stable, but the channel layer formed by the intrinsic drain epitaxial layer 10 has a better lattice matching degree with the drain epitaxial layer 10. In an example, the thickness of the active layer 30 is 0.5 to 3um.
As to further details of the active layer 30, in a preferred example, the active layer 30 is a multilayer structure including: a channel layer 32 located at the bottom, a current balance layer 33 located on the channel layer 32, a source domain layer 34 located on the current balance layer 33; the depth of the third trench 51 is such that the third trench 51 penetrates the source region layer 34 and the current balance layer 33. In the multi-layer structure of the active layer 30, the current balance layer 33 is formed between the source region layer 34 and the channel layer 32, and the thickness of the current balance layer 33 has a resistance function on both sides of the gate 40 after the insulation treatment, so as to provide a plurality of short-distance parallel resistors standing on the treatment surface 11, which are respectively connected between the corresponding parallel transistor channels and the source region layer 34 in a conductive manner, thereby avoiding the burning of the respective parallel transistor channels under a larger electron current, and eliminating the fuse effect. In an exemplary structure of an N-type transistor, the channel layer 32 is a P-type doped region, the current balance layer 33 and the source field layer 34 are N-type doped regions, wherein the current balance layer 33 is lower than the source field layer 34 with respect to N-type doping concentration, i.e., the current balance layer 33 is lightly N-type doped, and the source field layer 34 is heavily N-type doped; the resistance of the current balance layer 33 is higher than that of the source region layer 34, and the source region layer 34 tends to be conductive. While the P-type dopant species of the channel layer 32 may specifically be boron (B), the channeling of the channel layer 32 occurs in a thickness direction, rather than in a surface direction that is the same as or parallel to the processing surface 11. In another variation, the active layer 30 may include only: a channel layer 32 at the bottom, and a source field layer 34 on the channel layer 32. In an example, the thickness of the channel layer 32 is 0.1-2 um, the thickness of the current balance layer 33 is 0.05-1 um, and the thickness of the source region layer 34 is 0.05-1 um.
Regarding the insulation embodiment of the first trench 13, in a preferred example, the bottom of the first trench 13 is subjected to a thick oxidation process so that the insulation thickness of the first trench 13 is greater at the bottom of the inner wall than at the side of the inner wall. By using the insulation thickness of the first trench 13 to be greater at the bottom of the inner wall than at the side of the inner wall, the oxidation isolation stacking block 93 is formed at the bottom of the inner wall of the first trench 13, thereby avoiding the formation of electron tunneling between the bottom of the source extension inverted fin 20 and the drain epitaxial layer 10, improving the avalanche breakdown resistance of the trench bottom and the gate oxide modification resistance of ion implantation in the post-process, and simultaneously reducing the field effect at the bottom of the source extension inverted fin 20, so that the shunt field effect of the shunt isolation gate is formed in the drain epitaxial layer 10 at both sides of the source extension inverted fin 20. In an example, the thickness of the first oxide isolation layer 91 on the sidewall of the first trench 13 is 700-13000A, and the combined thickness of the first oxide isolation layer 91 on the bottom of the first trench 13 and the oxide isolation stacking block 93 is 1000-18000A; the thickness of the second oxide isolation layer 92 in the second trench 31 is 300-1300A.
In a specific embodiment of the drain epitaxial layer 10, in a preferred example, the drain epitaxial layer 10 is further formed with a deep implanted region at a position corresponding to the bottom of the first trench 13 to form a shield gate bottom floating inversion type bottom stud junction 70. The floating inverted-pole type bottom junction 70 at the bottom of the shielding gate is exposed from the bottom of the source extension inverted-fin 20, so that the charge balance of the floating inverted-pole type column to the adjacent inverted-pole type column is increased, the phenomenon that electron current between the source extension inverted-fins 20 in different regions is collected in advance is avoided, the depth of the first groove 13 can be reduced in manufacturing, the thickness of a bottom insulating layer can also be reduced, and the filling formation of the source extension inverted-fin 20 is facilitated. In the illustrated example, the counter-type pillar bottom junction 70 is doped P-type; the reverse-pole bottom junction 70 is used for improving the shunting isolation effect of the source extension inverted fin 20 and preventing the electron current from being collected in the drain epitaxial layer 10 in advance; therefore, the trench depth of the first trench 13 can be reduced under the same performance, and the difficulty of filling the trench with the source extension inverse fin 20 is reduced. In the example, the depth of the bottom of the reverse-pole type bottom stud junction 70 does not exceed the thickness of the drain epitaxial layer 10, so that the drain epitaxial layer 10 is not completely blocked by the reverse-pole type bottom stud junction 70 between the first trenches 13, reverse-pole type doping substances cannot enter the drain substrate 1, and the existence of the horizontal plane 17 for clearly changing the doping concentration in the figure is maintained in the manufacturing process, so that the vertical channel type field effect transistor has better product stability.
In another embodiment of the drain epitaxial layer 10 that can be used in parallel or simultaneously, in a preferred example, the drain epitaxial layer 10 is further formed with an implanted region at a position corresponding to the bottom of the second trench 31 to form a floating-gate-down inversion junction 80. The floating under-gate reverse-pole junction 80 is penetrated out from the bottom of the gate 40, so that the bottom of the gate insulating layer is prevented from being damaged by a bottom concentrated electric field, the reliability of the gate insulating layer is improved, and the breakdown voltage resistance reduction caused by the concentration of the bottom gate oxide electric field is avoided. The electron current on one side of the insulated side of the gate 40 creeps along the bottom profile of the gate 40 and returns to the other side of the insulated side of the gate 40, and both sides of the insulated side of the gate 40 can enter the drain epitaxial layer 10. In the example, the under-gate floating-cathode junction 80 is doped P-type, so that the drain epitaxial layer 10 forms a resistive effect under the gate 40, and the under-gate floating-cathode junction 80 can be adjusted to have a non-channel function based on the adjustment of the P-type doping concentration or/and the N-type and P-type mixed doping.
In a preferred exemplary use, by the electric field effect of the gate 40, the electron flow from the source layer 60 is shunted by the side of the third trench 51 to the drain epitaxial layer 10 between the first trenches 13 along one of the symmetrical sides of the sidewall profile of the second trench 31, and is uniform at the back surface 12 of the drain epitaxial layer 10 or the drain metal pad disposed on the back surface 12. By means of the electric field effect of the gate 40, a uniform separation of the electron current is achieved from the top surface to the bottom surface across the third trenches 51 on the treatment surface 11 and between the first trenches 13 of the drain epitaxial layer 10.
In addition, referring to fig. 2 to fig. 17, another embodiment of the present invention further provides a method for manufacturing a field effect transistor structure, which is used for manufacturing a field effect transistor structure combined by any of the above-mentioned technical solutions, and the process steps are described as follows.
Referring first to fig. 2, a corresponding step S2 is to provide a drain substrate 1 having a treated surface 11 provided by a drain epitaxial layer 10 and a corresponding back surface 12; in this step, the drain substrate 1 is usually in the form of a wafer, specifically a silicon wafer. A surface acidizing film 14 is formed on the treated surface 11 of the drain epitaxial layer 10, and has the function of a hard mask so as to facilitate the formation of the first trench 13 in the later process. In the example, the drain substrate 1 with the drain epitaxial layer 10 is specifically an EPI wafer, the base layer of the drain substrate 1 is specifically a silicon substrate, i.e. the body region 15 in fig. 2, the epitaxial structure is epitaxially grown above the body region 15 to the processing surface 11, i.e. the drain epitaxial layer 10, so that the drain epitaxial layer 10 is functionally conductive as an epitaxial structure portion between the processing surface 11 and the back surface 12 and has the same single crystal structure and crystal orientation as the silicon substrate wafer, and the body region 15 is conductive of a semiconductor material. In an NFET structure, the body region 15 is specifically N + single crystal silicon and the drain epitaxial layer 10 is specifically N-single crystal silicon. A doping concentration sharp variation horizontal plane 17 is formed between the body region 15 and the drain epitaxial layer 10 and is parallel to the processing surface 11, so that the yield and the yield of the vertical channel can be kept. The body region 15 is provided in the subsequent processes of fig. 3 to 17 until the back grinding, but the illustration is omitted, the body region 15 is present to maintain the basic physical structure of the substrate as a process carrier, the thickness of the body region 15 is greatly reduced after the back grinding, but the drain epitaxial layer 10 is not damaged, and the thinned body region 15 in the chip product may or may not be retained. The above epitaxial structure is selected as appropriate according to device blocking voltage and device parameter requirements, the epitaxial structure is N-type but not limited to N-type, and the crystal orientation <100> is not limited to this crystal orientation.
Referring to fig. 3, in step S3, first trenches 13 parallel to each other are etched from the processing surface 11, and the surface acidification film 14 is removed after the first trenches 13 are formed. The material of the surface acidification film 14 is silicon oxide, the thickness is 1000A-8000A, or the surface deposition masking film can be selected to replace, the material of the surface deposition masking film is silicon nitride but is not limited to silicon nitride. The pattern of the area masking film is selected by photoetching and etching modes, the field plate groove of the shielding body is etched, and the etching depth of the first groove 13 is 1.5-10 um according to different characteristics of devices.
Referring to fig. 4, as an optional step S4, after the steps of providing the drain substrate and forming the first trench 13, the method further includes: and forming a shield gate bottom floating inverted pole type bottom column junction 70 at the part, corresponding to the bottom of the first trench 13, of the drain epitaxial layer 10 by ion implantation. Specific example substeps include: s41, before injecting the floating inverted pole type bottom pillar junction 70 at the bottom of the shielding grid, growing a masking oxide layer with the growth thickness of 200-800A; s42, P column implant, implant B11 may include multiple implants, implant energy 20k-2Mev, implant dose 10 11 ～10 14 ions/cm 2 To form a floating reversed-pole type pillar-bottom junction 70 at the bottom of the shielding grid as shown in fig. 4, wherein the depth of the pillar-bottom junction is 0.5-5 um; s43, forming a sacrificial oxide layer, wherein the oxidation temperature is 700-1100 ℃, and the thickness is 300-1000A; s44, removing the sacrificial oxide layer in a selective dry etching mode; and S45, cleaning the drain electrode epitaxial layer 10. This step is for forming a reverse-polarity type bottom stud junction and cleaning the first trench 13, avoiding adverse effects of implantation of impurities on the insulation process of the first trench 13.
Referring to fig. 5, in step S5, a first oxide isolation layer 91 is formed in the processed surface 11 and the first trench 13 to insulate the inner wall of the first trench 13. The first oxide isolation layer 91 is specifically a thermal oxide layer or/and a deposited oxide layer, but is not limited to these two, and the thickness of the oxide layer may be 700 to 13000A according to the device parameter requirements.
Referring again to fig. 5, the step of forming the first oxide isolation layer 91 includes: forming a first oxide isolation layer 91 by thermal oxidation or precipitation; then forming a sidewall protection layer in the first trench 13; forming an opening at the bottom of the first trench 13 by anisotropically etching the sidewall protection layer; forming an oxidation isolation stacking block 93 in the opening of the side wall protection layer; selectively etching and removing the side wall protection layer to expose the first oxide isolation layer 91, wherein the thickness of the first oxide isolation layer 91 and the oxide isolation superposition block 93 at the bottom of the inner wall is larger than that of the first oxide isolation layer 91 at the side part of the inner wall; specifically, the first oxide isolation layer 91 is made of silicon oxide, and the sidewall protection layer is made of silicon nitride. The thickness of the sidewall protection layer, such as silicon nitride, may be between 500 and 10000A. When the oxide isolation stack block 93 may be formed on the processing surface 11 after being formed as a thick oxide layer on the bottom of the trench in an anisotropic deposition manner, the CMP may be used to remove the sidewall protection layer on the processing surface 11 and the excess portions of the oxide isolation stack block 93, and then selectively and chemically etch away the sidewall protection layer on the sidewall of the first trench 13.
Referring to fig. 6 and 7, the source extension inverse fin 20 is disposed in the first trench 13 by deposition filling, the depth of the first trench 13 does not exceed the thickness of the drain epitaxial layer 10, and the source extension inverse fin 20 and the first oxide isolation layer 91 are removed on the processing surface 11. Fig. 6 corresponds to step S6 of forming a large area of the source-extended inverse fin 20, and fig. 7 corresponds to step S7 of trimming the shape of the source-extended inverse fin 20. One example, but not limiting, of the process conditions of step S6 is: s61, depositing polycrystalline silicon (Poly) in the first groove 13 and forming on the processing surface 11; s62, doping and implanting dopants in an in-stu mode to enable the polycrystalline silicon to have conductivity, wherein the doping concentration is 10 18 ～10 21 ions/cm 3 The thickness is 1000-15000A.
Referring to fig. 7, as an optional step S7 after S6, in the step of disposing the source-extended reversed fin 20, the source-extended reversed fin 20 and the first oxide isolation layer 91 are removed from the processing surface 11, and the removal method includes Chemical Mechanical Polishing (CMP) or/and etch back (etch back); preferably, the material of the source extended fin 20 includes conductive polysilicon.
Referring to fig. 8, as a preceding step included in the step of forming the second trench 31, step S8 is: a mask layer 41 is formed on the processing surface 11 to cover the processing surface 11 and the top of the source extended fin 20. The mask layer 41 is used as a surface deposition masking film layer, and is made of, but not limited to, silicon oxide (SIO 2) or silicon nitride (SIN), and the thickness is 1000A to 8000A.
Referring to FIG. 9, corresponding to step S9, a mask layer is formedThe patterning of 41 is to etch from the processing surface 11 to form second trenches 31 between the first trenches 13, the second depth of the second trenches 31 being smaller than the first depth of the first trenches 13; referring again to fig. 9, preferably, after the second trench 31 is formed, an under-gate floating-type junction 80 is formed in the drain epitaxial layer 10 at a position corresponding to the bottom of the second trench 31 by ion implantation. An exemplary specific process of step S9 includes: s91, selecting a hollow-out area of the mask layer 41 by photoetching and etching; s92, forming a second groove 31 by etching, wherein the depth of the second groove 31 is 0.5-2.0 um; s93, forming a screen oxide layer (screen oxide) in the second groove 31, and growing to a thickness of 200-800A; s94, the ion implantation B11 comprises multiple times of implantation with the implantation energy of 20 to 200kev and the implantation dosage of 10 11 ～10 13 ions/cm 2 To form an under-gate floating inversion junction 80 as shown in fig. 9.
Referring to fig. 10, in step S10, a second oxide isolation layer 92 is formed in the processed surface 11 and the second trench 31 to insulate the inner wall of the second trench 31. Referring again to fig. 10, in the step of forming the second oxide isolation layer 92, the second oxide isolation layer 92 is specifically a gate oxide layer, and the gate oxide layer is formed on the inner wall of the second trench 31 and the processing surface 11 by thermal oxidation or thermal oxidation plus deposition; the oxidation temperature of the gate oxide layer is 700-1100 ℃, and the thickness is 300-1300A. Preferably, the step S10 further includes, before the gate oxide layer is formed, forming a sacrificial gate oxide layer on the inner wall of the second trench 31, where the oxidation temperature of the sacrificial gate oxide layer is 700-1100 ℃ and the thickness of the sacrificial gate oxide layer is 300-1000A, and then removing the sacrificial gate oxide layer and cleaning the drain epitaxial layer 10, in order to remove the adverse effect on the surface of the inner wall of the second trench 31 during ion implantation and remove the implanted ions accumulated on the surface.
Referring to fig. 11, in step S11, a gate 40 is disposed in the second trench 31 by deposition filling. In the step of disposing the gate 40, the method for removing the portion of the gate 40 on the processing surface 11 includes chemical mechanical polishing or/and back etching; preferably, the material of the gate electrode 40 includes conductive polysilicon containing dopant ions. One example, but not limiting, of the process conditions of step S11 is: s111, depositing polysilicon (Poly) in the second trench 31 and forming on the processing surface 11; s112. Doping and implanting dopant in-stu manner to make polysilicon conductive, with doping concentration of 10 18 ～10 21 ions/cm 3 The thickness is between 1000 and 15000A; s113, removing the excess conductive polysilicon on the processing surface 11 by Chemical Mechanical Polishing (CMP) or/and etch back (etch back) to obtain the gate 40 in the second trench 31.
Referring to fig. 12, in step S12, the active layer 30 is formed under the processed surface 11 of the drain epitaxial layer 10 by energy implantation, and the thickness and depth of the active layer 30 are within the range that the second depth of the second trench 31 can penetrate. In the step of forming the active layer 30, the active layer 30 is formed by internalization of the treated surface 11 of the drain epitaxial layer 10; the active layer 30 includes a channel layer 32 on the bottom, a current balance layer 33 on the channel layer 32, and a source domain layer 34 on the current balance layer 33. An exemplary but not limiting process condition of step S12 is: s121, defining a channel region through photoetching; s122, implanting B11 for multiple times to form a P-body region, wherein the implantation energy is 20-800 kev and the implantation dose is 10 12 ～10 14 ions/cm 2 To form the active layer 30.
Referring to fig. 13, as an optional step S13, a positive type implantation is performed in the active layer 30 to form a field layer on the upper layer of the active layer 30, so as to define an upper boundary of the channel layer 32 and a lower boundary of the current balance layer 33 on the lower layer of the active layer 30. One exemplary, but not limiting, process condition of step S13 is: s131, defining a channel region by photoetching; s132, implanting As or P for multiple times to form an N-type current balance layer, with implantation energy of 20-400 kev and implantation dose of 10 13 ～10 15 ions/cm 2 To form a current balancing layer 33 of the active layer 30 and to define a channel layer 32.
Referring to fig. 14, as an optional step S14, a source region layer 34 is formed by performing a positive type implantation in the region layer of the active layer 30 to define an upper boundary of the current balance layer 33 and a lower boundary of the source region layer 34. One example, but not limiting, of the process conditions of step S14 is: s141, implanting As or P for multiple times to form N-type source layer with implantation energy of 20-100 kev and implantation dose of 10 14 ～10 16 ions/cm 2 To form the source region layer 34 of the active layer 30 and define the current balance layer 33.
Referring to fig. 15, in step S15, an inter-dielectric layer 50 is deposited on the active layer 30 and the gate 40 to form an embedded gate 40. One exemplary, but not limiting, process condition of step S15 is: the deposited dielectric layer is specifically a combination of LTO (low temperature silicon oxide) or HTO (high temperature silicon oxide) and BPSG (borophosphosilicate glass) or PSG (phosphosilicate glass), wherein the thickness of the LTO or HTO is 500-3000A, and the thickness of the BPSG or PSG is 2000-10000A.
Referring to fig. 16, in step S16, a third trench 51 aligned with the first trench 13 is formed by etching the ild layer 50, when the third trench 51 is formed, the top of the first oxide isolation layer 91 protrudes from the bottom of the third trench 51, the inner wall of the third trench 51 is not insulated, and the width and depth of the third trench 51 are sufficient to directly expose the edge of the active layer 30 and the bottom of the third trench to expose the top of the source-extended flipper fin 20. In the step of forming the third trench 51, it is preferable that the third trench 51 is an enlarged trench hole structure, an inner wall of the third trench 51 is spaced apart from an inner wall of the second trench 31, a width of the third trench 51 is greater than a width of the first trench 13, and a depth of the third trench 51 is greater than a sum of thicknesses of the active layer 30 and the inner dielectric layer 50. One example, but not limiting, of the process conditions of step S16 is: s161, defining a contact hole region by photolithography to predefine a width of the third trench 51 to be greater than a width of the first trench 13 and less than a gap (spacing) between two adjacent second trenches 31; and S162, etching is carried out to form a third groove 51.
Referring to fig. 17, in step S17, a lightly doped region 102 is formed in the region of the drain epitaxial layer 10 between the protruding portion of the first oxide isolation layer 91 and the active layer 30 by implanting B11 with an angled ion implantation, and then a barrier metal layer 103 is deposited on top of the lightly doped region 102, and the barrier metal layer 103 forms a schottky barrier at the contact region with the lightly doped region 102 after annealing. One exemplary, but not limiting, process condition of step S17 is: the angled ion implantation B11 comprises multiple implantations with implantation energy of 20-200kev and implantation dosage of 10 9 -10 13 ions/cm 2 To form lightly doped regions 102, depositing a barrier metalThe material of layer 103 is specifically Ti, ni, mo or NiPt.
Referring to fig. 18, in step S18, after forming the schottky barrier, a barrier layer 104 is deposited, and the barrier layer 104 covers the protrusion portions of the ild 50, the active layer 30, the barrier metal layer 103, and the first oxide isolation layer 91. An exemplary but not limiting process condition of step S18 is: the material of the deposited barrier layer 104 is Ti, tiN or W.
Referring to fig. 19, corresponding to step S19, a source layer 60 is formed in the third trench 51 to turn on the source extended fin 20, and the inversion layer implantation thickness direction of the active layer 30 defines the channel length of the field effect transistor. In the step of forming the source layer 60, the source layer 60 is further formed on the barrier layer 104, and the material of the source layer 60 is metal; after the step of forming the source layer 60, the source layer 60 is annealed to perform back thinning and back metallization on the back surface 12 of the drain substrate 1. The source layer 60 is specifically made of metal, and a source contact pad may be provided on the upper surface of the source layer 60, and a drain contact pad 16 may be provided under the field effect transistor, and is formed by metallization of the back surface 12, and the structure of the field effect transistor is located between the metal pads of the source and drain.
The basic principle of the embodiment of the method is as follows: by using the pre-fabrication of the source extension inverted fin 20, the process difficulty of filling the source extension in the trench of the drain epitaxial layer 10 in the semiconductor manufacturing process is reduced, and finally the double inverted fin inter-half gate field effect transistor is manufactured.
An embodiment of the present invention further provides a semiconductor chip device, including: the field effect transistor structure that may be combined with any of the above embodiments, or used in conjunction with fig. 20, includes a drain epitaxial layer 10 below the processing surface 11, a source layer 60 on the processing surface 11, and a source extension fin 20 and a gate 40 embedded in the drain epitaxial layer 10; the gate 40 is arranged between the source extended inverted fins 20, and symmetrical channels which are connected in parallel from the source layer 60 to the inside of the drain epitaxial layer 10 are formed on two sides of the gate 40; preferably, a pair of symmetrical field resistors connected in parallel from the source layer 60 to the drain epitaxial layer 10 are further formed above the channel on both sides of the gate 40; preferably, the drain epitaxial layer 10 forms a floating-gate inversion junction 80 under the gate at the bottom of the corresponding gate 40; preferably, the drain epitaxial layer 10 forms a shield gate bottom floating-up inversion type bottom stud junction 70 at a bottom portion corresponding to the source extended reciprocal fin 20.
The basic principle of the embodiment is as follows: the source layer 60, which is located on the processing surface 11, and the gate 40, which is embedded in the drain epitaxial layer 10, establish a plurality of vertical parallel channels defined by the thickness direction of the active layer 30, and the electron current can be uniformly output (or input) to the back surface 12 of the drain substrate 1. When the semiconductor chip device is arranged on the carrier plate, the drain contact connection is completed, the connection operation of an electrode position can be saved, and the problem of the leakage current on the back surface of the chip does not need to be considered along with the fact that the chip is thinner and thinner. The electron current is shunted by the source layer 60, under the electric field effect of the gate 40, the channel layer 32 is longitudinally conducted to reach the back surface 12 of the drain substrate 1, the source extended inverted fin 20 can prevent the electron current from collecting in advance in the drain epitaxial layer 10, and the source layer 60 and the back surface 12 are in a shunting staggered isolation gate form, so that a more uniform electron current distribution is formed, and the semiconductor power device is particularly suitable for application. In addition, a Schottky barrier is introduced between the source electrode and the drain electrode, the Schottky barrier has lower forward voltage drop (VFsd) compared with the conventional PN junction, the generation of reverse charges (Qrr) can be effectively avoided, the loss of the device is small, the peak value of peak Voltage (VDS) is low, and the device is not easy to damage due to overvoltage.
Fig. 21 shows a first variation of the field effect transistor structure according to the present invention, in which the transistor includes a bottom drain epitaxial layer 10, a top source layer 60, and a source-extended fin 20 and a gate 40 embedded in the drain epitaxial layer 10, in a cross-gate partial structure; the gate 40 is arranged between the source extended inverted fins 20, and a pair of symmetrical channels connected in parallel from the source layer to the inside of the drain epitaxial layer are formed on both sides of the gate 20, and are located at the edges of the channel layer 32 along the thickness direction of the channel layer on both sides of the gate 40 in fig. 19; in this variation, a pair of symmetrical field resistors connected in parallel from the source layer 60 to the drain epitaxial layer 10 is further formed above the channel layer 32 on both sides of the gate 20, and is located at the edges of the current balance layer 33 along the thickness direction of the current balance layer on both sides of the gate 40; in comparison with the above preferred embodiment, the first modified embodiment omits the fabrication of the under gate floating inversion junction 80. One of the main functions of the floating-under-gate inversion junction 80 is to reduce the electron current breakdown at the bottom of the gate 20, resulting in UIS (unclamped inductive switching) performance. The omission of the floating-gate inversion junction 80 under the gate may change some electrical properties of the field effect transistor, but the basic heat dissipation performance, SOA improvement, semiconductor manufacturing process yield, and UIS reliability of the device may also be maintained. This configuration can be used where there is already sufficient gate oxide reliability and the fabrication of the floating-gate-under-gate inversion junction 80 can be omitted to simplify the semiconductor process.
Fig. 22 shows a second variation of the fet structure according to the present invention, in which the fet comprises a drain epi layer 10 at the bottom, a source layer 60 at the top, and a source-extended fin 20 and a gate 40 embedded in the drain epi layer 10 in a cross-gate local structure; the gate 40 is arranged between the source extended inverted fins 20, and a pair of symmetrical channels connected in parallel from the source layer to the inside of the drain epitaxial layer are formed on both sides of the gate 20, and are located at the edges of the channel layer 32 along the thickness direction of the channel layer on both sides of the gate 40 in fig. 20; in the second modified embodiment, compared with the first modified embodiment, the fabrication of the floating inversion-type pillar-bottom junction 70 is omitted; in contrast to the preferred embodiment, the floating-bottom and floating- bottom under-gate junctions 70, 80 are omitted. Basic heat dissipation performance, SOA improvement, semiconductor manufacturing process yield and UIS reliability of the device can be maintained. This architecture may be used where sufficient shield gate depth (the depth of the source-extended fin 20 embedded in the drain epitaxial layer 10) and gate oxide reliability are already available to simplify the semiconductor process. One of the main functions of the floating gate type bottom stud junction 70 in the semiconductor process is to reduce the etching depth of the first trench 13, reduce the thermal oxidation time and the process temperature, increase the process window, improve the yield, and omit the manufacturing of the floating gate type bottom stud junction 70 when the trench process capability and the accuracy of the semiconductor process are better.
Fig. 23 shows a third variation of the fet structure according to the present invention, in which the fet structure includes a bottom drain epi layer 10, a top source layer 60, and a source extended fin 20 and a gate 40 embedded in the drain epi layer 10; the gate 40 is arranged between the source extended inverted fins 20, and a pair of symmetrical channels connected in parallel from the source layer to the inside of the drain epitaxial layer are formed on both sides of the gate 20, and are located at the edges of the channel layer 32 along the thickness direction of the channel layer on both sides of the gate 40 in fig. 21; in contrast to the aforementioned second variant, the third variant omits the fabrication of the current balancing layer 33 and the oxidation isolation stack 93, i.e. the active layer 30 only includes the channel layer 32 and the source-domain layer 34 or/and does not require the fabrication of the oxidation isolation stack 93; compared with the first modified embodiment, the fabrication of the current balance layer 33, the oxidation isolation stacking block 93 and the floating reverse-pole type bottom stud junction 70 is omitted; compared with the previous preferred embodiment, the fabrication of the current balance layer 33, the oxide isolation stack block 93, the floating-to-bottom-of-column junction 70 and the floating-to-bottom-of-gate junction 80 is omitted. Basic heat dissipation performance, SOA improvement, semiconductor manufacturing process yield and UIS reliability of the device can be maintained. This architecture can be used where there is already sufficient uniformity of device temperature rise, sufficient shield gate depth (depth of source extension fin 20 embedded in drain epitaxial layer 10) and gate oxide reliability to simplify semiconductor processing. One of the main roles of the current balancing layer 33 is: the edge along the layer thickness direction on both sides of the gate 40 is equivalent to introducing a resistor at the source in the equivalent circuit of the transistor circuit structure to balance the current of the individual transistor units connected in parallel, and when the temperature rise of each transistor unit is uniform, the fabrication of the current balance layer 33 can be omitted. One of the main roles of the oxidation isolation building block 93 is: the problem that the electric field is completely concentrated at the bottom of the shielding grid when the internal field plate charge balance device is reversely blocked is solved by improving that the oxide layer at the bottom of the first trench 13 is too thin, and when the thickness of the oxide layer at the bottom of the first trench 13 is close to that of the side wall oxide layer (> 80%) or the requirement that the electric field is concentrated at the bottom of the shielding grid is not high, the manufacturing of the oxidation isolation superposition block 93 can be omitted.
Any of the floating-bottom-of-the-column junction 70, the floating-bottom-of-the-gate bottom-of-the-column junction 80, the oxide isolation stack 93, the current balance layer 33, or any combination thereof in the above preferred embodiment and the first to third variations is within the scope of the present invention.
The embodiments of the present invention are only used as preferred embodiments for understanding or implementing the technical solution of the present invention, and not to limit the scope of the present invention, and all equivalent changes made by the structure, shape and principle of the present invention should be covered by the scope of the present invention.
Claims (10)
1. A field effect transistor structure, comprising:
the drain electrode substrate is provided with a processing surface and a corresponding back surface, the processing surface is provided with first grooves which are parallel to each other, the inner walls of the first grooves are subjected to insulation processing to form first oxidation isolation layers, source electrode extension inverted fins are arranged in the first grooves, and the depth of the first grooves does not exceed the thickness of the drain electrode epitaxial layer;
an active layer formed in the drain electrode epitaxial layer, wherein second grooves are formed between the first grooves by the active layer, the inner walls of the second grooves are subjected to insulation treatment, a grid electrode is arranged in the second grooves, and the second depth of the second grooves is enough to penetrate through the active layer and is smaller than the first depth of the first grooves;
the inner dielectric layer is formed on the active layer and the grid electrode, so that the grid electrode is of an embedded structure; forming a third trench aligned with the first trench from the inner dielectric layer, wherein the inner wall of the third trench is not subjected to insulation treatment, and the width and depth of the third trench are sufficient to directly expose the edge of the active layer from the side and expose the top of the source extended inverted fin from the bottom;
the barrier layer is formed at the bottom of the third groove to cover the exposed area of the drain electrode epitaxial layer at the bottom of the third groove; a source layer formed on the processing surface and filled in the third trench to conduct the source extended inverted fin, wherein an inversion layer of the active layer is implanted in a thickness direction to define a channel length of the field effect transistor;
wherein the third trench extends through the active layer, the barrier layer being located at a bottom corner of the third trench; the barrier layer includes: the Schottky barrier is formed by a contact region of the lightly doped region and the barrier metal layer.
2. The field effect transistor structure of claim 1, wherein said active layer is formed by internalization of said treated surface of said drain epitaxial layer; the width of the third groove is larger than that of the first groove;
the active layer is a multilayer structure comprising: the current balancing device comprises a channel layer positioned at the bottom, a current balancing layer positioned on the channel layer and a source electrode field layer positioned on the current balancing layer; the depth of the third trench is such that the third trench passes through the source-region layer and the current-balance layer.
3. The field effect transistor structure of claim 1 wherein the bottom of the first trench is subjected to a thick oxidation process such that the insulation thickness of the first trench is greater at the bottom of the inner wall than at the sides of the inner wall.
4. The field effect transistor structure of claim 1, wherein the drain epitaxial layer further forms a deep implanted region at a portion corresponding to the bottom of the first trench to form a shielded gate bottom floating inversion type bottom-of-pillar junction.
5. The field effect transistor structure of claim 1, wherein the drain epitaxial layer is further formed with an implanted region at a portion corresponding to a bottom of the second trench to form an under-gate floating-inversion junction.
6. The field effect transistor structure of any of claims 1-5, wherein electron flow from the source layer is shunted by a side of the third trench to the drain substrate between the first trenches along a symmetrical side of a sidewall profile of the second trench, and is uniform at the backside of the drain epitaxial layer or a drain metal pad disposed at the backside, by an electric field effect of the gate.
7. A method of fabricating a field effect transistor structure, comprising:
providing a drain electrode substrate, wherein the drain electrode substrate is provided with a processing surface provided by a drain electrode epitaxial layer and a corresponding back surface, and first grooves which are parallel to each other are formed by etching the processing surface;
forming a first oxidation isolation layer in the processing surface and the first groove to enable the inner wall of the first groove to be subjected to insulation processing; arranging a source extension inverted fin in the first groove in a deposition filling mode, and removing the source extension inverted fin and the part of the first oxidation isolation layer on the processing surface, wherein the depth of the first groove does not exceed the thickness of the drain electrode epitaxial layer; forming second grooves between the first grooves by etching the processing surface, wherein the second depth of the second grooves is smaller than the first depth of the first grooves;
forming a second oxidation isolation layer in the processing surface and the second groove to enable the inner wall of the second groove to be subjected to insulation processing; arranging a grid in the second groove in a deposition filling mode;
forming an active layer under the processing surface of the drain electrode epitaxial layer in an energy injection mode, wherein the thickness and the depth of the active layer are within a range which can be penetrated by the second depth of the second groove;
forming an inner dielectric layer on the active layer and the grid electrode in a deposition covering mode, so that the grid electrode is of an embedded structure;
etching the inner dielectric layer to form a third groove aligned with the first groove, wherein the inner wall of the third groove is not subjected to insulation treatment, the width and the depth of the third groove are sufficient to directly expose the edge of the active layer from the side and expose the top of the source electrode extended inverted fin from the bottom;
forming a barrier layer at the bottom of the third trench, wherein the barrier layer covers the drain epitaxial layer at the bottom exposed region of the third trench, and a Schottky barrier is formed in the barrier layer;
forming a source layer in the third trench to conduct the source extension inverted fin, wherein the inversion layer of the active layer is injected in the thickness direction to define the channel length of the field effect transistor;
wherein the third trench extends through the active layer, the barrier layer being located at a bottom corner of the third trench;
the step of forming the barrier layer includes: forming a lightly doped region in the region of the drain electrode epitaxial layer between the protruding part of the first oxidation isolation layer and the active layer in an ion implantation mode; and then depositing a barrier metal layer on the top of the lightly doped region in a deposition mode, and forming the Schottky barrier at a contact region with the lightly doped region after annealing the barrier metal layer.
8. The method of claim 7, wherein said step of forming a field effect transistor structure comprises,
after the step of providing the drain substrate, further comprising: forming a shielding grid bottom floating inverted pole type column bottom junction at the part, corresponding to the bottom of the first groove, of the drain electrode epitaxial layer in an ion implantation mode; specifically, the drain epitaxial layer is a conductive semiconductor wafer;
in the step of forming the first oxidation isolation layer, it includes: forming the first oxidation isolation layer in a thermal oxidation or precipitation mode; forming a side wall protection layer in the first groove; anisotropically etching the side wall protection layer to form an opening at the bottom of the first groove; then forming an oxidation isolation stacking block in the opening of the side wall protection layer; selectively etching and removing the side wall protection layer to expose the first oxidation isolation layer, wherein the thickness of the first oxidation isolation layer and the oxidation isolation superposition block at the bottom of the inner wall is larger than that of the first oxidation isolation layer at the side part of the inner wall; specifically, the first oxide isolation layer is made of silicon oxide, and the sidewall protection layer is made of silicon nitride;
in the step of arranging the source extension inverted fin, a part removing method of the source extension inverted fin and the first oxidation isolation layer on the processing surface comprises chemical mechanical polishing or/and back etching; the material of the source electrode extension inverted fin comprises conductive polysilicon;
in the step of forming the second trench, the preceding steps included are: forming a mask layer on the processing surface to cover the processing surface and the top of the source electrode extension inverted fin; after the second groove is formed, forming a gate-lower floating inverted-pole type junction on the drain electrode epitaxial layer at a position corresponding to the bottom of the second groove in an ion implantation mode;
in the step of forming the second oxidation isolation layer, the second oxidation isolation layer is specifically a gate oxide layer, and the gate oxide layer is formed on the inner wall of the second trench and the processing surface in a thermal oxidation or thermal oxidation plus deposition mode;
in the step of arranging the grid electrode, the method for removing the part of the grid electrode on the processing surface comprises chemical mechanical polishing or/and back etching; the grid electrode comprises conductive polysilicon containing doped ions;
in the step of forming the active layer, the active layer is formed by internalization of the treated surface of the drain epitaxial layer; the active layer comprises a channel layer positioned at the bottom, a current balance layer positioned on the channel layer and a source electrode field layer positioned on the current balance layer;
in the step of forming the third trench, the third trench is of an enlarged slot structure, the inner wall of the third trench keeps a gap with the inner wall of the second trench, the width of the third trench is greater than that of the first trench, and the depth of the third trench is greater than the sum of the thicknesses of the active layer and the inner dielectric layer; when the third groove is formed, the top of the first oxidation isolation layer protrudes out of the bottom of the third groove;
forming a barrier layer in a deposition mode after forming a Schottky barrier, wherein the barrier layer covers the inner dielectric layer, the active layer, the barrier metal layer and the protruding parts of the first oxidation isolation layer;
in the step of forming the source layer, the source layer is made of metal; after the step of forming the source electrode layer, annealing the source electrode layer, and performing back thinning and back metallization on the back surface of the drain electrode substrate.
9. The method of claim 8, wherein a sacrificial gate oxide layer is formed on an inner wall of the second trench before the gate oxide layer is formed, and then the sacrificial gate oxide layer is removed and the drain epitaxial layer is cleaned.
10. A semiconductor chip apparatus, comprising: a field effect transistor structure according to any of claims 1-6, comprising: the semiconductor device comprises a drain electrode epitaxial layer, a source electrode layer, a barrier layer and a source electrode extension inverted fin and a grid electrode, wherein the drain electrode epitaxial layer is positioned below a processing surface, the source electrode layer is positioned on the processing surface, the barrier layer is positioned between a first oxidation isolation layer and an active layer, and the source electrode extension inverted fin and the grid electrode are embedded in the drain electrode epitaxial layer; the grid electrode is arranged between the source electrode extended inverted fins, and symmetrical channels which are connected in parallel from the source electrode layer to the inside of the drain electrode epitaxial layer are formed on two sides of the grid electrode; symmetrical domain resistors connected in parallel from the source electrode layer to the drain electrode epitaxial layer are further formed above the channels on the two sides of the grid electrode; the drain electrode epitaxial layer forms a floating-under-gate inverted-pole junction at the bottom part corresponding to the grid electrode; and the drain electrode epitaxial layer forms a shield grid bottom floating inverted pole type column bottom junction at the position corresponding to the bottom of the source electrode extension inverted fin.
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| CN116632041B (en) * | 2023-07-24 | 2023-09-22 | 苏州华太电子技术股份有限公司 | Shielded gate trench field effect transistor structure and manufacturing method thereof |
| CN117238969A (en) * | 2023-11-13 | 2023-12-15 | 深圳基本半导体有限公司 | Silicon carbide MOSFET device and preparation method and application thereof |
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