CN117393615B - TMBS semiconductor device structure and manufacturing method thereof - Google Patents
TMBS semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN117393615B CN117393615B CN202311683182.2A CN202311683182A CN117393615B CN 117393615 B CN117393615 B CN 117393615B CN 202311683182 A CN202311683182 A CN 202311683182A CN 117393615 B CN117393615 B CN 117393615B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 15
- 238000010168 coupling process Methods 0.000 abstract description 15
- 238000005859 coupling reaction Methods 0.000 abstract description 15
- 238000013461 design Methods 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 5
- 230000001808 coupling effect Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 150000003384 small molecules Chemical class 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a TMBS semiconductor device structure and a manufacturing method thereof, wherein the semiconductor device structure comprises a substrate, an epitaxial layer and a groove; the grooves are arranged in a two-dimensional cored grid-shaped array, each groove comprises a cylindrical groove and a strip-shaped groove, the strip-shaped grooves are arranged along the direction of each grid edge of the two-dimensional cored grid-shaped array, and the cylindrical grooves are arranged in the grid center of the two-dimensional cored grid-shaped array. According to the invention, the cylindrical grooves are introduced to enable the charge coupled cylindrical structure to extend like a transverse direction and a longitudinal direction, so that the charge coupling efficiency is increased by effectively utilizing the cylindrical grooves, the active area grooves are in a two-dimensional grid-shaped layout in the horizontal direction, so that the charge coupling effect distribution is more uniform, on the other hand, the design of the common strip-shaped grooves is changed into the design of the grid center provided with the cylindrical grooves, and under the condition of equal space interval distances, the charge coupling efficiency is ensured, the current flow area is increased, the working efficiency is improved, and the VF value is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a TMBS semiconductor device structure and a manufacturing method thereof.
Background
Currently, in semiconductor device technology, a side oxygen (oxide b) technology of a trench structure is widely used, for example, in devices such as a medium-low voltage MOSFET and a trench schottky (TMBS), and FRD and IGBT devices are also used. Typical mass-produced products such as isolated gate Semiconductor (SGT) devices and the like have a gap between the electric field distribution of a device drift region of a trench-side oxygen (oxide bypass OB) MOSFET and a Super Junction structure, and thus have a design concept of a gradient-side oxygen (Graded oxide bypassed GOB) structure.
In the prior art, there is a process for manufacturing a step-shaped trench semiconductor device, as shown in fig. 1A to 1H, and the conventional manufacturing process of the step-shaped trench semiconductor device includes the following steps:
preparing a substrate 1, forming an epitaxial layer 2 on the substrate 1, and forming a hard mask layer 3 on the epitaxial layer 2, as shown in fig. 1A;
etching the epitaxial layer 2 and the hard mask layer 3 to form a trench 4, as shown in fig. 1B;
removing the hard mask layer 3 as shown in fig. 1C;
forming an oxide layer 5 on the surface of the epitaxial layer 2 and the side walls and bottom of the trench 4 by thermal oxidation or CVD process as shown in fig. 1D, and depositing polysilicon 6 to fill the trench 4 as shown in fig. 1E;
performing surface etching to remove the oxide layer 5 and the redundant polysilicon 6 on the surface of the epitaxial layer 2, as shown in fig. 1F;
a barrier layer 8 is disposed on the upper surface of the epitaxial layer 2 in the termination region, a schottky barrier layer 10 is disposed on the upper surface of the epitaxial layer in the active region, and a metal layer 9 is disposed on the schottky barrier layer 10, thereby forming a TMBS device, as shown in fig. 1G.
One conventional layout of trenches in the horizontal direction in the prior art is shown in fig. 1H, because all trenches are elongated in one direction, the current flow area is relatively low, and there is room for further optimization.
Disclosure of Invention
Accordingly, the present invention is directed to a TMBS semiconductor device structure and a method for fabricating the same, in which the active region trenches are arranged in a two-dimensional grid shape in a horizontal direction, so that the distribution of charge coupling effects is more uniform, and on the other hand, the design of the common stripe trench is changed into the design of arranging a column trench in the center of the grid, and under the condition of equal space interval distances, the charge coupling efficiency is ensured, and meanwhile, the current flow area is increased, thereby improving the working efficiency therebetween, and reducing the VF value.
In order to achieve the above purpose, the invention provides a semiconductor device structure of TMBS, which comprises a substrate, an epitaxial layer arranged on the substrate and a groove arranged on the upper surface of the epitaxial layer, wherein the inner wall of the groove is provided with a stepped field dielectric layer, and a polysilicon region is filled in the groove:
the upper surface of the epitaxial layer is provided with a Schottky barrier layer, and a metal layer is arranged on the Schottky barrier layer;
the grooves are arranged in a two-dimensional cored grid-shaped array, each groove comprises a cylindrical groove and a strip-shaped groove, the strip-shaped grooves are arranged along the direction of each grid edge of the two-dimensional cored grid-shaped array, and the cylindrical grooves are arranged in the grid center of the two-dimensional cored grid-shaped array. The charge coupled columnar structure is simultaneously delayed like a transverse direction and a longitudinal direction in terms of layout through the introduction of the columnar grooves. The effective use of the cylindrical grooves increases the efficiency of the telephone coupling.
Preferably, the elongated grooves are not communicated at the grid edge intersection points, so that the area of the grooves in the horizontal direction is further reduced.
Preferably, the distance from the edge of the cylindrical groove to the adjacent strip-shaped groove is D1, the distance from the intersection point of the grid edge to the adjacent strip-shaped groove is D2/2, and D2 is less than or equal to D1. The width of the elongated grooves is denoted as CD, the width of CD and the widths of D1 and D2, and can be defined by those skilled in the art according to the design requirements of the process device.
Preferably, the two-dimensional grid with the heart is a regular polygon grid.
Preferably, the regular polygon mesh includes a square mesh or a regular hexagon mesh. The grid can also be formed by splicing various regular polygons, wherein at least one part of regular polygon grid is of a cored structure with a columnar groove arranged at the center.
In another aspect, the present invention provides a method for manufacturing the semiconductor device structure, including the following steps:
preparing a substrate, forming an epitaxial layer on the substrate, forming a groove on the epitaxial layer, wherein the groove comprises an active area groove and a terminal area groove, the active area groove is arranged in a two-dimensional grid array with a center, and a first field dielectric layer is arranged on the surface of the epitaxial layer and on the inner wall of the groove;
a photoresist layer is arranged on the inner wall of the groove and the surface of the first field dielectric layer, the photoresist layer is a positive photoresist material layer, and maskless exposure is carried out on the photoresist layer;
dry etching is carried out on the upper surface of the epitaxial layer and the first field dielectric layer at the upper part of the inner wall of the groove;
removing the residual photoresist layer;
a second field dielectric layer is arranged on the upper surface of the epitaxial layer and the inner wall of the groove;
setting a polysilicon region in the trench;
etching the second field dielectric layer on the upper surface of the epitaxial layer;
and a barrier layer is arranged on the upper surface of the epitaxial layer of the terminal area, a Schottky barrier layer is arranged on the upper surface of the epitaxial layer of the active area, and a metal layer is arranged on the Schottky barrier layer.
The beneficial effects of the invention are as follows:
(1) According to the invention, the active region grooves are in a two-dimensional grid-shaped layout in the horizontal direction, so that the charge coupling effect distribution is more uniform, on the other hand, the design of the common strip-shaped grooves is changed into the design of the cylindrical grooves arranged in the center of the grid, and the charge coupling cylindrical structure is extended like a transverse and longitudinal structure simultaneously through the introduction of the cylindrical grooves, so that the efficiency of telephone coupling is increased by effectively utilizing the cylindrical grooves. Under the condition that the space interval distances are equal, the charge coupling efficiency is ensured, and meanwhile, the current flow area is increased, so that the working efficiency is improved, and the VF value is reduced (namely the conduction loss is reduced);
(2) According to the invention, the manufacturing process is adjusted and optimized, the charge coupling efficiency is improved by adopting the thickness of the field oxide layer which is changed (along the vertical direction), the same withstand voltage can be realized by adopting the EPI with lower resistivity, and compared with the traditional BV/VF improvement, the device performance is improved; the process for forming the field oxide layer is changed, the flow is simplified, the thinner second field oxide layer can be realized by using a CVD or thermal growth mode, the uniformity is better, and the device performance is further optimized.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIGS. 1A-1H are schematic diagrams of the prior art;
FIGS. 2A-2H are schematic flow diagrams of embodiments of the present invention;
fig. 3A to 3D are schematic structural diagrams of an active region trench according to an embodiment of the present invention;
wherein:
1. a substrate; 2. an epitaxial layer; 3. a hard mask layer; 4. a groove; 41. an active region trench; 411. a cylindrical trench; 412. an elongated groove; 42. a termination region trench; 5. an oxide layer; 51. a first field dielectric layer; 52. a second field dielectric layer; a 6/61 polysilicon region; 7. a photoresist layer; 8. a barrier layer; 9. a metal layer; 10. a schottky barrier layer.
Detailed Description
The invention aims at providing a TMBS semiconductor device structure and a manufacturing method thereof, wherein the active region grooves are in two-dimensional grid-shaped layout in the horizontal direction, so that the charge coupling effect distribution is more uniform, on the other hand, the design of a common strip-shaped groove is changed into the design of a cylindrical groove arranged in the center of a grid, and the charge coupling cylindrical structure extends like a transverse and longitudinal structure simultaneously through the introduction of the cylindrical groove, so that the efficiency of telephone coupling is improved by effectively utilizing the cylindrical groove. Under the condition that the space interval distances are equal, the charge coupling efficiency is ensured, and meanwhile, the current flow area is increased, so that the working efficiency is improved, and the VF value is reduced.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Fig. 2A to 2H illustrate a semiconductor device structure of a TMBS and a method for manufacturing the same according to the present embodiment, including the following steps:
s1: as shown in fig. 2A, a substrate 1 is prepared, an epitaxial layer 2 is formed on the substrate 1, a trench 4 is formed on the epitaxial layer 2, the trench 4 includes an active region trench 41 and a termination region trench 42 (specific steps are described in text corresponding to fig. 1A to 1C in the background art part), and a first field dielectric layer 51 is grown or deposited on the surface of the epitaxial layer 2 and the inner wall of the trench 4; in this embodiment, the active region trenches 41 are arranged in a two-dimensional cored grid array.
S2: as shown in fig. 2B, a photoresist layer 7 is disposed on the inner wall of the trench 4 and the surface of the first field dielectric layer 51, the photoresist layer 7 is a positive photoresist material layer, and maskless exposure is performed on the photoresist layer 7, so that the photoresist layer 7 on the surface of the epitaxial layer 2 is dissociated into small molecules by exposure, and the photoresist layer 7 in the trench 4 is reserved because the exposure cannot be fully performed, that is, at least the photoresist layer below a reserved depth is guaranteed not to be dissociated into small molecules, and the reserved depth corresponds to the step position of the finally formed stepped field dielectric layer; after exposure, the photoresist layer dissociated into small molecules is removed by development.
S3: as shown in fig. 2C, the first field dielectric layer 51 on the upper surface of the epitaxial layer 2 and on the upper portion of the inner wall of the trench 4 is dry etched, and a portion of the first field dielectric layer 51 (including a portion of the surface of the epitaxial layer 2 and a portion of the upper side wall in the trench 4) above the remaining depth is removed.
S4: as shown in fig. 2D, the remaining photoresist layer 7 is removed.
S5: as shown in fig. 2E, a second field dielectric layer 52 is grown or deposited on the upper surface of the epitaxial layer 2 and the inner wall of the trench 4, and the first field dielectric layer 51 is not removed at the portion below the retention depth, so that the thickness of the field dielectric layer below the retention depth is greater than that at the portion above the retention depth, thereby forming a stepped structure.
S6: as shown in fig. 2F, a polysilicon region 61 is provided within the trench 4.
S7: as shown in fig. 2G, the second field dielectric layer 52 and the excess polysilicon 6 on the surface of the epitaxial layer 2 are etched;
s8: as shown in fig. 2H, a barrier layer 8 is disposed on the upper surface of the epitaxial layer 2 in the termination region, a schottky barrier layer 10 is disposed on the upper surface of the epitaxial layer in the active region, and a metal layer 9 is disposed on the schottky barrier layer 10, and at this time, the semiconductor device structure of the TMBS disclosed in this embodiment is formed, and based on this structure, other partial structures of the active region may be further disposed by those skilled in the art to form a desired semiconductor device.
As shown in fig. 3A to 3D, fig. 3A to 3D are top views, and the active region trenches 41 are arranged in a two-dimensional grid array with centers, and the grid array may be, for example, a square grid, a regular hexagon grid, or other regular polygon spliced grids. The active region trench 41 includes a column trench 411 and an elongated trench 412, the elongated trench 412 being disposed along a direction of each grid side of the two-dimensional cored grid-shaped array, the column trench 411 being disposed at a grid center of the two-dimensional cored grid-shaped array.
In a preferred embodiment, as shown in fig. 3A and 3C, the elongated trenches 412 are connected at the grid edge intersections, the distance from the edge of the pillar trench 411 to the adjacent elongated trench 412 is D1, the width of the elongated trench 412 is denoted as CD, the width of the CD and the width of D1, and those skilled in the art can define the device design requirements. In this example, d1=1.5 μm and cd=0.5 μm, and the smaller the CD width is, the better the process requirements are satisfied.
In a preferred embodiment, as shown in fig. 3B and 3D, the elongated grooves 412 are not connected at the intersections of the grid edges, the distance from the edges of the column-shaped grooves 411 to the adjacent elongated grooves 412 is D1, the distance from the intersections of the grid edges to the adjacent elongated grooves 412 is D2/2, and D2 is equal to or less than D1; preferably, the width of the elongated grooves 412 is denoted as CD, the width of CD and the widths of D1, D2, in this embodiment d2=d1=1.5 μm, and cd=0.5 μm, which can be defined by those skilled in the art according to the process device design requirements. Preferably, the smaller the CD width is, the better the process requirements are met. Compared with the case of fig. 3A and 3C, this embodiment further sets the grid edge intersections as current flow areas, thereby further increasing the current flow area; because the charge coupling efficiency in the epitaxial layer decays with the increase of the distance between the position of the epitaxial layer and the groove during reverse blocking, when d2=d1, the charge coupling efficiency at the grid edge intersection point is equivalent to the area in the grid, and the optimal current flow area can be realized while ensuring the charge coupling efficiency.
In the case of other regular polygon spliced grids, those skilled in the art can also refer to the modes of fig. 3A to 3D, and since the middle cylindrical trench 411 is provided in the cored grid, the size (measured by the distance from the center of the grid to the grid edge) of the grid can be doubled while ensuring the charge coupling efficiency compared with the grid without the core, so that the trench area occupation ratio is further reduced, and the effective current flow area is improved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. The semiconductor device structure of TMBS is characterized by comprising a substrate, an epitaxial layer arranged on the substrate and a groove formed in the upper surface of the epitaxial layer, wherein a stepped field dielectric layer is arranged on the inner wall of the groove, and a polysilicon region is filled in the groove:
the upper surface of the epitaxial layer is provided with a Schottky barrier layer, and a metal layer is arranged on the Schottky barrier layer;
the grooves are arranged in a two-dimensional cored grid-shaped array, the grooves comprise cylindrical grooves and strip-shaped grooves, the strip-shaped grooves are arranged along the direction of each grid edge of the two-dimensional cored grid-shaped array, and the cylindrical grooves are arranged in the grid center of the two-dimensional cored grid-shaped array;
the distance from the edge of the cylindrical groove to the adjacent strip-shaped groove is D1, and the distance from the intersection point of the grid edge to the adjacent strip-shaped groove is D2/2, wherein D2 is less than or equal to D1.
2. The semiconductor device structure of claim 1, wherein the elongated trenches do not communicate at grid edge intersections.
3. The semiconductor device structure of claim 1, wherein the two-dimensional cored mesh is a regular polygon mesh.
4. The semiconductor device structure of claim 3, wherein the regular polygon mesh comprises a square mesh or a regular hexagon mesh.
5. The method for manufacturing the semiconductor device structure of the TMBS according to any one of claims 1 to 4, comprising the steps of:
preparing a substrate, forming an epitaxial layer on the substrate, forming a groove on the epitaxial layer, wherein the groove comprises an active area groove and a terminal area groove, the active area groove is arranged in a two-dimensional grid array with a center, and a first field dielectric layer is arranged on the surface of the epitaxial layer and on the inner wall of the groove;
a photoresist layer is arranged on the inner wall of the groove and the surface of the first field dielectric layer, the photoresist layer is a positive photoresist material layer, and maskless exposure is carried out on the photoresist layer;
dry etching is carried out on the upper surface of the epitaxial layer and the first field dielectric layer at the upper part of the inner wall of the groove;
removing the residual photoresist layer;
a second field dielectric layer is arranged on the upper surface of the epitaxial layer and the inner wall of the groove;
setting a polysilicon region in the trench;
etching the second field dielectric layer on the upper surface of the epitaxial layer;
and a barrier layer is arranged on the upper surface of the epitaxial layer of the terminal area, a Schottky barrier layer is arranged on the upper surface of the epitaxial layer of the active area, and a metal layer is arranged on the Schottky barrier layer.
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| CN202311683182.2A CN117393615B (en) | 2023-12-09 | 2023-12-09 | TMBS semiconductor device structure and manufacturing method thereof |
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|---|---|---|---|---|
| JPH10284631A (en) * | 1997-04-03 | 1998-10-23 | Shinko Electric Ind Co Ltd | Semiconductor package |
| JP2017123441A (en) * | 2016-01-08 | 2017-07-13 | 三菱電機株式会社 | Method of manufacturing semiconductor laser element |
| CN107958936A (en) * | 2016-10-14 | 2018-04-24 | 现代自动车株式会社 | Semiconductor devices and the method being used for producing the semiconductor devices |
| CN115224127A (en) * | 2021-04-16 | 2022-10-21 | 深圳真茂佳半导体有限公司 | Field effect transistor structure, manufacturing method thereof and chip device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10214151B4 (en) * | 2002-03-28 | 2007-04-05 | Infineon Technologies Ag | Semiconductor device with increased breakdown voltage in the edge region |
| TWI521693B (en) * | 2012-11-27 | 2016-02-11 | 財團法人工業技術研究院 | Schottky barrier diode and fabricating method thereof |
| DE102016108934B4 (en) * | 2016-05-13 | 2021-12-09 | Infineon Technologies Austria Ag | Semiconductor devices and methods of forming semiconductor devices |
| WO2018078776A1 (en) * | 2016-10-27 | 2018-05-03 | サンケン電気株式会社 | Semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10284631A (en) * | 1997-04-03 | 1998-10-23 | Shinko Electric Ind Co Ltd | Semiconductor package |
| JP2017123441A (en) * | 2016-01-08 | 2017-07-13 | 三菱電機株式会社 | Method of manufacturing semiconductor laser element |
| CN107958936A (en) * | 2016-10-14 | 2018-04-24 | 现代自动车株式会社 | Semiconductor devices and the method being used for producing the semiconductor devices |
| CN115224127A (en) * | 2021-04-16 | 2022-10-21 | 深圳真茂佳半导体有限公司 | Field effect transistor structure, manufacturing method thereof and chip device |
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