CN111129108A - Transistor terminal structure and manufacturing method thereof - Google Patents
Transistor terminal structure and manufacturing method thereof Download PDFInfo
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- CN111129108A CN111129108A CN201911140881.6A CN201911140881A CN111129108A CN 111129108 A CN111129108 A CN 111129108A CN 201911140881 A CN201911140881 A CN 201911140881A CN 111129108 A CN111129108 A CN 111129108A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention relates to a transistor terminal structure and a manufacturing method thereof, wherein the terminal structure annularly surrounds an active area of a transistor on a plane, the terminal structure comprises a substrate, a stop ring on the substrate and a plurality of voltage division rings on the substrate, and each voltage division ring is arranged between the stop ring and a main node at the boundary of the active area and the terminal structure; the semiconductor structure is characterized by further comprising a plurality of groove polycrystalline silicon field plates, wherein the groove polycrystalline silicon field plates are distributed in the substrate between the voltage dividing ring closest to the main node and the cut-off ring, and no more than one groove polycrystalline silicon field plate is arranged between every two adjacent voltage dividing rings. The invention replaces the traditional horizontal polysilicon field plate scheme with the trench polysilicon field plate, and can reduce the spacing of the voltage division ring on the premise of ensuring the same voltage resistance as the traditional scheme, thereby shortening the overall size of the terminal structure and embodying better terminal cost performance and economy.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a transistor terminal structure and a manufacturing method of the transistor terminal structure.
Background
The high-reliability terminal is generally a composite terminal technology of a floating space compression ring matched with a field plate, so that the terminal reliability of the transistor is effectively improved, the space between floating rings is wider for placing the poly field plate and improving the voltage-resistant level of each floating ring, and although the normal-temperature and high-temperature voltage-resistant reliability is good, the whole terminal structure is longer, the economic cheapness is poor, the market competitiveness is insufficient, and the marketization and the popularization of high-quality products are seriously restricted.
Disclosure of Invention
In view of the above, it is desirable to provide a transistor termination structure with a smaller area and a method for fabricating the same.
A transistor terminal structure annularly surrounds an active area of a transistor on a plane, and comprises a substrate, a stop ring on the substrate and a plurality of partial pressure rings on the substrate, wherein each partial pressure ring is arranged between the stop ring and a main junction at the boundary of the active area and the terminal structure; the semiconductor structure is characterized by further comprising a plurality of groove polycrystalline silicon field plates, wherein the groove polycrystalline silicon field plates are distributed in the substrate between the voltage dividing ring closest to the main node and the cut-off ring, and no more than one groove polycrystalline silicon field plate is arranged between every two adjacent voltage dividing rings.
In one embodiment, at least a part of the trench polysilicon field plate is arranged at the midpoint of two adjacent voltage dividing rings.
In one embodiment, there is only one trench polysilicon field plate between each of the adjacent voltage divider rings, and a first field plate is disposed between the first voltage divider ring and the stop ring, the first voltage divider ring is the voltage divider ring with the terminal structure closest to the stop ring, and the first field plate is a trench polysilicon field plate.
In one embodiment, the distance between the first field plate and the first voltage dividing ring is less than half of the cutoff distance and greater than the distance between a trench polysilicon field plate nearest to the first field plate and a voltage dividing ring nearest to the first voltage dividing ring.
In one embodiment, a trench polysilicon field plate is not arranged between a second voltage division ring and the main node, and the second voltage division ring is the voltage division ring closest to the main node; the transistor terminal structure further comprises a first metal field plate arranged on the substrate and extending from the main junction to the second voltage division ring.
In one embodiment, the length of the first metal field plate is greater than or equal to 1 micron and less than or equal to the distance between the main junction and the second voltage division ring.
In one embodiment, the semiconductor device further comprises a second metal field plate extending from the cutoff ring to the first voltage divider ring and electrically connected to the cutoff ring, and the length of the second metal field plate is less than half of the cutoff interval.
In one embodiment, the cut-off rings are of opposite conductivity type to each of the voltage divider rings.
According to the transistor terminal structure, the traditional horizontal polycrystalline silicon field plate scheme is replaced by the groove polycrystalline silicon field plate, the voltage division ring distance can be reduced on the premise that the same voltage resistance as the traditional scheme is guaranteed, so that the whole size of the terminal structure can be shortened, and better terminal cost performance and economy are reflected.
A method of fabricating a transistor termination structure which surrounds an active region of a transistor in a ring shape in a plane, the method comprising: providing a substrate, wherein a first mask layer is formed on the substrate, and a voltage division ring doping window is formed in the first mask layer; injecting second conductive type impurities through the grading ring doping window to form a plurality of grading rings on the substrate; forming a hard mask layer on the substrate, wherein the hard mask layer is provided with a groove window, and the hard mask layer and the groove window are positioned in the active region and the terminal structure; etching a groove below the groove window, wherein the groove comprises an active area groove and a plurality of terminal grooves, and each terminal groove is positioned between adjacent voltage division rings and on the outer side of the voltage division ring farthest from the active area; forming gate dielectric layers on the inner surfaces of the active region grooves and the inner surfaces of the terminal grooves; depositing polycrystalline silicon and reversely etching to form a trench polycrystalline silicon field plate in each terminal trench, wherein no more than one trench polycrystalline silicon field plate is arranged between every two adjacent voltage dividing rings; forming a second mask layer on the substrate, wherein the second mask layer is provided with a stop ring injection window; and implanting first conductive type impurities through the stop ring implantation window to form a stop ring on the substrate, wherein the first conductive type and the second conductive type are opposite conductive types.
In one embodiment, the step of etching the trench below the trench window is a dry etching process, and before the step of forming the gate dielectric layer on the inner surface of the active region trench and the inner surface of each terminal trench, the method further includes a step of thermally growing a sacrificial oxide layer on the inner surface of the trench and removing the sacrificial oxide layer with a hydrofluoric acid solution.
According to the manufacturing method of the transistor terminal structure, the groove polycrystalline silicon field plate is manufactured synchronously with the groove of the active area, so that extra photoetching plates and working procedures are not needed for manufacturing the groove polycrystalline silicon field plate, and the manufacturing cost can be saved.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.
FIG. 1 is a top view of an active region of a transistor and a termination structure;
FIG. 2 is a schematic cross-sectional view of a transistor termination structure in one embodiment;
FIG. 3 is a flow chart of a method for fabricating a transistor termination structure in one embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
Fig. 1 is a top view of an active region 200 of a transistor and a termination structure 300, the termination structure 300 annularly surrounding the active region 200 of the transistor in plan view. The terminal structure 300 has the functions of ensuring the reverse breakdown voltage of the device and improving the reverse breakdown reliability.
Referring collectively to fig. 2, the termination structure 300 includes a substrate, a cutoff ring 26 on the substrate, and a plurality of voltage divider rings 24 on the substrate. In the embodiment shown in fig. 2, the substrate includes a base 10 and an epitaxial layer 12 on the base 10, each of the grading rings 24 is extended downward from the upper surface of the epitaxial layer 12 by a certain depth, and each of the grading rings 24 is disposed between a stopper ring 26 and a main node 22 (the main node 22 is located at the boundary between the active region 200 and the terminal structure 300). The termination structure 300 also includes a plurality of trench polysilicon field plates 42 distributed in the substrate between the grading ring 24b (the grading ring 24b being the grading ring closest to the main ring 22) and the stop ring 26. The trench polysilicon field plates 42 are structures filled with polysilicon in the trenches, and in the embodiment shown in fig. 2, each trench polysilicon field plate 42 extends downward from the upper surface of the epitaxial layer 12 by a certain depth, and no more than one trench polysilicon field plate 42 is provided between every two adjacent voltage dividing rings 24. In one embodiment, the substrate 10 is a silicon wafer, the substrate 10 and the epitaxial layer 12 are both of the first conductivity type, and each of the voltage divider rings 24 mainly functions to raise the back-pressure level of the second conductivity type impurity to the curved junction of the first conductivity type impurity in the device to the planar junction state of the epitaxial layer 12 doped with the first conductivity type.
In one embodiment, the shunt ring 24 is of the opposite conductivity type to the cutoff ring 26, the cutoff ring 26 having a first conductivity type, and the shunt ring 24 having a second conductivity type. In the present embodiment, the first conductivity type is N-type, and the second conductivity type is P-type; in another embodiment, the first conductivity type may be P-type and the second conductivity type may be N-type.
According to the terminal structure of the transistor, the traditional horizontal polycrystalline silicon field plate scheme is replaced by the groove polycrystalline silicon field plate, the groove polycrystalline silicon field plate introduces an electric field peak into the substrate/epitaxial layer, the back pressure capability (reverse breakdown voltage) is guaranteed, the voltage withstanding effect similar to that of the horizontal polycrystalline silicon field plate can be achieved, the voltage dividing ring distance can be reduced on the premise that the same voltage withstanding effect as that of the traditional scheme is guaranteed, the whole size of the terminal structure can be shortened, and better terminal cost performance and economy are embodied. The traditional scheme is limited by the fact that the terminal is long in size, low in cost performance and large in whole chip size, and is not beneficial to upgrading and updating of products and the national concept of energy conservation and emission reduction. In order to embody the high reliability, the low price and the high cost performance of a terminal structure without increasing other cost, a horizontal polycrystalline silicon field plate is replaced by a vertically arranged groove polycrystalline silicon field plate, the application effect of the field plate is not changed, the space between voltage division rings can be properly shortened after the polycrystalline silicon field plate is vertically arranged, the overall size length of a terminal can be reduced by 20-50%, and the terminal structure has strong terminal economy.
In one embodiment, the trench polysilicon field plate 42 includes polysilicon and a gate dielectric layer between the polysilicon and the walls/bottom of the trench. In one embodiment, the gate dielectric layer is made of silicon oxide, such as silicon dioxide. In one embodiment, the gate dielectric layer has a thickness of
In one embodiment, the polysilicon in the trench polysilicon field plate 42 is doped polysilicon. In one embodiment, the depth of the trench polysilicon field plate 42 is 0.5-50 μm, the width of the field plate (i.e. the length in the left-right direction in FIG. 2) is 0.1-2.0 μm, and the resistivity of the doped polysilicon is 1-100 Ω/□. In one embodiment, the doped polysilicon is doped with the first conductivity type.
In the embodiment shown in fig. 2, a screen oxide layer 30 is further disposed on the upper surface of the epitaxial layer 12.
In the embodiment shown in fig. 2, a trench polysilicon field plate 42 is disposed at the midpoint of each two adjacent voltage divider rings 24, and a trench polysilicon field plate 42, which is named as a first field plate, is also disposed between the voltage divider ring 24a (the voltage divider ring 24a is the closest voltage divider ring to the stop ring 26) and the stop ring 26.
In one embodiment, the first field plate is spaced from the first voltage divider ring 24a by less than one-half of the cutoff spacing and by more than the spacing between a trench polysilicon field plate 42 nearest the first field plate and the voltage divider ring 24c (voltage divider ring 24c is the voltage divider ring nearest the first voltage divider ring 24 a). The cutoff distance indicates the distance between the voltage dividing ring 24a and the cutoff ring 26.
In the embodiment shown in fig. 2, instead of providing a trench polysilicon field plate 42 between the second divider ring 24b (the second divider ring 24b being the closest divider ring to the main ring 22) and the main ring 22, a first metal field plate 44a is provided extending from above the main ring 22 towards the second divider ring 24b, the first metal field plate 44a being electrically connected to the main ring 22. In one embodiment, the second voltage divider ring 24b is spaced from the main junction 22 by a smaller distance than the ring spacing of all other adjacent voltage divider rings 24, i.e., the second voltage divider ring 24b is spaced from the main junction 22 by a shorter distance, so the arrangement of the first metal field plate 44a in a parallel field plate configuration will better improve the peak electric field at the main junction 22.
In one embodiment, the length of the first metal field plate 44a is greater than or equal to 1 micron and less than or equal to the spacing between the main junction 22 and the second voltage divider ring 24 b. It will be appreciated that a first metal field plate 44a that is too short will be ineffective, and that it will be ineffective if too long, such as extending to the second divider ring 24 b.
In the embodiment shown in fig. 2, the termination structure of the transistor further includes a second metal field plate 44b, and the second metal field plate 44b is electrically connected to the stop ring 26 and extends from the stop ring 26 to the first voltage divider ring 24a, so as to achieve the effect of equipotential stop. In one embodiment, the length of the second metal field plate 44b is less than one-half of the cutoff spacing.
In one embodiment, the first metal field plate 44a and the second metal field plate 44b are 1-10 μm thick.
In one embodiment, the ring pitch of each of the voltage divider rings 24 gradually increases at a step from the inside to the outside (i.e., from the main structure 22 toward the cut-off ring 26). The variation value of the ring spacing can be obtained by certain formula or simulation calculation.
In one embodiment, the junction depth of each grading ring 24 is greater than or equal to 1 μm and the width is greater than or equal to 1 μm; wherein the width refers to the length in the left-right direction in fig. 2.
In one embodiment, the stop ring 26 has a junction depth of 0.2 μm or more and a width of 0.2 μm or more; wherein the width refers to the length in the left-right direction in fig. 2.
The present application further provides a method for manufacturing a transistor termination structure, which can be used to manufacture the transistor termination structure according to any of the above embodiments. FIG. 3 is a flow diagram of a method for fabricating a transistor termination structure in one embodiment, including:
s310, providing a substrate.
A first mask layer is formed on the substrate, and a voltage division ring doping window is formed in the first mask layer. In one embodiment, the substrate is a semiconductor epitaxial silicon wafer of a first conductivity type having two opposing major surfaces and having a first silicon oxide layer, i.e., a screen oxide layer, formed on the first major surface. In one embodiment, the screen oxide layer is thermally grown to a thickness of 0.01 μm to 5 μm. The embodiment selectively etches the first silicon oxide layer by photoetching to define a voltage division ring doping window. In one embodiment, the step of high temperature thermal growth to form the screen oxide layer is a separate process operation. In one embodiment, the lithography of the strap doping windows is formed as a separate lithography process step.
And S320, injecting second conductive type impurities through the grading ring doping windows to form a plurality of grading rings on the substrate.
In the present embodiment, the first conductivity type is N-type, and the second conductivity type is P-type; in another embodiment, the first conductivity type may be P-type and the second conductivity type may be N-type. In this embodiment, after ion implantation, a P + strap with a certain doped junction depth is formed by high-temperature drive-in, the strap is formed in an epitaxial layer on a substrate, and the junction depth of the strap is to be precisely controlled. In one embodiment, step S320 is performedThe second conductivity type impurity is boron B11(11 represents the relative atomic mass), which, prior to implantation,
the implantation dosage of the impurity boron B11 is 1e 12-8 e16 atomicity/cm2The injection energy is 60-150 kev, the diffusion temperature of the high-temperature drive-in trap is 900-1250 ℃, and the diffusion time is 60-450 min. Since the respective voltage dividing rings are manufactured together, the junction depths of the respective voltage dividing rings are uniform. In one embodiment, the ion implantation of step S320 is performed with the photoresist remaining.
S330, forming a hard mask layer with a groove window on the substrate.
In one embodiment, after removing the photoresist layer formed in step S320, a silicon oxide (e.g., silicon dioxide) is deposited by chemical vapor deposition on the first main surface as a hard mask layer, and then a photoresist is coated on the hard mask layer and is developed by photolithography, and then the hard mask layer is etched to form a trench window. To save costs, the trenches of the termination structure and the trenches of the active area may be formed together, so that both the active area and the termination structure are formed with trench windows. In one embodiment, the deposited silicon dioxide is 0.01 μm to 5 μm thick.
S340, etching an active region groove and a plurality of terminal grooves below the groove window.
In an embodiment, after removing the photoresist layer formed in step S330, a hard mask layer with a trench window is used as an etching barrier layer, and trenches with a certain width and depth are etched in the active region and the terminal structure by dry etching. Each terminal groove is positioned between adjacent voltage division rings and on the outer side of the voltage division ring farthest from the active region.
And S350, forming a gate dielectric layer on the inner surface of the active region groove and the inner surface of each terminal groove.
In one embodiment, a gate oxide layer with a certain thickness is thermally grown to be used as a gate dielectric layer. For embodiments in which the trench is dry etched, the trench may be first thermally grown on the inner surface of the trenchAnd growing a sacrificial oxide layer, removing the sacrificial oxide layer by using hydrofluoric acid solution, and then growing a gate oxide layer. The formation of the sacrificial oxide layer can improve the interface state of the inner surface of the trench because the dry etching has large damage to the inner surface of the trench, which can cause the formation of roughness and particles on the surface. In one embodiment, the thickness of the grown sacrificial silicon oxide layer is 0.01-2.0 μm, and the thickness of the gate oxide layer is
And S360, depositing polysilicon and reversely etching to form a trench polysilicon field plate in each terminal trench.
In one embodiment, a doped polysilicon layer is deposited on the first main surface, and the polysilicon layer with the deposited thickness is etched back, so that the excessive polysilicon on the surface of the epitaxial layer except the polysilicon in the groove can be etched cleanly, and a photoetching plate is not needed for etching. And no more than one groove polycrystalline silicon field plate is arranged between every two adjacent voltage division rings. In one embodiment, the polysilicon deposition is a low temperature low pressure chemical reaction deposition process. In one embodiment, an oxide layer is also thermally grown on the upper surface of the doped polysilicon layer to shield the polysilicon in the trench. The oxide layer can shield the trench polysilicon field plate in the epitaxial layer, thereby playing the role of the polysilicon field plate. In one embodiment, polysilicon is also deposited into the active area trenches and an oxide layer is thermally grown thereon; the trench, the gate oxide layer, the polysilicon deposition and the shielding oxidation of the terminal structure are completed together with the active region process steps, and the parameters of the terminal trench, the thickness of the gate oxide layer, the thickness of the polysilicon and the shielding oxidation are all consistent with those of the active region. The width of the trench polysilicon field plate can be increased appropriately according to the requirement of back pressure to ensure the voltage-resistant effect of the terminal.
In one embodiment, the depth of the trench polysilicon field plate is 0.5-50 μm, the width of the field plate is 0.1-2.0 μm, and the resistivity of the doped polysilicon is 1-100 Ω/□. In one embodiment, the resistivity of the trench polysilicon field plate is precisely controlled. In one embodiment, the doped polysilicon is doped with the first conductivity type.
And S370, forming a second mask layer on the substrate, wherein the second mask layer is provided with a stop ring injection window.
In this embodiment, the stop-ring implant window is formed by selective mask lithography.
And S380, implanting first conductive type impurities through the stop ring implantation window to form a stop ring on the substrate.
In one embodiment, the post-implant high temperature push-well forms an effective N + stop-ring formed in the epitaxial layer on the substrate, the junction depth of the stop-ring being precisely controlled. In one embodiment, the high temperature push-trap temperature of the cutoff ring is lower than the high temperature push-trap temperature of the grading ring. In one embodiment, step S370 is completed together with step S380 and the first conductive type impurity doping step of the active region.
In one embodiment, the first conductivity type impurity implanted in step S380 is phosphorus P31(31 denotes relative atomic mass) or arsenic, which, prior to implantation,
the implantation dosage of the impurity phosphorus P31 or arsenic is 1e 14-8 e16 atomicity/cm2The injection energy is 60-150 kev, the diffusion temperature of the high-temperature drive-in trap is 900-1150 ℃, and the diffusion time is 60-300 min.
According to the manufacturing method of the transistor terminal structure, the groove polycrystalline silicon field plate is manufactured synchronously with the groove of the active area, so that extra photoetching plates and working procedures are not needed for manufacturing the groove polycrystalline silicon field plate, and the manufacturing cost can be saved.
In one embodiment, step S380 is followed by:
and forming a dielectric layer on the shielding oxide layer of the first main surface. In one embodiment, a dielectric layer doped with P31 is deposited on the surface of the polycrystalline field plate and the second oxide layer. In one embodiment, the dielectric layer is formed by low temperature low pressure chemical reaction deposition. In one embodiment, the dielectric layer is made of PSG (phosphosilicate glass), and in another embodiment, the dielectric layer is made of BPSG (borophosphosilicate glass). The dielectric layer can isolate each partial pressure ring and the groove polycrystalline field plate, and reliability of the terminal structure is improved. In one embodiment, the dielectric layer is deposited and then subjected to a high temperature reflow process to enhance the compactness and smoothness of the dielectric layer.
And etching the dielectric layer to form a contact hole. And selectively masking and photoetching to etch the contact hole. In one embodiment the contact hole size is ≧ 0.5 μm × 0.5 μm. In one embodiment, the lithography of the contact holes is a separate lithography process step.
A metal field plate is formed. The method comprises the steps of forming a first metal field plate which extends from the main node to the second voltage division ring and is electrically connected with the main node and a second metal field plate which extends from the cut-off ring to the first voltage division ring and is electrically connected with the cut-off ring on the epitaxial layer. The length of the first metal field plate is larger than or equal to 1 micron and smaller than or equal to the distance between the main junction and the second voltage division ring, and the length of the second metal field plate is smaller than one half of the cutoff distance. In one embodiment, the metal field plate is an aluminum layer, and a vacuum physical evaporation deposition process for the aluminum layer can be used. In one embodiment, the lithography of the metal field plate is formed for a separate lithography process step.
And (3) carrying out alloy annealing on the terminal structure at the low temperature of 300-500 ℃ for 10-60 minutes to eliminate the surface state and improve the contact.
In conclusion, the grading ring, the groove polysilicon field plate, the contact hole and the metal field plate in the terminal structure are manufactured by step-by-step photoetching.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A transistor terminal structure annularly surrounds an active area of a transistor on a plane, and comprises a substrate, a stop ring on the substrate and a plurality of partial pressure rings on the substrate, wherein each partial pressure ring is arranged between the stop ring and a main junction at the boundary of the active area and the terminal structure; the semiconductor structure is characterized by further comprising a plurality of groove polycrystalline silicon field plates, wherein the groove polycrystalline silicon field plates are distributed in the substrate between the voltage dividing ring closest to the main node and the cut-off ring, and no more than one groove polycrystalline silicon field plate is arranged between every two adjacent voltage dividing rings.
2. The transistor termination structure of claim 1, wherein at least a portion of the trench polysilicon field plate is disposed at a midpoint between two adjacent voltage divider rings.
3. A transistor termination structure according to claim 1 or 2, wherein there is only one trench polysilicon field plate between each of the adjacent divider rings, and a first field plate is provided between a first divider ring and the stop ring, the first divider ring being the divider ring of the termination structure closest to the stop ring, the first field plate being a trench polysilicon field plate.
4. The transistor termination structure of claim 3, wherein the first field plate is spaced from the first voltage divider ring by less than one-half of an off-pitch distance and by more than a trench polysilicon field plate nearest the first field plate and a voltage divider ring nearest the first voltage divider ring.
5. The transistor termination structure of claim 1, wherein no trench polysilicon field plate is provided between a second voltage divider ring and the main node, the second voltage divider ring being the closest voltage divider ring to the main node; the transistor terminal structure further comprises a first metal field plate arranged on the substrate and extending from the main junction to the second voltage division ring.
6. The transistor termination structure of claim 5, wherein the length of the first metal field plate is greater than or equal to 1 micron and less than or equal to the spacing between the main junction and the second voltage divider ring.
7. The transistor termination structure of claim 3, further comprising a second metal field plate extending from above the cutoff ring to the first voltage divider ring and electrically connected to the cutoff ring, the second metal field plate having a length less than one-half of a cutoff spacing.
8. The transistor termination structure of claim 1, wherein said cutoff ring has a conductivity type opposite to each of said voltage divider rings.
9. A method of fabricating a transistor termination structure that annularly surrounds an active region of a transistor in a plane, the method comprising:
providing a substrate, wherein a first mask layer is formed on the substrate, and a voltage division ring doping window is formed in the first mask layer;
injecting second conductive type impurities through the grading ring doping window to form a plurality of grading rings on the substrate;
forming a hard mask layer on the substrate, wherein the hard mask layer is provided with a groove window, and the hard mask layer and the groove window are positioned in the active region and the terminal structure;
etching a groove below the groove window, wherein the groove comprises an active area groove and a plurality of terminal grooves, and each terminal groove is positioned between adjacent voltage division rings and on the outer side of the voltage division ring farthest from the active area;
forming gate dielectric layers on the inner surfaces of the active region grooves and the inner surfaces of the terminal grooves;
depositing polycrystalline silicon and reversely etching to form a trench polycrystalline silicon field plate in each terminal trench, wherein no more than one trench polycrystalline silicon field plate is arranged between every two adjacent voltage dividing rings;
forming a second mask layer on the substrate, wherein the second mask layer is provided with a stop ring injection window;
and implanting first conductive type impurities through the stop ring implantation window to form a stop ring on the substrate, wherein the first conductive type and the second conductive type are opposite conductive types.
10. The method of claim 9, wherein the step of etching the trench below the trench window is a dry etching process, and further comprising a step of thermally growing a sacrificial oxide layer on the inner surface of the trench and removing the sacrificial oxide layer with a hydrofluoric acid solution before the step of forming the gate dielectric layer on the inner surface of the active region trench and the inner surface of each terminal trench.
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