WO2021082273A1 - Trench-type field-effect transistor structure and preparation method therefor - Google Patents

Trench-type field-effect transistor structure and preparation method therefor Download PDF

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Publication number
WO2021082273A1
WO2021082273A1 PCT/CN2019/130496 CN2019130496W WO2021082273A1 WO 2021082273 A1 WO2021082273 A1 WO 2021082273A1 CN 2019130496 W CN2019130496 W CN 2019130496W WO 2021082273 A1 WO2021082273 A1 WO 2021082273A1
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trench
gate
layer
extraction
dielectric layer
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PCT/CN2019/130496
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French (fr)
Chinese (zh)
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陈雪萌
王艳颖
杨林森
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华润微电子（重庆）有限公司
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Publication of WO2021082273A1 publication Critical patent/WO2021082273A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Definitions

  • the invention relates to the technical field of integrated circuit design and manufacturing, in particular to a trench field effect transistor structure and a preparation method thereof.
  • the trench device As an important power device, the trench device has a wide range of applications. It has lower on-resistance, faster switching speed and good avalanche resistance. The requirements of energy saving, emission reduction and market competition can further reduce the on-resistance of the device while ensuring that other performance parameters of the device remain unchanged. As we all know, reducing the lateral spacing of trench-type device cells and increasing the cell density is a very effective method to reduce the source-drain on-resistance. However, limited by the capabilities of the lithography machine and the etching machine, the lateral spacing of the cells cannot be continuously reduced.
  • the purpose of the present invention is to provide a trench field effect transistor structure and a manufacturing method thereof, which is used to solve the limitation of the ability of the photolithography machine and the etching machine in the prior art. It is difficult to continue to reduce the lateral spacing of cells, and it is difficult to continue to reduce the on-resistance of the device.
  • the present invention provides a method for fabricating a trench field effect transistor structure.
  • the fabricating method includes the following steps:
  • the epitaxial layer is etched based on the sidewall oxide layer to form a second device trench communicating with the first device trench, and the width of the second device trench is smaller than that of the first device The width of the groove;
  • the source contact hole penetrates the source region to the body region and exposes the body region;
  • At least a conductive material layer is filled in the source contact hole to form a source electrode structure, and a bottom electrode structure electrically connected to the substrate is formed on the side of the substrate away from the epitaxial layer.
  • the present invention also provides a trench field effect transistor structure, wherein the trench field effect transistor structure is preferably prepared by the preparation method of the present invention, and the trench field effect transistor structure includes:
  • the epitaxial layer of the first doping type is formed on the substrate, a plurality of gate trenches are formed in the epitaxial layer, and each of the gate trenches includes an upper and lower interconnection arrangement
  • the first device trench and the second device trench of the second device trench, the width of the second device trench is smaller than the width of the first device trench;
  • a shielding dielectric layer is filled in the trench of the first device
  • the body region of the second doping type is formed in the epitaxial layer between adjacent gate trenches;
  • the source region of the first doping type is formed in the body region and adjacent to the gate trench, and a source contact hole that penetrates the source region and exposes the body region is formed in the source region ;
  • the source electrode structure is filled at least in the source contact hole
  • the bottom electrode structure is formed on the side of the substrate away from the epitaxial layer and is electrically connected to the substrate.
  • a first device trench with a larger opening is first formed, and then the etching is continued to form a first device trench.
  • a second device trench with a smaller opening, and a shielding dielectric layer is formed in the first device trench, a self-aligned source contact hole is formed in the active area of the device through process design, and the lateral size of the cell can be reduced Below 1 micron, the cell density of the device can be increased, and the on-resistance of the device can be reduced.
  • trench-type devices such as trench-type MOSFET and trench-type IGBT.
  • Fig. 1 shows a flow chart of the manufacturing process of the trench field effect transistor of the present invention.
  • FIG. 2 is a diagram showing the formation of an epitaxial layer in the preparation of a trench field effect transistor of the present invention.
  • FIG. 3 is a diagram showing the formation of the first device trench and the first extraction trench during the preparation of the trench field effect transistor of the present invention.
  • FIG. 4 is a diagram showing the formation of a surface oxide layer in the preparation of a trench field effect transistor of the present invention.
  • FIG. 5 is a diagram showing the formation of a sidewall oxide layer in the preparation of a trench field effect transistor of the present invention.
  • FIG. 6 is a diagram showing the formation of the second device trench and the second extraction trench during the preparation of the trench field effect transistor of the present invention.
  • FIG. 7 is a diagram showing the formation of the gate trench and the lead-out gate trench during the preparation of the trench field effect transistor of the present invention.
  • FIG. 8 is a diagram showing the formation of the gate dielectric layer and the extraction of the gate dielectric layer in the preparation of the trench field effect transistor of the present invention.
  • FIG. 9 is a diagram showing the formation of a gate material layer in the preparation of a trench field effect transistor of the present invention.
  • FIG. 10 is a diagram showing the formation of the gate layer and the extraction gate layer in the preparation of the trench field effect transistor of the present invention.
  • FIG. 11 is a diagram showing the formation of the body region in the preparation of the trench field effect transistor of the present invention.
  • FIG. 12 is a diagram showing the formation of a shielding dielectric material layer in the preparation of a trench field effect transistor of the present invention.
  • FIG. 13 is a diagram showing the formation of a shielding dielectric layer, a shielding extraction dielectric layer, and an intermediate dielectric layer in the preparation of the trench field effect transistor of the present invention.
  • FIG. 14 is a diagram showing the formation of the source region in the preparation of the trench field effect transistor of the present invention.
  • FIG. 15 is a diagram showing the formation of a source contact hole in the preparation of a trench field effect transistor of the present invention.
  • FIG. 16 is a diagram showing the formation of the gate contact hole in the preparation of the trench field effect transistor of the present invention.
  • FIG. 17 is a diagram showing the structure of the source electrode and the gate electrode formed in the preparation of the trench field effect transistor of the present invention.
  • the present invention provides a method for manufacturing a trench field effect transistor structure.
  • the manufacturing method includes the following steps:
  • the epitaxial layer is etched based on the sidewall oxide layer to form a second device trench communicating with the first device trench, and the width of the second device trench is smaller than that of the first device The width of the groove;
  • a shielding dielectric layer is filled in the first device trench, and a source region is formed in the body region based on the shielding dielectric layer, and the source region is formed between adjacent gate trenches and is connected to all the gate trenches.
  • the gate trench is in contact;
  • the source contact hole penetrates the source region to the body region and exposes the body region;
  • At least a conductive material layer is filled in the source contact hole to form a source electrode structure, and a bottom electrode structure electrically connected to the substrate is formed on the side of the substrate away from the epitaxial layer.
  • a substrate 100 of a first doping type is provided, and an epitaxial layer 101 of the first doping type is formed on the substrate 100.
  • the first doping type (ie, the first conductivity type) may be P-type doping or N-type doping, and may be implanting the first doping type (
  • the substrate 100 formed by ions of P-type or N-type) is set according to actual device requirements.
  • the N-type doped substrate 100 is selected.
  • it may be a heavily doped substrate.
  • the bottom 100 may be such that the concentration of the first doping type ions doped in the substrate 100 is greater than or equal to 1 ⁇ 10 16 /cm 3 .
  • the substrate 100 may be a silicon substrate 100, a silicon germanium substrate 100, a silicon carbide substrate 100, etc.
  • the substrate 100 is selected as an N++ type doped silicon substrate 100
  • the resistivity range is between 0.001 ohm-cm and 0.003 ohm-cm.
  • the first doping type and the second doping type (ie, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (first conductivity type) semiconductor is an N-type semiconductor
  • the second doping type (second conductivity type) semiconductor is a P-type semiconductor
  • the trench MOSFET device of the present invention is an N-type device; on the contrary, the trench MOSFET device of the present invention is a P-type device.
  • the doping type of the epitaxial layer 101 is consistent with the doping type of the substrate 100.
  • the doping concentration of the epitaxial layer 101 is lower than the doping concentration of the substrate 100
  • the intrinsic epitaxial layer 101 may be formed on the upper surface of the substrate 100 of the first doping type by an epitaxial process, and then the first dopant is implanted into the intrinsic epitaxial layer 101 through an ion implantation process.
  • Doped ions to form the epitaxial layer 101 of the first doping type in another example, an epitaxial process can also be used to directly epitaxially form the second doping type on the upper surface of the substrate 100 of the first doping type.
  • the epitaxial layer 101 is selected as an N-type monocrystalline silicon epitaxial layer 101.
  • a plurality of first device trenches 103 are formed in the epitaxial layer 101.
  • the method of forming the first device trench 103 includes the following steps:
  • a mask material layer is formed on the surface of the epitaxial layer 101, wherein the mask material layer includes a silicon oxide layer.
  • the thickness of the mask material layer ranges from 8000 angstroms to 15000 angstroms;
  • the epitaxial layer 101 is etched based on the first mask 102 to form the first device trench 103 in the epitaxial layer 101.
  • the width d of the first device trench 103 is 0.2 ⁇ m to 0.4 ⁇ m
  • the depth w of the first device trench 103 is 0.2 ⁇ m to 0.4 ⁇ m.
  • a method for forming the first device trench 103 is provided, and the first device trench 103 can be formed by a photolithography-etching process, such as in the epitaxial layer 101 first.
  • a mask material layer is formed on the surface, and the mask material layer can be formed by a chemical vapor deposition process.
  • the deposition thickness can be 10,000 angstroms, 12,000 angstroms, etc., and then use the first photolithography plate to perform a photolithography process to form an etching
  • the pattern of the first device trench 103 is obtained, and the epitaxial layer 101 is etched based on the first mask 102 obtained after the patterning to form the first device trench 103, as described in etching using a dry etching process
  • the epitaxial layer 101 wherein, in an example, the width of the first device trench 103 may be between 0.3 micrometers, and the depth of the first device trench 103 may be 0.25 micrometers, where the width refers to the lateral dimension As shown in w in FIG. 3, depth refers to the size of the first device trench 103 buried in the epitaxial layer 101, as shown in d in FIG.
  • the number and layout of the first device trenches 103 can be selected according to actual requirements.
  • a sidewall oxide layer 106 is formed on the sidewall of the first device trench 103.
  • the method of forming the sidewall oxide layer 106 includes: forming a surface oxide layer 105 on the inner wall of the first device trench 103, and removing the surface oxide layer 105 at the bottom of the first device trench 103 The sidewall oxide layer 106 is formed.
  • the etching mask of the first device trench 103 is retained before the formation of the surface oxide layer 105, the surface oxide layer 105 is formed based on a thermal oxidation process, and dry etching is used based on the etching mask. The etching process removes the surface oxide layer 105 at the bottom of the first device trench 103.
  • a sidewall oxide layer 106 is formed on the sidewall of the first device trench 103 to be used for the etching of the second device trench 107 with a thickness.
  • a surface oxide layer 105 is formed on the inner wall of the first device trench 103, that is, the surface oxide layer 105 is formed on the bottom and sidewalls of the first device trench 103.
  • a thermal oxidation process is used.
  • the surface oxide layer 105 is formed, and its material includes but is not limited to silicon oxide.
  • the thickness of the surface oxide layer 105 is between 0.2 ⁇ m and 0.3 ⁇ m, which may be beneficial to subsequent second device trenches.
  • 107 is formed without causing damage to the device structure.
  • the surface oxide layer 105 is formed, in one example, a dry etching process is used to remove the surface oxide layer 105 at the bottom of the first device trench 103, Thus, the sidewall oxide layer 106 is formed.
  • the etching mask used when forming the first device trench 103 is retained. For example, it may be the aforementioned one.
  • the first mask 102 is commonly used for subsequent etching.
  • the epitaxial layer 101 is etched based on the sidewall oxide layer 106 to form a second device trench 107 communicating with the first device trench 103, Moreover, the width of the second device trench 107 is smaller than the width of the first device trench 103.
  • the sidewall oxide layer 106 is removed to expose the first device trench 103 and the second device trench 107, corresponding to the first device trench 103 And the second device trench 107 constitutes a gate trench 108.
  • the sidewall oxide layer 106 before removing the sidewall oxide layer 106, it further includes a step of forming a sacrificial layer (not shown in FIGS. 6 and 7) on the inner wall of the second device trench 107, wherein wet etching is used The process removes the sacrificial layer and the sidewall oxide layer 106.
  • the gate trench 108 is formed, and the formed gate trench 108 includes the first device trench 103 and the second device trench 107, that is, a similar bowl mouth is formed.
  • the upper and lower structures are small, which can facilitate the implementation of the subsequent self-alignment process.
  • the present invention uses only one photolithography plate to form the gate trench 108 of the device with the “bowl-mouth” structure mentioned above.
  • the sidewall oxide layer 106 formed previously is directly used as an etching mask, and the etching mask formed based on the first device trench 103 can be used as a protection, simplifying The process improves the utilization of materials and saves costs.
  • the second device trench 107 is formed by a dry etching process.
  • the sidewall oxide layer 106 is removed.
  • the etching mask formed by the first device trench 103 is retained, such as when the first mask 102 is retained, the first mask 102 is also removed at the same time, so as to finally obtain the gate trench ⁇ 108 ⁇ Slot 108.
  • the depth of the first device trench 103 is smaller than the depth of the second device trench 107.
  • a sacrificial layer is also formed on the sidewall of the second device trench 107 to repair the damage caused by the etching process.
  • it may be an oxide layer, such as a silicon oxide layer.
  • the sacrificial layer is formed by a thermal oxidation process.
  • the thickness of the sacrificial layer is between 500 angstroms and 1250 angstroms, which may be 800 angstroms. Angstroms, 1000 Angstroms, and then the sacrificial layer and the sidewall oxide layer 106 on the sidewall of the first device trench 103 can be removed at the same time. Lower a small gate trench 108.
  • a gate dielectric layer 111 is formed at least on the inner wall of the second device trench 107, and a gate layer 114 is formed on the surface of the gate dielectric layer 111.
  • the gate The pole layer 114 fills the second device trench 107.
  • the gate dielectric layer 111 also extends to the inner wall of the first device trench 103 and the surface of the epitaxial layer 101 around the first device trench 103;
  • the step of forming the gate layer 114 includes depositing a gate material layer 113 on the surface of the gate dielectric layer 111, and performing an over-etching process on the gate material layer 113 to remove all the materials.
  • the gate material layer 113 in the first device trench 103 and on the epitaxial layer 101 around the first device trench 103 forms the gate layer 114.
  • the gate dielectric layer 111 is formed after the gate trench 108 is formed.
  • the gate dielectric layer 111 may be formed only on the inner wall of the second device trench 107, or may be formed on the entire surface.
  • the inner wall of the gate trench 108 may further extend to the epitaxial layer 101 around the gate trench 108.
  • the gate dielectric layer 111 is continuously formed on the gate trench 108
  • the gate dielectric layer 111 can be formed by a high-temperature thermal oxidation process, and the thickness range is 150 angstroms to 500 angstroms, such as 200 angstroms, 300 angstroms, etc.
  • the gate layer 114 is formed on the surface of the gate dielectric layer 111 of the second device trench 107 and fills the second device trench 107.
  • the material of the gate layer 114 includes but not limited to polysilicon, the gate layer 114 may be formed by a chemical vapor deposition process.
  • the gate dielectric layer 111 also extends to the epitaxial layer 101 around the gate trench 108, The method of the gate layer 114 may be to first deposit a gate material layer 113 on the surface of the dielectric layer, as shown in FIG. 9, for example, it may be deposited by a chemical vapor deposition process.
  • the formed gate The thickness of the material layer 113 is between 0.1 ⁇ m and 1 ⁇ m, such as 0.5 ⁇ m or 0.8 ⁇ m.
  • the thickness here refers to the thickness of the gate material layer 113 formed on the epitaxial layer 101, such as Shown by s in Figure 9.
  • a dry etching process is used to remove the excess gate material layer 113 to form the gate layer 114, wherein the gate layer 114 (such as polysilicon) fills the deep trench (the The second device trench 107), the upper surface of the gate layer 114 is flush with the upper opening of the second device trench 107.
  • the polysilicon surface is flush with the opening on the deep trench, optionally Ground
  • the dry etching of the gate material layer 113 adopts over-etching and basically stops at the bottom of the first device trench 103, where over-etching refers to setting a main etching, after the main etching Perform a subsequent etching. For example, increase the etching time and continue to use the same etching parameters for etching.
  • the gate dielectric layer 111 is formed on the epitaxial layer 101, and over-etching is used.
  • the process of etching the gate material layer 113 when the signal of the gate dielectric layer 111 (such as silicon oxide) is detected, an over-etching time is set to realize the etching termination at the bottom of the first device trench 103
  • the purpose is to form the gate layer 114 and make the upper surface of the gate layer 114 flush with the upper opening of the second device trench 107.
  • a body region 116 of the second doping type is formed in the epitaxial layer 101, and the body region 116 is located between the adjacent gate trenches 108.
  • the depth of the body region 116 does not exceed the depth of the second device trench 107.
  • the second doping type represents a doping type opposite to the first doping type, If the first doping type is N-type, the second doping type is P-type, and if the first doping type is P-type, the second doping type is N-type, and The doping type of the body region 116 is opposite to the doping type of the epitaxial layer 101 and the substrate 100.
  • the depth of the body region 116 is smaller than the depth of the gate trench 108, and the There is a height difference between the bottom of the body region 116 and the bottom of the gate layer 114, that is, the distance between the bottom of the body region 116 and the bottom of the epitaxial layer 101 is greater than that of the gate trench 108.
  • the distance from the bottom of the epitaxial layer 101, in this example, the body region 116 is selected to be P-type lightly doped.
  • forming the body region 116 also includes a step of performing high temperature annealing after ion implantation.
  • the implantation dose is adjusted according to the threshold voltage, breakdown voltage and other performance parameters of the device.
  • the implantation is adjusted.
  • the dose is 5E12/CM ⁇ 2 to 1E13/CM ⁇ 2.
  • a shielding dielectric layer 118 is filled in the first device trench 103, and a source region 121 is formed in the body region 116 based on the shielding dielectric layer 118, The source region 121 is formed between adjacent gate trenches 108, that is, the edge of the source region 121 is adjacent to the edge of the gate trench 108.
  • the step of forming the shielding dielectric layer 118 and the source region 121 includes: forming a shielding dielectric material on the first device trench 103 and the epitaxial layer 101 around the first device trench 103 Layer 117, and patterning the shielding dielectric material layer 117 based on the second photolithography to define an active region, ion implantation is performed on the active region to form the source region 121, after the patterning
  • the remaining shielding dielectric material layer 117 filled in the first device trench 103 constitutes the shielding dielectric layer 118.
  • the implantation energy for performing the ion implantation is between 60Kev and 120Kev, and the implantation angle is between 7 degrees and 30 degrees.
  • the depth of the source region 121 is greater than the depth of the first device trench 103.
  • the source region 121 of the device is formed in the body region 116, that is, the source electrode of the trench field effect transistor is prepared, wherein the source region 121 is formed in the adjacent Between the gate trenches 108, the edge of the source region 121 is adjacent to the edge of the gate trench 108.
  • ion implantation to form the source region 121 is performed on the body region 116. 121 is formed in the body region 116, and the upper surface of the source region 121 is flush with the upper surface of the body region 116.
  • the implantation energy for performing the ion implantation is between 60Kev and 120Kev, such as 70Kev, 80Kev, or 100Kev, etc.
  • the implantation angle is between 7 degrees and 30 degrees, for example, 10 degrees. Or 20 degrees or 25 degrees, which may facilitate the formation of the source region.
  • the above-mentioned angle design is beneficial to the subsequent activation after ion implantation, and the ions diffuse below the shielding dielectric layer to form the source region 121 .
  • the depth of the source region 121 is greater than the depth of the first device trench 103, which is beneficial to prevent the source region of the device from not being connected to the channel, causing the device to fail to turn on or to have a relatively large on-resistance.
  • the depth of the source region 121 is greater than the depth of the first device trench 103, that is, the height of the overlapping portion of the two can be 0.08 ⁇ m-0.12 ⁇ m, or 0.1 ⁇ m.
  • a method for forming the source region 121 is provided.
  • a layer of shielding dielectric material 117 is formed on the entire surface of the device, which can be formed by a chemical vapor deposition process.
  • the thickness of the shielding dielectric material layer 117 is between 0.5 micrometers and 1 micrometer, and can be 0.6 micrometers or 0.8 micrometers.
  • the thickness here means that the shielding dielectric layer 118 is formed on the epitaxial layer.
  • the thickness above the layer 101 is shown as m in FIG. 12.
  • the masking dielectric material layer 117 is patterned based on the second photolithography to define the active area, as shown in FIG. 13.
  • the active region reveals the position where the source region 121 needs to be formed, the corresponding shielding dielectric material layer 117 above the epitaxial layer 101 is removed, and the first device trench 103 filled in the The shielding dielectric layer 118 is then subjected to ion implantation under the shielding of the shielding dielectric layer 118 to form the source region 121, as shown in FIG. 14.
  • annealing is further included to form the source region 121.
  • a heavily doped (for example, n+) device source region 121 is formed.
  • a self-aligned source contact hole 122 is formed in the epitaxial layer 101 based on the shielding dielectric layer 118, and the source contact hole 122 penetrates the source region 121 To the body region 116, the bottom of the source contact hole 122 exposes the body region 116.
  • the opening edge of the source contact hole 122 is adjacent to the edge of the corresponding source region 121, that is, the width of the source contact hole 122 is equal to that between two adjacent first device trenches 103
  • the sidewall of the contact hole 122 is an inclined sidewall, and the cross-sectional shape of the source contact hole 122 includes an inverted trapezoid.
  • the source contact hole 122 of the trench field effect transistor of the present invention is formed.
  • a shielding dielectric layer 118 is formed in the device trench 103, so that the epitaxial layer 101 can be etched using the shielding dielectric layer 118 as a mask to form a self-aligned source contact hole 122 in the active area, thereby
  • the lateral spacing of the device can be reduced, such as reduced to less than 1 micron, which increases the density of the device cell and reduces the on-resistance of the source and drain of the device.
  • the source region can be formed at the same time based on the same shielding dielectric layer 118. 121 and the source contact hole 122 to simplify the process and save cost. As shown in FIG.
  • the first device trench 103 and the source contact hole 102 are arranged alternately is formed, and the first device trench 103 It is closely adjacent to the source contact hole 102.
  • the right edge of the first device trench 103 is adjacent to the left edge of the first source contact hole 102, and the first source contact hole The right edge of 102 is adjacent to the left edge of the second first device trench 103, and so on.
  • the longitudinal cross-sectional shape of the source contact hole 122 may be an inverted trapezoid.
  • the source contact hole 122 extends through the source region 121 into the body region 116, thereby The electrical stability of the device can be improved.
  • At least a conductive material layer is filled in the source contact hole 122 to form a source electrode structure 124, and is located on the side of the substrate 100 away from the epitaxial layer 101 A lower electrode structure electrically connected to the substrate 100 is formed.
  • a conductive material layer is filled therein to form the source electrode to electrically lead out the source region 121 and the body region 116, as an example
  • the conductive material layer filled in the source contact hole 122 is also connected to realize a common connection between the sources.
  • a lower electrode structure is formed on the other side of the substrate 100 to serve as the drain of the device.
  • the material of the conductive material layer may be polysilicon or metal, but it is not limited to this.
  • the method for preparing the trench field effect transistor structure further includes a step of preparing a gate structure, and the epitaxial layer 101 also defines a terminal region, wherein the formation of the At the same time as the gate trench 108, an extraction gate trench 110 is also prepared in the terminal region.
  • the extraction gate trench 110 includes a first extraction trench 104 and a second extraction trench 109 connected up and down, and formed
  • the first device trench 103 is formed at the same time as the first extraction trench 104
  • the second device trench 107 is formed at the same time as the second extension trench 109 is formed
  • the gate dielectric layer 111 is formed at the same time
  • An extraction gate dielectric layer 112 is formed on the inner wall of the second extraction trench 109.
  • an extraction gate layer 115 is formed in the second extraction trench 109 to form the shielding dielectric layer 118.
  • a shielding extraction dielectric layer 119 is formed in the first extraction trench 104 to prepare the extraction gate structure.
  • the method further includes the step of forming a gate contact that exposes the extraction gate layer 115 on the extraction gate layer 115 based on a third photolithography. A hole 123, the gate contact hole 123 penetrates the intermediate dielectric layer 120 and the shielding and drawing dielectric layer 119.
  • the extraction gate trench 110 is also prepared in the epitaxial layer 101.
  • the area corresponding to the epitaxial layer 101 is pre-divided into devices Region B and terminal region A, wherein the gate trench 108 is prepared in the device region B, and the extraction trench is prepared in the terminal region A.
  • Both can be prepared based on the same process and mask, that is, In an example, these two trench patterns are formed on the trench first mask 102, and then etching is performed based on the patterns, that is, the first device trench is formed based on the first mask 102.
  • the first lead-out trench 104 is also formed.
  • the sidewall oxide layer 106 is formed, it is also formed on the sidewall of the first lead-out trench 104, so that the first lead-out trench 104 can be formed based on it.
  • the second extraction trench 109 refer to the preparation of the gate trench 108 for related description.
  • an extraction gate dielectric layer 112 is formed on the bottom and sidewalls of the extraction trench while the gate dielectric layer 111 is formed.
  • the gate layer 114 is formed by The gate material layer 113 is simultaneously formed in the lead-out gate trench 110 to prepare the lead-out gate layer 115.
  • the shielding dielectric layer 118 is formed, the shielding extraction dielectric layer 119 and the intermediate dielectric layer 120 are simultaneously prepared and formed in the first extraction trench 104.
  • the second When the photolithography plate is etched, the shielding dielectric material layer 117 corresponding to the active area is removed, so that the shielding dielectric layer 118 is formed in the first device trench 103 in the core area while retaining the terminal
  • the layer forms the intermediate dielectric layer 120.
  • the etching of the shielding dielectric layer 118 in the interface range of the device region B and the terminal region A can be selected according to actual conditions, such as As shown in FIG. 13, the removal of the shielding material layer stays above the outermost gate trench 108 in the boundary range.
  • the conductive material layer is also filled in the gate contact hole 123 and extends to the intermediate dielectric layer 120 around the gate contact hole 123 and extends to the source On the shielding dielectric layer 118 around the electrode contact hole 122, wherein the preparation method further includes patterning the conductive material layer based on a fourth photolithography plate to form a gate electrode structure 125 and the source electrode Structure 124 steps.
  • it further includes the step of preparing a gate contact hole 123 based on a third photolithography, wherein the bottom of the gate contact hole 123 may be flush with the bottom of the first extraction trench 104, which has just been revealed
  • the lead-out gate layer 115 may also extend into the lead-out gate layer 115.
  • terminal contact holes can also be prepared in the terminal area, such as the through hole prepared next to the gate contact hole in the terminal area, and the terminal contact hole extends into the epitaxial layer. Used as a connection through hole when the terminal is connected to the substrate.
  • the source electrode structure 124 and the gate electrode structure 125 are formed by depositing a whole piece of conductive material layer on the core region and the terminal region. When the entire conductive material layer is deposited, and then etched based on the fourth photolithography, the source electrode structure 124 and the gate electrode structure 125 are defined to be separated.
  • the conductive material The thickness of the material layer is between 0.8 ⁇ m and 2 ⁇ m, and can be 1 ⁇ m or 1.5 ⁇ m, etc. The thickness here refers to the thickness of the conductive material layer formed on the epitaxial layer 101, as shown in n in FIG. 17 Shown.
  • the present invention also provides a trench field effect transistor structure, wherein the field effect transistor structure is preferably prepared by the trench field effect transistor manufacturing method of the present invention Obtained, the trench field effect transistor structure includes:
  • the epitaxial layer 101 of the first doping type is formed on the substrate 100, and a plurality of gate trenches 108 are formed in the epitaxial layer 101, and each of the gate trenches Each 108 includes a first device trench 103 and a second device trench 107 connected up and down, and the width of the second device trench 107 is smaller than the width of the first device trench 103;
  • the gate layer 114 is formed on the surface of the gate oxide layer, and the gate layer 114 fills the second device trench 107;
  • the shielding dielectric layer 118 is filled in the first device trench 103;
  • the body region 116 of the second doping type is formed in the epitaxial layer 101 between adjacent gate trenches 108;
  • the source region 121 of the first doping type is formed in the body region 116 between adjacent gate trenches 108 and is in contact with the gate trench 108, in the source region 121 A source contact hole 122 that penetrates the source region 121 and exposes the body region 116 is formed;
  • the source electrode structure 124 is filled at least in the source contact hole 122;
  • the bottom electrode structure is formed on the side of the substrate 100 away from the epitaxial layer 101 and is electrically connected to the substrate 100.
  • the first doping type (ie, the first conductivity type) may be P-type doping or N-type doping, and may be implanting the first doping type (
  • the substrate 100 formed by ions of P-type or N-type) is set according to actual device requirements.
  • the N-type doped substrate 100 is selected.
  • it may be a heavily doped substrate.
  • the bottom 100 for example, may be that the concentration of the first doping type ions doped in the substrate 100 is greater than or equal to 1 ⁇ 10 16 /cm 3 .
  • the substrate 100 may be a silicon substrate 100, a silicon germanium substrate 100, a silicon carbide substrate 100, etc.
  • the substrate 100 is selected as an N++ type doped silicon substrate 100 .
  • the first doping type and the second doping type (ie, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (first conductivity type) semiconductor is an N-type semiconductor
  • the second doping type (second conductivity type) semiconductor is a P-type semiconductor
  • the trench MOSFET device of the present invention is an N-type device; conversely, the trench MOSFET device of the present invention is a P-type device.
  • the doping type of the epitaxial layer 101 is consistent with the doping type of the substrate 100.
  • the doping concentration of the epitaxial layer 101 is lower than the doping concentration of the substrate 100
  • the intrinsic epitaxial layer 101 may be formed on the upper surface of the substrate 100 of the first doping type by an epitaxial process, and then the first dopant is implanted into the intrinsic epitaxial layer 101 through an ion implantation process.
  • Doped ions to form the epitaxial layer 101 of the first doping type in another example, an epitaxial process can also be used to directly epitaxially form the second doping type on the upper surface of the substrate 100 of the first doping type.
  • the epitaxial layer 101 is selected as an N-type monocrystalline silicon epitaxial layer 101.
  • the width of the first device trench 103 may be between 0.3 micrometers, and the depth of the first device trench 103 may be 0.25 micrometers, where the width refers to the lateral dimension, as shown in FIG.
  • the w in 3, depth refers to the size of the first device trench 103 buried in the epitaxial layer 101, as shown in d in FIG. 3.
  • the number and layout of the first device trenches 103 can be selected according to actual requirements.
  • the gate trench 108 formed in the present invention includes the first device trench 103 and the second device trench 107, that is, it forms a structure similar to a bowl with a large top and a small bottom. This can facilitate the implementation of the subsequent self-alignment process.
  • the gate dielectric layer 111 may be formed only on the inner wall of the second device trench 107, or may be formed on the entire inner wall of the gate trench 108, and It can be further extended to the epitaxial layer 101 around the gate trench 108, preferably the gate dielectric layer 111 is continuously formed on the inner wall of the gate trench 108 and around the gate trench 108 On the epitaxial layer 101, where the inner wall includes the side wall and the bottom, the thickness can be 150-500 angstroms, such as 200 angstroms, 300 angstroms, and so on.
  • the gate layer 114 is formed on the surface of the gate dielectric layer 111 of the second device trench 107 and fills the second device trench 107.
  • the gate layer 114 (such as polysilicon) Fill the deep trench (the second device trench 107).
  • the upper surface of the gate layer 114 is flush with the upper opening of the second device trench 107.
  • the polysilicon surface is flush with the deep trench.
  • the upper opening is flush, and the material of the gate layer 114 includes but is not limited to polysilicon.
  • the depth of the body region 116 does not exceed the depth of the gate trench 108.
  • the depth of the source region 121 is greater than the depth of the first device trench 103.
  • the second doping type represents a doping type opposite to the first doping type, as in the first doping type. If the first doping type is N-type, the second doping type is P-type. If the first doping type is P-type, the second doping type is N-type. The doping type is opposite to the doping type of the epitaxial layer 101 and the substrate 100.
  • the depth of the body region 116 is smaller than the depth of the gate trench 108, and the bottom of the body region 116 There is a height difference between the bottom of the gate layer 114 and the bottom of the gate layer 114, that is, the distance between the bottom of the body region 116 and the bottom of the epitaxial layer 101 is greater than that between the bottom of the gate trench 108 and the epitaxial layer.
  • the distance from the bottom of 101, in this example, the body region 116 is selected to be P-type lightly doped.
  • the source region 121 of the device is formed in the body region 116, that is, the source electrode of the trench field effect transistor is prepared, wherein the source region 121 is formed adjacent to the gate.
  • ion implantation to form the source region 121 is performed on the body region 116, and the source region 121 is formed in the body region. In the region 116, and the upper surface of the source region 121 is flush with the upper surface of the body region 116, in this example, a heavily doped (for example, n+) device source region 121 is formed.
  • the opening edge of the source contact hole 122 is adjacent to the edge of the corresponding source region 121, that is, the width of the source contact hole 122 is equal to that between two adjacent first device trenches 103
  • the sidewall of the contact hole 122 is an inclined sidewall, and the cross-sectional shape of the source contact hole 122 includes an inverted trapezoid.
  • the gate trench 108 is formed with a large upper and a lower gate, and a shielding dielectric layer 118 is formed in the first device trench 103, so that the shielding dielectric layer 118 can be used as a mask for the epitaxial layer 101 is etched, so that the lateral spacing of the device can be reduced, for example, reduced to less than 1 micron, which increases the density of the device cell and reduces the on-resistance of the source and drain of the device.
  • the source The opening of the contact hole 122 is in contact with the edge of the corresponding source region 121, that is, the size of the opening of the source contact hole 122 is the distance between the adjacent first device trenches 103, as shown in FIG.
  • the first device trench 103 and the source contact hole 102 are arranged alternately is formed, and the first device trench 103 is closely adjacent to the source contact hole 102, as described in the first one.
  • the right edge of the device trench 103 is adjacent to the left edge of the first source contact hole 102, and the right edge of the first source contact hole 102 is adjacent to the second first device trench 103
  • the longitudinal cross-sectional shape of the source contact hole 122 may be an inverted trapezoid.
  • the source contact hole 122 extends through the source region 121 Into the body region 116, thereby improving the electrical stability of the device.
  • a conductive material layer is filled therein to form the source electrode to electrically lead out the source region 121 and the body region 116, as an example
  • the conductive material layer filled in the source contact hole 122 is also connected to realize a common connection between the sources.
  • a lower electrode structure is formed on the other side of the substrate 100 to serve as the drain of the device.
  • the material of the conductive material layer may be polysilicon or metal, but it is not limited to this.
  • the trench field effect transistor structure further includes an extraction gate structure, and a terminal region is defined in the epitaxial layer 101, wherein the extraction gate structure is formed in the terminal region, and the extraction gate structure It includes: a lead-out gate trench 110, which includes a first lead-out trench 104 and a second lead-out trench 109 connected up and down; a lead-out gate dielectric formed on the inner wall of the second lead-out trench 109 Layer 112; an extraction gate layer 115 formed on the surface of the extraction gate dielectric layer 112, the extraction gate layer 115 filling the second extraction trench 109; and filling in the first extraction trench 104
  • the dielectric layer 119 is drawn out by shielding.
  • an intermediate dielectric layer 120 is further formed on the shielding extraction dielectric layer 119, and the trench field effect transistor structure further includes a gate contact hole 123 and a gate electrode structure 125, wherein the gate contact hole 123 successively penetrates the intermediate dielectric layer 120, the shielding extraction dielectric layer 119 to the extraction gate layer 115, and reveals the extraction gate layer 115, and the gate electrode structure 125 at least fills the gate In the contact hole 123.
  • the extraction gate trench 110 is also prepared in the epitaxial layer 101.
  • the area corresponding to the epitaxial layer 101 is pre-divided into devices Region B and terminal region A, wherein the gate trench 108 is prepared in the device region, and the extraction trench is prepared in the terminal region, wherein the first extraction trench 104 and the first The device trench 103, the second extraction trench 109 and the second device trench 107, the gate dielectric layer 111 and the extraction gate dielectric layer 112, the gate layer 114 and the extraction gate
  • the layer 115, the shielding dielectric layer 118 and the shielding extraction dielectric layer 119 can all be formed based on the same process and have the same size.
  • the interface between the core area and the terminal area can be selected according to actual conditions. As shown in FIG. 13, the removal of the shielding material layer stays above the outermost gate trench 108 in the boundary range.
  • the source electrode structure 124 and the gate electrode structure 125 are formed by depositing a whole piece of conductive material layer on the core region and the terminal region. When the entire conductive material layer is deposited, and then etched based on the fourth photolithography, the source electrode structure 124 and the gate electrode structure 125 are defined to be separated.
  • the conductive material The thickness of the material layer is between 0.8 ⁇ m and 2 ⁇ m, and can be 1 ⁇ m or 1.5 ⁇ m, etc.
  • the thickness here refers to the thickness of the conductive material layer formed on the epitaxial layer 101, as shown in n in FIG. 17 Shown.
  • the present invention when the gate trench is formed and etched, a first device trench with a larger opening is first formed, and then a second device trench with a smaller opening is formed by the etching.
  • a shielding dielectric layer is formed in the trench of the first device, and a self-aligned source contact hole is formed in the active area of the device through process design.
  • the lateral size of the cell can be reduced to less than 1 micron, thereby increasing the cell size of the device. Density, reduce the on-resistance of the device, suitable for trench-type devices such as trench-type MOSFET and trench-type IGBT. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial value.

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Abstract

Provided in the present invention are a trench-type field-effect transistor structure and a preparation method therefor, the preparation method comprising: providing a substrate (100) and forming an epitaxial layer (101); forming first device trenches (103); forming a side wall oxide layer (106); on the basis of the side wall oxide layer (106), etching the epitaxial layer (101) to form second device trenches (107); removing the side wall oxide layer (106) to form a gate dielectric layer (111), a gate electrode layer (114), and a body area (116); filling the first device trenches (103) with a shielding dielectric layer (118) and, on the basis of the shielding dielectric layer (118), forming a source area (121) and a self-aligned source electrode contact hole (122); and forming a source electrode structure (124) and a lower electrode structure.

Description

沟槽型场效应晶体管结构及其制备方法Trench type field effect transistor structure and preparation method thereof 技术领域Technical field
本发明涉及集成电路设计及制造技术领域，特别是涉及一种沟槽型场效应晶体管结构及其制备方法。The invention relates to the technical field of integrated circuit design and manufacturing, in particular to a trench field effect transistor structure and a preparation method thereof.
背景技术Background technique
沟槽型器件作为一种重要的功率器件具有很广泛的应有,其具有较低的导通电阻低、较快的开关速度和良好的抗雪崩冲击能力等。节能减排及市场竞争的要求在保证器件其它性能参数不变的条件下，进一步降低器件的导通电阻。众所周知,减小沟槽型器件元胞的横向间距，增加元胞密度是一种很有效的降低源漏极导通电阻的方法。然而，受光刻机台和刻蚀机台的能力限制，元胞的横向间距不可能一直减小下去。As an important power device, the trench device has a wide range of applications. It has lower on-resistance, faster switching speed and good avalanche resistance. The requirements of energy saving, emission reduction and market competition can further reduce the on-resistance of the device while ensuring that other performance parameters of the device remain unchanged. As we all know, reducing the lateral spacing of trench-type device cells and increasing the cell density is a very effective method to reduce the source-drain on-resistance. However, limited by the capabilities of the lithography machine and the etching machine, the lateral spacing of the cells cannot be continuously reduced.
因此，如何提供一种沟槽型场效应晶体管结构及其制备方法，以解决现有技术中的上述问题实属必要。Therefore, it is necessary to provide a trench field effect transistor structure and a manufacturing method thereof to solve the above-mentioned problems in the prior art.
发明内容Summary of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种沟槽型场效应晶体管结构及其制备方法，用于解决现有技术中受光刻机台和刻蚀机台的能力限制元胞的横向间距难以继续减小，器件导通电阻难以继续降低等问题。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a trench field effect transistor structure and a manufacturing method thereof, which is used to solve the limitation of the ability of the photolithography machine and the etching machine in the prior art. It is difficult to continue to reduce the lateral spacing of cells, and it is difficult to continue to reduce the on-resistance of the device.
为实现上述目的及其他相关目的，本发明提供一种沟槽型场效应晶体管结构的制备方法，所述制备方法包括如下步骤：In order to achieve the above objectives and other related objectives, the present invention provides a method for fabricating a trench field effect transistor structure. The fabricating method includes the following steps:
提供第一掺杂类型的衬底，并于所述衬底上形成所述第一掺杂类型的外延层；Providing a substrate of a first doping type, and forming an epitaxial layer of the first doping type on the substrate;
于所述外延层中形成若干个第一器件沟槽；Forming a plurality of first device trenches in the epitaxial layer;
于所述第一器件沟槽的侧壁形成侧壁氧化层；Forming a sidewall oxide layer on the sidewall of the first device trench;
基于所述侧壁氧化层对所述外延层进行刻蚀，以形成与所述第一器件沟槽连通的第二器件沟槽，且所述第二器件沟槽的宽度小于所述第一器件沟槽的宽度；The epitaxial layer is etched based on the sidewall oxide layer to form a second device trench communicating with the first device trench, and the width of the second device trench is smaller than that of the first device The width of the groove;
去除所述侧壁氧化层以显露所述第一器件沟槽及所述第二器件沟槽，对应的所述第一器件沟槽及所述第二器件沟槽构成栅极沟槽；Removing the sidewall oxide layer to expose the first device trench and the second device trench, and the corresponding first device trench and the second device trench form a gate trench;
至少于所述第二器件沟槽的内壁形成栅介质层，并于所述栅介质层表面形成栅极层，所述栅极层填充所述第二器件沟槽中；Forming a gate dielectric layer at least on the inner wall of the second device trench, and forming a gate layer on the surface of the gate dielectric layer, and the gate layer fills the second device trench;
于所述外延层中形成第二掺杂类型的体区，所述体区位于相邻的所述栅极沟槽之间；Forming a body region of the second doping type in the epitaxial layer, the body region being located between the adjacent gate trenches;
于所述第一器件沟槽中填充遮蔽介质层，并基于所述遮蔽介质层于所述体区中形成源区，所述源区邻接所述栅极沟槽；Filling a shielding dielectric layer in the first device trench, and forming a source region in the body region based on the shielding dielectric layer, and the source region is adjacent to the gate trench;
基于所述遮蔽介质层于所述外延层中形成自对准的源极接触孔，所述源极接触孔贯穿所述源区至所述体区，并显露所述体区；以及Forming a self-aligned source contact hole in the epitaxial layer based on the shielding dielectric layer, the source contact hole penetrates the source region to the body region and exposes the body region; and
至少于所述源极接触孔中填充导电材料层以形成源极电极结构，并于所述衬底远离所述外延层的一侧形成与所述衬底电连接的下电极结构。At least a conductive material layer is filled in the source contact hole to form a source electrode structure, and a bottom electrode structure electrically connected to the substrate is formed on the side of the substrate away from the epitaxial layer.
本发明还提供一种沟槽型场效应晶体管结构，其中，所述沟槽型场效应晶体管结构优选采用本发明的制备方法制备得到，所述沟槽型场效应晶体管结构包括：The present invention also provides a trench field effect transistor structure, wherein the trench field effect transistor structure is preferably prepared by the preparation method of the present invention, and the trench field effect transistor structure includes:
第一掺杂类型的衬底；A substrate of the first doping type;
所述第一掺杂类型的外延层，所述外延层形成于所述衬底上，所述外延层中形成有若干个栅极沟槽，每个所述栅极沟槽均包括上下连通设置的第一器件沟槽及第二器件沟槽，所述第二器件沟槽的宽度小于所述第一器件沟槽的宽度；The epitaxial layer of the first doping type, the epitaxial layer is formed on the substrate, a plurality of gate trenches are formed in the epitaxial layer, and each of the gate trenches includes an upper and lower interconnection arrangement The first device trench and the second device trench of the second device trench, the width of the second device trench is smaller than the width of the first device trench;
栅极氧化层，形成于所述第二器件沟槽的内壁上；A gate oxide layer formed on the inner wall of the second device trench;
栅极层，形成于所述栅极氧化层的表面，所述栅极层填充所述第二器件沟槽；A gate layer formed on the surface of the gate oxide layer, and the gate layer fills the second device trench;
遮蔽介质层，填充于所述第一器件沟槽中；A shielding dielectric layer is filled in the trench of the first device;
第二掺杂类型的体区，形成于相邻所述栅极沟槽之间的所述外延层中；The body region of the second doping type is formed in the epitaxial layer between adjacent gate trenches;
所述第一掺杂类型的源区，形成于所述体区中并邻接所述栅极沟槽，所述源区中形成有贯穿所述源区并显露所述体区的源极接触孔；The source region of the first doping type is formed in the body region and adjacent to the gate trench, and a source contact hole that penetrates the source region and exposes the body region is formed in the source region ；
源极电极结构，至少填充于所述源极接触孔中；以及The source electrode structure is filled at least in the source contact hole; and
下电极结构，形成于所述衬底远离所述外延层的一侧并与所述衬底电连接。The bottom electrode structure is formed on the side of the substrate away from the epitaxial layer and is electrically connected to the substrate.
如上所述，本发明的沟槽型场效应晶体管及制备方法，本发明在形成栅极沟槽刻蚀时，先形成了一个开口较大的第一器件沟槽，并继续刻蚀形成了一个开口较小的第二器件沟槽，并在第一器件沟槽中形成遮蔽介质层，通过工艺设计在器件的有源区形成自对准的源极接触孔,元胞的横向尺寸可以减小到1微米以下，从而可以增加器件的元胞密度，降低器件的导通电阻，适用于沟槽型MOSFET、沟槽型IGBT等沟槽型器件。As described above, in the trench field effect transistor and the manufacturing method of the present invention, when the gate trench is formed and etched, a first device trench with a larger opening is first formed, and then the etching is continued to form a first device trench. A second device trench with a smaller opening, and a shielding dielectric layer is formed in the first device trench, a self-aligned source contact hole is formed in the active area of the device through process design, and the lateral size of the cell can be reduced Below 1 micron, the cell density of the device can be increased, and the on-resistance of the device can be reduced. It is suitable for trench-type devices such as trench-type MOSFET and trench-type IGBT.
附图说明Description of the drawings
图1显示为本发明沟槽型场效应晶体管的制备工艺流程图。Fig. 1 shows a flow chart of the manufacturing process of the trench field effect transistor of the present invention.
图2显示为本发明沟槽型场效应晶体管制备中形成外延层的图示。FIG. 2 is a diagram showing the formation of an epitaxial layer in the preparation of a trench field effect transistor of the present invention.
图3显示为本发明沟槽型场效应晶体管制备中形成第一器件沟槽和第一引出沟槽图示。FIG. 3 is a diagram showing the formation of the first device trench and the first extraction trench during the preparation of the trench field effect transistor of the present invention.
图4显示为本发明沟槽型场效应晶体管制备中形成表面氧化层的图示。FIG. 4 is a diagram showing the formation of a surface oxide layer in the preparation of a trench field effect transistor of the present invention.
图5显示为本发明沟槽型场效应晶体管制备中形成侧壁氧化层图示。FIG. 5 is a diagram showing the formation of a sidewall oxide layer in the preparation of a trench field effect transistor of the present invention.
图6显示为本发明沟槽型场效应晶体管制备中形成第二器件沟槽和第二引出沟槽图示。FIG. 6 is a diagram showing the formation of the second device trench and the second extraction trench during the preparation of the trench field effect transistor of the present invention.
图7显示为本发明沟槽型场效应晶体管制备中形成栅极沟槽和引出栅沟槽的图示。FIG. 7 is a diagram showing the formation of the gate trench and the lead-out gate trench during the preparation of the trench field effect transistor of the present invention.
图8显示为本发明沟槽型场效应晶体管制备中形成栅介质层和引出栅介质层的图示。FIG. 8 is a diagram showing the formation of the gate dielectric layer and the extraction of the gate dielectric layer in the preparation of the trench field effect transistor of the present invention.
图9显示为本发明沟槽型场效应晶体管制备中形成栅极材料层的图示。FIG. 9 is a diagram showing the formation of a gate material layer in the preparation of a trench field effect transistor of the present invention.
图10显示为本发明沟槽型场效应晶体管制备中形成栅极层和引出栅极层的图示。FIG. 10 is a diagram showing the formation of the gate layer and the extraction gate layer in the preparation of the trench field effect transistor of the present invention.
图11显示为本发明沟槽型场效应晶体管制备中形成体区的图示。FIG. 11 is a diagram showing the formation of the body region in the preparation of the trench field effect transistor of the present invention.
图12显示为本发明沟槽型场效应晶体管制备中形成遮蔽介质材料层的图示。FIG. 12 is a diagram showing the formation of a shielding dielectric material layer in the preparation of a trench field effect transistor of the present invention.
图13显示为本发明沟槽型场效应晶体管制备中形成遮蔽介质层、遮蔽引出介质层及中间介质层的图示。FIG. 13 is a diagram showing the formation of a shielding dielectric layer, a shielding extraction dielectric layer, and an intermediate dielectric layer in the preparation of the trench field effect transistor of the present invention.
图14显示为本发明沟槽型场效应晶体管制备中形成源区的图示。FIG. 14 is a diagram showing the formation of the source region in the preparation of the trench field effect transistor of the present invention.
图15显示为本发明沟槽型场效应晶体管制备中形成源极接触孔的图示。FIG. 15 is a diagram showing the formation of a source contact hole in the preparation of a trench field effect transistor of the present invention.
图16显示为本发明沟槽型场效应晶体管制备中形成栅极接触孔的图示。FIG. 16 is a diagram showing the formation of the gate contact hole in the preparation of the trench field effect transistor of the present invention.
图17显示为本发明沟槽型场效应晶体管制备中形成源极电极结构和栅极电极结构图示。FIG. 17 is a diagram showing the structure of the source electrode and the gate electrode formed in the preparation of the trench field effect transistor of the present invention.
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The following describes the implementation of the present invention through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1-17。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可为一种随意的改变，且其组件布局形态也可能更为复杂。Refer to Figure 1-17. It should be noted that the diagrams provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner, so the diagrams only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation. For size drawing, the form, quantity and proportion of each component can be changed at will during actual implementation, and its component layout form may also be more complicated.
实施例一：Example one:
如图1所示，本发明提供一种沟槽型场效应晶体管结构的制备方法，所述制备方法包括如下步骤：As shown in FIG. 1, the present invention provides a method for manufacturing a trench field effect transistor structure. The manufacturing method includes the following steps:
提供第一掺杂类型的衬底，并于所述衬底上形成所述第一掺杂类型的外延层；Providing a substrate of a first doping type, and forming an epitaxial layer of the first doping type on the substrate;
于所述外延层中形成若干个第一器件沟槽；Forming a plurality of first device trenches in the epitaxial layer;
于所述第一器件沟槽的侧壁形成侧壁氧化层；Forming a sidewall oxide layer on the sidewall of the first device trench;
基于所述侧壁氧化层对所述外延层进行刻蚀，以形成与所述第一器件沟槽连通的第二器件沟槽，且所述第二器件沟槽的宽度小于所述第一器件沟槽的宽度；The epitaxial layer is etched based on the sidewall oxide layer to form a second device trench communicating with the first device trench, and the width of the second device trench is smaller than that of the first device The width of the groove;
去除所述侧壁氧化层以显露所述第一器件沟槽及所述第二器件沟槽，对应的所述第一器件沟槽及所述第二器件沟槽构成栅极沟槽；Removing the sidewall oxide layer to expose the first device trench and the second device trench, and the corresponding first device trench and the second device trench form a gate trench;
至少于所述第二器件沟槽的内壁形成栅介质层，并于所述栅介质层表面形成栅极层，所述栅极层填充所述第二器件沟槽中；Forming a gate dielectric layer at least on the inner wall of the second device trench, and forming a gate layer on the surface of the gate dielectric layer, and the gate layer fills the second device trench;
于所述外延层中形成第二掺杂类型的体区，所述体区位于相邻的所述栅极沟槽之间；Forming a body region of the second doping type in the epitaxial layer, the body region being located between the adjacent gate trenches;
于所述第一器件沟槽中填充遮蔽介质层，并基于所述遮蔽介质层于所述体区中形成源区，所述源区形成于相邻所述栅极沟槽之间并与所述栅极沟槽相接触；A shielding dielectric layer is filled in the first device trench, and a source region is formed in the body region based on the shielding dielectric layer, and the source region is formed between adjacent gate trenches and is connected to all the gate trenches. The gate trench is in contact;
基于所述遮蔽介质层于所述外延层中形成自对准的源极接触孔，所述源极接触孔贯穿所述源区至所述体区，并显露所述体区；以及Forming a self-aligned source contact hole in the epitaxial layer based on the shielding dielectric layer, the source contact hole penetrates the source region to the body region and exposes the body region; and
至少于所述源极接触孔中填充导电材料层以形成源极电极结构，并于所述衬底远离所述外延层的一侧形成与所述衬底电连接的下电极结构。At least a conductive material layer is filled in the source contact hole to form a source electrode structure, and a bottom electrode structure electrically connected to the substrate is formed on the side of the substrate away from the epitaxial layer.
下面将结合附图详细说明本发明的沟槽型场效应晶体管的制备工艺。The manufacturing process of the trench field effect transistor of the present invention will be described in detail below with reference to the accompanying drawings.
如图1中的S1及图2所示，提供第一掺杂类型的衬底100，并于所述衬底100上形成所述第一掺杂类型的外延层101。As shown in FIG. 1 and FIG. 2, a substrate 100 of a first doping type is provided, and an epitaxial layer 101 of the first doping type is formed on the substrate 100.
具体的，所述第一掺杂类型(即第一导电类型)可以是P型掺杂，也可以是N型掺杂，可以为采用离子注入工艺在衬底100中注入第一掺杂类型(P型或N型)的离子而形成的衬底100，以实际器件需求设定，在本示例中，选择为N型掺杂衬底100，另外，在一示例中，可以为重掺杂衬底100，如可以是在所述衬底100中掺杂的第一掺杂类型离子的浓度大于或等于1×10 16/cm 3。需要说明的，所述衬底100可以为硅衬底100、锗硅衬底100、碳化硅衬底100等，在本示例中，所述衬底100选用为N++型掺杂的硅衬底100，例如，可以是电阻率范围介于0.001ohm-cm～0.003ohm-cm之间。其中，第一掺杂类型与后续提到的第二掺杂类型(即第二导电类型)为相反的掺杂类型，当所述第一掺杂类型(第一导电类型)半导体为N型半导体、第二掺杂类型(第二导电类型)半导体为P型半导体时，本发明的沟槽MOSFET器件为N型器件；反之，本发明沟槽MOSFET器件为P型器件。 Specifically, the first doping type (ie, the first conductivity type) may be P-type doping or N-type doping, and may be implanting the first doping type ( The substrate 100 formed by ions of P-type or N-type) is set according to actual device requirements. In this example, the N-type doped substrate 100 is selected. In addition, in one example, it may be a heavily doped substrate. The bottom 100 may be such that the concentration of the first doping type ions doped in the substrate 100 is greater than or equal to 1×10 16 /cm 3 . It should be noted that the substrate 100 may be a silicon substrate 100, a silicon germanium substrate 100, a silicon carbide substrate 100, etc. In this example, the substrate 100 is selected as an N++ type doped silicon substrate 100 For example, the resistivity range is between 0.001 ohm-cm and 0.003 ohm-cm. Wherein, the first doping type and the second doping type (ie, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (first conductivity type) semiconductor is an N-type semiconductor When the second doping type (second conductivity type) semiconductor is a P-type semiconductor, the trench MOSFET device of the present invention is an N-type device; on the contrary, the trench MOSFET device of the present invention is a P-type device.
具体的，所述外延层101的掺杂类型与所述衬底100的掺杂类型一致，在一示例中，所述外延层101的掺杂浓度低于所述衬底100的掺杂浓度，其中，可以先采用外延工艺在所述 第一掺杂类型的所述衬底100的上表面形成本征外延层101，然后再通过离子注入工艺在所述本征外延层101内注入第一掺杂类型的离子以形成所述第一掺杂类型的外延层101；在另一示例中，还可以采用外延工艺直接在所述第一掺杂类型的衬底100的上表面外延形成所述第一掺杂类型的外延层101。本示例中，所述外延层101选用为N-型单晶硅外延层101。Specifically, the doping type of the epitaxial layer 101 is consistent with the doping type of the substrate 100. In an example, the doping concentration of the epitaxial layer 101 is lower than the doping concentration of the substrate 100, Wherein, the intrinsic epitaxial layer 101 may be formed on the upper surface of the substrate 100 of the first doping type by an epitaxial process, and then the first dopant is implanted into the intrinsic epitaxial layer 101 through an ion implantation process. Doped ions to form the epitaxial layer 101 of the first doping type; in another example, an epitaxial process can also be used to directly epitaxially form the second doping type on the upper surface of the substrate 100 of the first doping type. An epitaxial layer 101 of doping type. In this example, the epitaxial layer 101 is selected as an N-type monocrystalline silicon epitaxial layer 101.
如图1中的S2及图3所示，于所述外延层101中形成若干个第一器件沟槽103。As shown in S2 in FIG. 1 and FIG. 3, a plurality of first device trenches 103 are formed in the epitaxial layer 101.
作为示例，形成所述第一器件沟槽103的方法包括如下步骤：As an example, the method of forming the first device trench 103 includes the following steps:
于所述外延层101表面形成掩膜材料层，其中，所述掩膜材料层包括氧化硅层，在一示例中，所述掩膜材料层的厚度范围为8000埃至15000埃；A mask material layer is formed on the surface of the epitaxial layer 101, wherein the mask material layer includes a silicon oxide layer. In an example, the thickness of the mask material layer ranges from 8000 angstroms to 15000 angstroms;
基于第一光刻版对所述掩膜材料层进行图形化以形成第一掩膜102，所述第一掩膜102定义出待形成的所述第一器件沟槽103；以及Patterning the mask material layer based on a first photolithography plate to form a first mask 102, which defines the first device trench 103 to be formed; and
基于所述第一掩膜102对所述外延层101进行刻蚀以于所述外延层101中形成所述第一器件沟槽103。The epitaxial layer 101 is etched based on the first mask 102 to form the first device trench 103 in the epitaxial layer 101.
作为示例，所述第一器件沟槽103的宽度范围d为0.2微米至0.4微米，所述第一器件沟槽103的深度范围w为0.2微米至0.4微米。As an example, the width d of the first device trench 103 is 0.2 μm to 0.4 μm, and the depth w of the first device trench 103 is 0.2 μm to 0.4 μm.
具体的，在一示例中，提供一种所述第一器件沟槽103的形成方式，可以采用光刻-刻蚀的工艺形成所述第一器件沟槽103，如先在所述外延层101表面形成掩膜材料层，可以采用化学气相沉积工艺形成所述掩膜材料层，如沉积厚度可以是10000埃、12000埃等，接着用所述第一光刻版进行光刻工艺，形成刻蚀得到所述第一器件沟槽103的图形，以基于图形化后得到的第一掩膜102刻蚀外延层101形成所述第一器件沟槽103，如采用干法刻蚀工艺刻蚀所述外延层101，其中，在一示例中，所述第一器件沟槽103的宽度可以是0.3微米之间，所述第一器件沟槽103的深度可以是0.25微米，这里宽度指的是横向尺寸，如图3中的w，深度指的是所述第一器件沟槽103埋入所述外延层101中的尺寸，如图3中的d所示。另外，所述第一器件沟槽103的数量及布局可以依据实际需求进行选择。Specifically, in an example, a method for forming the first device trench 103 is provided, and the first device trench 103 can be formed by a photolithography-etching process, such as in the epitaxial layer 101 first. A mask material layer is formed on the surface, and the mask material layer can be formed by a chemical vapor deposition process. For example, the deposition thickness can be 10,000 angstroms, 12,000 angstroms, etc., and then use the first photolithography plate to perform a photolithography process to form an etching The pattern of the first device trench 103 is obtained, and the epitaxial layer 101 is etched based on the first mask 102 obtained after the patterning to form the first device trench 103, as described in etching using a dry etching process The epitaxial layer 101, wherein, in an example, the width of the first device trench 103 may be between 0.3 micrometers, and the depth of the first device trench 103 may be 0.25 micrometers, where the width refers to the lateral dimension As shown in w in FIG. 3, depth refers to the size of the first device trench 103 buried in the epitaxial layer 101, as shown in d in FIG. In addition, the number and layout of the first device trenches 103 can be selected according to actual requirements.
如图1中的S3及图4-5所示，于所述第一器件沟槽103的侧壁形成侧壁氧化层106。As shown in S3 in FIG. 1 and FIGS. 4-5, a sidewall oxide layer 106 is formed on the sidewall of the first device trench 103.
作为示例，形成所述侧壁氧化层106的方法包括：于所述第一器件沟槽103的内壁形成表面氧化层105，并去除所述第一器件沟槽103底部的所述表面氧化层105形成所述侧壁氧化层106。As an example, the method of forming the sidewall oxide layer 106 includes: forming a surface oxide layer 105 on the inner wall of the first device trench 103, and removing the surface oxide layer 105 at the bottom of the first device trench 103 The sidewall oxide layer 106 is formed.
作为示例，形成所述表面氧化层105之前保留所述第一器件沟槽103的刻蚀掩膜，基于热氧化工艺形成所述表面氧化层105，并基于所述刻蚀掩膜采用干法刻蚀的工艺去除所述第一器件沟槽103底部的所述表面氧化层105。As an example, the etching mask of the first device trench 103 is retained before the formation of the surface oxide layer 105, the surface oxide layer 105 is formed based on a thermal oxidation process, and dry etching is used based on the etching mask. The etching process removes the surface oxide layer 105 at the bottom of the first device trench 103.
具体的，该步骤中，在所述第一器件沟槽103的侧壁形成一侧壁氧化层106，以用于厚度第二器件沟槽107的刻蚀，在一示例中，先在所述第一器件沟槽103的内壁形成表面氧化层105，即在所述第一器件沟槽103的底部和侧壁均形成所述表面氧化层105，在一可选示例中，采用热氧化的工艺形成所述表面氧化层105，其材料包括但不限于氧化硅，在一示例中，所述表面氧化层105的厚度介于0.2微米至0.3微米之间，从而可以有利于后续第二器件沟槽107的形成，且不对器件结构造成损伤，所述表面氧化层105形成后，在一示例中，采用干法刻蚀的工艺去除所述第一器件沟槽103底部的所述表面氧化层105，从而形成所述侧壁氧化层106，可选地，此时保留进行所述第一器件沟槽103形成时所采用的刻蚀掩膜，如在一示例中，可以是前文所提到的所述第一掩膜102，共同用于后续刻蚀。Specifically, in this step, a sidewall oxide layer 106 is formed on the sidewall of the first device trench 103 to be used for the etching of the second device trench 107 with a thickness. A surface oxide layer 105 is formed on the inner wall of the first device trench 103, that is, the surface oxide layer 105 is formed on the bottom and sidewalls of the first device trench 103. In an alternative example, a thermal oxidation process is used. The surface oxide layer 105 is formed, and its material includes but is not limited to silicon oxide. In one example, the thickness of the surface oxide layer 105 is between 0.2 μm and 0.3 μm, which may be beneficial to subsequent second device trenches. 107 is formed without causing damage to the device structure. After the surface oxide layer 105 is formed, in one example, a dry etching process is used to remove the surface oxide layer 105 at the bottom of the first device trench 103, Thus, the sidewall oxide layer 106 is formed. Optionally, at this time, the etching mask used when forming the first device trench 103 is retained. For example, it may be the aforementioned one. The first mask 102 is commonly used for subsequent etching.
如图1中的S4及图6所示，基于所述侧壁氧化层106对所述外延层101进行刻蚀，以形成与所述第一器件沟槽103连通的第二器件沟槽107，且所述第二器件沟槽107的宽度小于所述第一器件沟槽103的宽度。As shown in S4 in FIG. 1 and FIG. 6, the epitaxial layer 101 is etched based on the sidewall oxide layer 106 to form a second device trench 107 communicating with the first device trench 103, Moreover, the width of the second device trench 107 is smaller than the width of the first device trench 103.
如图1中的S5及图7所示，去除所述侧壁氧化层106以显露所述第一器件沟槽103及所述第二器件沟槽107，对应的所述第一器件沟槽103及所述第二器件沟槽107构成栅极沟槽108。As shown in S5 in FIG. 1 and FIG. 7, the sidewall oxide layer 106 is removed to expose the first device trench 103 and the second device trench 107, corresponding to the first device trench 103 And the second device trench 107 constitutes a gate trench 108.
作为示例，去除所述侧壁氧化层106之前还包括于所述第二器件沟槽107的内壁形成牺牲层(图6和图7中均未示出)的步骤，其中，采用湿法刻蚀工艺去除所述牺牲层及所述侧壁氧化层106。As an example, before removing the sidewall oxide layer 106, it further includes a step of forming a sacrificial layer (not shown in FIGS. 6 and 7) on the inner wall of the second device trench 107, wherein wet etching is used The process removes the sacrificial layer and the sidewall oxide layer 106.
具体的，该步骤中形成所述栅极沟槽108，形成的所述栅极沟槽108包括所述第一器件沟槽103及所述第二器件沟槽107，也即形成了类似碗口的上大下小的结构，从而可以有利于后续的自对准工艺的实施，本发明只用一块光刻版可以形成上述具有“碗口”结构的器件的栅极沟槽108，其中，在所述第二器件沟槽107的形成过程中，基于前面形成的侧壁氧化层106直接作为刻蚀掩膜，并可基于所述第一器件沟槽103形成的刻蚀掩膜作为保护，简化工艺，提高材料的利用率，节约成本，所述第二器件沟槽107的形成采用干法刻蚀的工艺，另外，所述第二器件沟槽107形成之后，去除所述侧壁氧化层106，当保留有所述第一器件沟槽103形成的刻蚀掩膜时，如保留所述第一掩膜102时，还同时去除所述第一掩膜102，从而最终得到所述栅极沟槽108。另外，在一示例中，所述第一器件沟槽103的深度小于所述第二器件沟槽107的深度。Specifically, in this step, the gate trench 108 is formed, and the formed gate trench 108 includes the first device trench 103 and the second device trench 107, that is, a similar bowl mouth is formed. The upper and lower structures are small, which can facilitate the implementation of the subsequent self-alignment process. The present invention uses only one photolithography plate to form the gate trench 108 of the device with the “bowl-mouth” structure mentioned above. During the formation of the second device trench 107, the sidewall oxide layer 106 formed previously is directly used as an etching mask, and the etching mask formed based on the first device trench 103 can be used as a protection, simplifying The process improves the utilization of materials and saves costs. The second device trench 107 is formed by a dry etching process. In addition, after the second device trench 107 is formed, the sidewall oxide layer 106 is removed When the etching mask formed by the first device trench 103 is retained, such as when the first mask 102 is retained, the first mask 102 is also removed at the same time, so as to finally obtain the gate trench槽108。 Slot 108. In addition, in an example, the depth of the first device trench 103 is smaller than the depth of the second device trench 107.
在一示例中，当刻蚀形成所述第二器件沟槽107之后，还在所述第二器件沟槽107的侧壁形成一层牺牲层，对刻蚀过程的损伤进行修复，在一示例中，可以是氧化层，如氧化硅层， 可选地，通过热氧化工艺形成所述牺牲层，在一示例中，所述牺牲层的厚度介于500埃至1250埃之间，可以是800埃、1000埃，进而可以同时去除所述牺牲层和位于所述第一器件沟槽103侧壁的侧壁氧化层106，如采用湿法刻蚀工艺进行去除，最终得到类似碗口的上大下小的栅极沟槽108。In an example, after the second device trench 107 is formed by etching, a sacrificial layer is also formed on the sidewall of the second device trench 107 to repair the damage caused by the etching process. In an example Wherein, it may be an oxide layer, such as a silicon oxide layer. Optionally, the sacrificial layer is formed by a thermal oxidation process. In one example, the thickness of the sacrificial layer is between 500 angstroms and 1250 angstroms, which may be 800 angstroms. Angstroms, 1000 Angstroms, and then the sacrificial layer and the sidewall oxide layer 106 on the sidewall of the first device trench 103 can be removed at the same time. Lower a small gate trench 108.
如图1中的S8及图8-10所示，至少于所述第二器件沟槽107的内壁形成栅介质层111，并于所述栅介质层111表面形成栅极层114，所述栅极层114填充所述第二器件沟槽107中。As shown in S8 in Figure 1 and Figures 8-10, a gate dielectric layer 111 is formed at least on the inner wall of the second device trench 107, and a gate layer 114 is formed on the surface of the gate dielectric layer 111. The gate The pole layer 114 fills the second device trench 107.
作为示例，所述栅介质层111还延伸至所述第一器件沟槽103的内壁及所述第一器件沟槽103周围的所述外延层101表面；As an example, the gate dielectric layer 111 also extends to the inner wall of the first device trench 103 and the surface of the epitaxial layer 101 around the first device trench 103;
作为示例，形成所述栅极层114的步骤包括：于所述栅介质层111表面沉积栅极材料层113，并对所述栅极材料层113采用过刻蚀工艺进行回刻，以去除所述第一器件沟槽103内及所述第一器件沟槽103周围的所述外延层101上的所述栅极材料层113，从而形成所述栅极层114。As an example, the step of forming the gate layer 114 includes depositing a gate material layer 113 on the surface of the gate dielectric layer 111, and performing an over-etching process on the gate material layer 113 to remove all the materials. The gate material layer 113 in the first device trench 103 and on the epitaxial layer 101 around the first device trench 103 forms the gate layer 114.
具体的，形成所述栅极沟槽108之后形成所述栅介质层111，其中，所述栅介质层111可以仅形成于所述第二器件沟槽107的内壁上，也可以形成于整个所述栅极沟槽108的内壁上，还可以进一步延伸至所述栅极沟槽108周围的所述外延层101上，优选所述栅介质层111连续的形成在所述栅极沟槽108的内壁上及所述栅极沟槽108周围的所述外延层101上，这里内壁包括侧壁和底部，在一示例中，可以采用高温热氧化工艺形成所述栅介质层111，其厚度范围是150埃至500埃，如可以是200埃、300埃等。Specifically, the gate dielectric layer 111 is formed after the gate trench 108 is formed. The gate dielectric layer 111 may be formed only on the inner wall of the second device trench 107, or may be formed on the entire surface. The inner wall of the gate trench 108 may further extend to the epitaxial layer 101 around the gate trench 108. Preferably, the gate dielectric layer 111 is continuously formed on the gate trench 108 On the inner wall and on the epitaxial layer 101 around the gate trench 108, where the inner wall includes sidewalls and a bottom, in one example, the gate dielectric layer 111 can be formed by a high-temperature thermal oxidation process, and the thickness range is 150 angstroms to 500 angstroms, such as 200 angstroms, 300 angstroms, etc.
具体的，所述栅极层114形成在所述第二器件沟槽107的所述栅介质层111的表面，并填充满所述第二器件沟槽107，所述栅极层114的材料包括但不限于多晶硅，可以通过化学气相沉积的工艺形成所述栅极层114，在一示例中，所述栅介质层111还延伸至所述栅极沟槽108周围的所述外延层101上，所述栅极层114的方法可以是先在所述介质层的表面沉积栅极材料层113，如图9所示，例如可以采用化学气相沉积工艺淀积，在一示例中，形成的栅极材料层113的厚度介于0.1微米至1微米之间，如可以是0.5微米或0.8微米，这里的厚度指的是形成在所述外延层101上方的所述栅极材料层113的厚度，如图9中的s所示。在一示例中，采用干法刻蚀的工艺去掉多余的所述栅极材料层113以形成所述栅极层114，其中，所述栅极层114(如多晶硅)填充深沟槽(所述第二器件沟槽107)，所述栅极层114的上表面与所述第二器件沟槽107的上开口相平齐，该示例中该多晶硅表面与深沟槽上开口齐平，可选地，所述栅极材料层113的干法刻蚀采用过刻蚀基本停在所述第一器件沟槽103的底部，这里过刻蚀是指设定一主刻蚀，在主刻蚀过后进行一后续刻蚀，如可以是增加刻蚀时 间继续采用同样的刻蚀参数进行刻蚀，例如，在一示例中，所述栅介质层111形成在所述外延层101上，采用过刻蚀的工艺对栅极材料层113进行刻蚀，当检测到栅介质层111(如氧化硅)的信号时，通过设置一过刻蚀时间实现刻蚀终止在所述第一器件沟槽103底部的目的，从而形成所述栅极层114，并使所述栅极层114的上表面与所述第二器件沟槽107的上开口相平齐。Specifically, the gate layer 114 is formed on the surface of the gate dielectric layer 111 of the second device trench 107 and fills the second device trench 107. The material of the gate layer 114 includes But not limited to polysilicon, the gate layer 114 may be formed by a chemical vapor deposition process. In one example, the gate dielectric layer 111 also extends to the epitaxial layer 101 around the gate trench 108, The method of the gate layer 114 may be to first deposit a gate material layer 113 on the surface of the dielectric layer, as shown in FIG. 9, for example, it may be deposited by a chemical vapor deposition process. In one example, the formed gate The thickness of the material layer 113 is between 0.1 μm and 1 μm, such as 0.5 μm or 0.8 μm. The thickness here refers to the thickness of the gate material layer 113 formed on the epitaxial layer 101, such as Shown by s in Figure 9. In one example, a dry etching process is used to remove the excess gate material layer 113 to form the gate layer 114, wherein the gate layer 114 (such as polysilicon) fills the deep trench (the The second device trench 107), the upper surface of the gate layer 114 is flush with the upper opening of the second device trench 107. In this example, the polysilicon surface is flush with the opening on the deep trench, optionally Ground, the dry etching of the gate material layer 113 adopts over-etching and basically stops at the bottom of the first device trench 103, where over-etching refers to setting a main etching, after the main etching Perform a subsequent etching. For example, increase the etching time and continue to use the same etching parameters for etching. For example, in one example, the gate dielectric layer 111 is formed on the epitaxial layer 101, and over-etching is used. The process of etching the gate material layer 113, when the signal of the gate dielectric layer 111 (such as silicon oxide) is detected, an over-etching time is set to realize the etching termination at the bottom of the first device trench 103 The purpose is to form the gate layer 114 and make the upper surface of the gate layer 114 flush with the upper opening of the second device trench 107.
如图1中的S9及图11所示，于所述外延层101中形成第二掺杂类型的体区116，所述体区116位于相邻的所述栅极沟槽108之间。As shown in S9 in FIG. 1 and FIG. 11, a body region 116 of the second doping type is formed in the epitaxial layer 101, and the body region 116 is located between the adjacent gate trenches 108.
作为示例，所述体区116的深度不超过所述第二器件沟槽107的深度。As an example, the depth of the body region 116 does not exceed the depth of the second device trench 107.
具体的，该步骤中，在所述外延层101中进行离子注入以形成体区116，其中，具体的，所述第二掺杂类型表示与所述第一掺杂类型相反的掺杂类型，如所述第一掺杂类型为N型，则所述第二掺杂类型为P型，如所述第一掺杂类型为P型，则所述第二掺杂类型为N型，所述体区116的掺杂类型与所述外延层101及所述衬底100的掺杂类型相反，在一示例中，所述体区116的深度小于所述栅极沟槽108的深度，所述体区116底部与所述栅极层114底部之间具有一高度差，也就是说，所述体区116的底部距所述外延层101底部的距离大于所述栅极沟槽108的底部距所述外延层101底部的距离，在本示例中，所述体区116选择为P型轻掺杂。另外，形成所述体区116还包括离子注入后进行高温退火的步骤，其中，在一示例中，根据器件的阈值电压、击穿电压等性能参数需求调整注入剂量，在一示例中，调整注入剂量为5E12/CM^2至1E13/CM^2。Specifically, in this step, ion implantation is performed in the epitaxial layer 101 to form the body region 116, wherein, specifically, the second doping type represents a doping type opposite to the first doping type, If the first doping type is N-type, the second doping type is P-type, and if the first doping type is P-type, the second doping type is N-type, and The doping type of the body region 116 is opposite to the doping type of the epitaxial layer 101 and the substrate 100. In an example, the depth of the body region 116 is smaller than the depth of the gate trench 108, and the There is a height difference between the bottom of the body region 116 and the bottom of the gate layer 114, that is, the distance between the bottom of the body region 116 and the bottom of the epitaxial layer 101 is greater than that of the gate trench 108. The distance from the bottom of the epitaxial layer 101, in this example, the body region 116 is selected to be P-type lightly doped. In addition, forming the body region 116 also includes a step of performing high temperature annealing after ion implantation. In one example, the implantation dose is adjusted according to the threshold voltage, breakdown voltage and other performance parameters of the device. In one example, the implantation is adjusted. The dose is 5E12/CM^2 to 1E13/CM^2.
如图1中的S10及图12-14所示，于所述第一器件沟槽103中填充遮蔽介质层118，并基于所述遮蔽介质层118于所述体区116中形成源区121，所述源区121形成于相邻所述栅极沟槽108之间，即源区121的边缘邻接所述栅极沟槽108的边缘。As shown in S10 in FIG. 1 and FIGS. 12-14, a shielding dielectric layer 118 is filled in the first device trench 103, and a source region 121 is formed in the body region 116 based on the shielding dielectric layer 118, The source region 121 is formed between adjacent gate trenches 108, that is, the edge of the source region 121 is adjacent to the edge of the gate trench 108.
作为示例，形成所述遮蔽介质层118及所述源区121的步骤包括：于所述第一器件沟槽103及所述第一器件沟槽103周围的所述外延层101上形成遮蔽介质材料层117，并基于第二光刻版对所述遮蔽介质材料层117进行图形化以定义出有源区，对所述有源区进行离子注入以形成所述源区121，所述图形化后剩余的填充在所述第一器件沟槽103中的所述遮蔽介质材料层117构成所述遮蔽介质层118。As an example, the step of forming the shielding dielectric layer 118 and the source region 121 includes: forming a shielding dielectric material on the first device trench 103 and the epitaxial layer 101 around the first device trench 103 Layer 117, and patterning the shielding dielectric material layer 117 based on the second photolithography to define an active region, ion implantation is performed on the active region to form the source region 121, after the patterning The remaining shielding dielectric material layer 117 filled in the first device trench 103 constitutes the shielding dielectric layer 118.
作为示例，进行所述离子注入的注入能量介于60Kev至120Kev之间，注入角度介于7度至30度之间。As an example, the implantation energy for performing the ion implantation is between 60Kev and 120Kev, and the implantation angle is between 7 degrees and 30 degrees.
作为示例，所述源区121的深度大于所述第一器件沟槽103的深度。As an example, the depth of the source region 121 is greater than the depth of the first device trench 103.
具体的，所述体区116形成之后，于所述体区116中形成器件的源区121，即制备沟槽 型场效应晶体管的源极，其中，所述源区121形成于相邻所述栅极沟槽108之间，源区121的边缘邻接所述栅极沟槽108的边缘，在一示例中，形成所述源区121的离子注入对所述体区116进行，所述源区121形成在所述体区116中，且所述源区121的上表面与所述体区116的上表面平齐。在一可选示例中，进行所述离子注入的注入能量介于60Kev至120Kev之间，例如可以是70Kev、80Kev或者100Kev等，注入角度介于7度至30度之间，例如可以是10度或20度或25度，从而可以有利于所述源区的形成，上述角度的设计，有利于在进行离子注入后，经过后续的激活，离子扩散到遮蔽介质层的下方形成所述源区121。另外，在一示例中，所述源区121的深度大于所述第一器件沟槽103的深度，有利于防止器件的源区没接到沟道处导致器件无法导通或导通电阻比较大的问题，例如，源区121的深度大于所述第一器件沟槽103的深度大出的尺寸，即二者重叠部分的高度可以是0.08微米-0.12微米，可以是0.1微米。Specifically, after the body region 116 is formed, the source region 121 of the device is formed in the body region 116, that is, the source electrode of the trench field effect transistor is prepared, wherein the source region 121 is formed in the adjacent Between the gate trenches 108, the edge of the source region 121 is adjacent to the edge of the gate trench 108. In one example, ion implantation to form the source region 121 is performed on the body region 116. 121 is formed in the body region 116, and the upper surface of the source region 121 is flush with the upper surface of the body region 116. In an optional example, the implantation energy for performing the ion implantation is between 60Kev and 120Kev, such as 70Kev, 80Kev, or 100Kev, etc., and the implantation angle is between 7 degrees and 30 degrees, for example, 10 degrees. Or 20 degrees or 25 degrees, which may facilitate the formation of the source region. The above-mentioned angle design is beneficial to the subsequent activation after ion implantation, and the ions diffuse below the shielding dielectric layer to form the source region 121 . In addition, in an example, the depth of the source region 121 is greater than the depth of the first device trench 103, which is beneficial to prevent the source region of the device from not being connected to the channel, causing the device to fail to turn on or to have a relatively large on-resistance. For example, the depth of the source region 121 is greater than the depth of the first device trench 103, that is, the height of the overlapping portion of the two can be 0.08 μm-0.12 μm, or 0.1 μm.
在一示例中，提供一种所述源区121的形成方式，在所述体区116形成之后，先在器件的整个表面形成一层遮蔽介质材料层117，可以采用化学气相沉积的工艺形成，在一示例中，所述遮蔽介质材料层117的厚度介于0.5微米至1微米之间，可以是0.6微米或0.8微米等，这里的厚度指的是所述遮蔽介质层118形成在所述外延层101上方的厚度，如图12中的m所示。接着，基于第二光刻版对所述遮蔽介质材料层117进行图形化以定义出有源区，参见图13所示。所述有源区显露出需要形成所述源区121的位置，去掉了所述外延层101上方对应的遮蔽介质材料层117，同时形成了填充在所述第一器件沟槽103中的所述遮蔽介质层118，接着再在所述遮蔽介质层118的遮挡下进行离子注入形成所述源区121，如图14所示。在一示例中，在进行离子注入后还包括进行退火从而形成源区121的步骤，本示例中，形成浓掺杂(例如，n+)的器件源区121。In one example, a method for forming the source region 121 is provided. After the body region 116 is formed, a layer of shielding dielectric material 117 is formed on the entire surface of the device, which can be formed by a chemical vapor deposition process. In an example, the thickness of the shielding dielectric material layer 117 is between 0.5 micrometers and 1 micrometer, and can be 0.6 micrometers or 0.8 micrometers. The thickness here means that the shielding dielectric layer 118 is formed on the epitaxial layer. The thickness above the layer 101 is shown as m in FIG. 12. Next, the masking dielectric material layer 117 is patterned based on the second photolithography to define the active area, as shown in FIG. 13. The active region reveals the position where the source region 121 needs to be formed, the corresponding shielding dielectric material layer 117 above the epitaxial layer 101 is removed, and the first device trench 103 filled in the The shielding dielectric layer 118 is then subjected to ion implantation under the shielding of the shielding dielectric layer 118 to form the source region 121, as shown in FIG. 14. In one example, after ion implantation, annealing is further included to form the source region 121. In this example, a heavily doped (for example, n+) device source region 121 is formed.
如图1中的S11及图15所示，基于所述遮蔽介质层118于所述外延层101中形成自对准的源极接触孔122，所述源极接触孔122贯穿所述源区121至所述体区116，所述源极接触孔122的底部显露所述体区116。As shown in S11 in FIG. 1 and FIG. 15, a self-aligned source contact hole 122 is formed in the epitaxial layer 101 based on the shielding dielectric layer 118, and the source contact hole 122 penetrates the source region 121 To the body region 116, the bottom of the source contact hole 122 exposes the body region 116.
作为示例，所述源极接触孔122的开口边缘邻接对应的所述源区121的边缘，即所述源极接触孔122的宽度等于相邻的两个所述第一器件沟槽103之间的距离，所述接触孔122的侧壁为倾斜侧壁，所述源极接触孔122的截面形状包括倒梯形。As an example, the opening edge of the source contact hole 122 is adjacent to the edge of the corresponding source region 121, that is, the width of the source contact hole 122 is equal to that between two adjacent first device trenches 103 The sidewall of the contact hole 122 is an inclined sidewall, and the cross-sectional shape of the source contact hole 122 includes an inverted trapezoid.
具体的，如图15所示，形成本发明沟槽型场效应晶体管的源极接触孔122，该步骤中，形成了上大下小的所述栅极沟槽108，并在所述第一器件沟槽103中形成了遮蔽介质层118，从而可以以所述遮蔽介质层118作为掩膜对所述外延层101进行刻蚀，在有源区形成自对准 的源极接触孔122，从而可以使得器件的横向间距可以降低，如降低到1微米以下，增加了器件元胞的密度，降低了器件的源漏极导通电阻，本发明中，可以基于同一遮蔽介质层118同时形成源区121和源极接触孔122，简化工艺，节约成本，如图15所示，形成所述第一器件沟槽103、所述源极接触孔102交替排列设置的结构，且第一器件沟槽103与源极接触孔102紧密邻接，如第一个所述第一器件沟槽103的右侧边缘邻接第一个所述源极接触孔102的左侧边缘，第一个所述源极接触孔102的右侧边缘邻接第二个所述第一器件沟槽103的左侧边缘，以此类推。可选地，所述源极接触孔122的纵截面形状可以是倒梯形，在一可选示例中，所述源极接触孔122贯穿所述源区121延伸至所述体区116中，从而可以提高器件的电学稳定性。Specifically, as shown in FIG. 15, the source contact hole 122 of the trench field effect transistor of the present invention is formed. A shielding dielectric layer 118 is formed in the device trench 103, so that the epitaxial layer 101 can be etched using the shielding dielectric layer 118 as a mask to form a self-aligned source contact hole 122 in the active area, thereby The lateral spacing of the device can be reduced, such as reduced to less than 1 micron, which increases the density of the device cell and reduces the on-resistance of the source and drain of the device. In the present invention, the source region can be formed at the same time based on the same shielding dielectric layer 118. 121 and the source contact hole 122 to simplify the process and save cost. As shown in FIG. 15, a structure in which the first device trench 103 and the source contact hole 102 are arranged alternately is formed, and the first device trench 103 It is closely adjacent to the source contact hole 102. For example, the right edge of the first device trench 103 is adjacent to the left edge of the first source contact hole 102, and the first source contact hole The right edge of 102 is adjacent to the left edge of the second first device trench 103, and so on. Optionally, the longitudinal cross-sectional shape of the source contact hole 122 may be an inverted trapezoid. In an optional example, the source contact hole 122 extends through the source region 121 into the body region 116, thereby The electrical stability of the device can be improved.
如图1中的S12及图17所示，至少于所述源极接触孔122中填充导电材料层以形成源极电极结构124，并于所述衬底100远离所述外延层101的一侧形成与所述衬底100电连接的下电极结构。As shown in S12 in FIG. 1 and FIG. 17, at least a conductive material layer is filled in the source contact hole 122 to form a source electrode structure 124, and is located on the side of the substrate 100 away from the epitaxial layer 101 A lower electrode structure electrically connected to the substrate 100 is formed.
具体的，形成所述源极接触孔122后，在其中进行导电材料层的填充，从而形成所述源极电极，以将所述源区121及所述体区116电性引出，在一示例中，所述源极接触孔122中填充的所述导电材料层还相连接，以实现源极之间的共同连接。另外，在所述衬底100的另外一面形成下电极结构，从而作为器件的漏极引出，其中，所述导电材料层的材料可以是多晶硅或者金属，但并不以此为限。Specifically, after the source contact hole 122 is formed, a conductive material layer is filled therein to form the source electrode to electrically lead out the source region 121 and the body region 116, as an example In this case, the conductive material layer filled in the source contact hole 122 is also connected to realize a common connection between the sources. In addition, a lower electrode structure is formed on the other side of the substrate 100 to serve as the drain of the device. The material of the conductive material layer may be polysilicon or metal, but it is not limited to this.
参见图3-17所示，作为示例，所述沟槽型场效应晶体管结构的制备方法还包括制备引出栅结构的步骤，且所述外延层101中还定义有终端区，其中，形成所述栅极沟槽108的同时还于所述终端区中制备引出栅沟槽110，所述引出栅沟槽110包括第一引出沟槽104及与其上下连通的第二引出沟槽109，且形成所述第一器件沟槽103的同时形成所述第一引出沟槽104，形成所述第二器件沟槽107的同时形成所述第二引出沟槽109，形成所述栅介质层111的同时于所述第二引出沟槽109内壁形成引出栅介质层112，形成所述栅极层114的同时于所述第二引出沟槽109中形成引出栅极层115，形成所述遮蔽介质层118的同时于所述第一引出沟槽104中形成遮蔽引出介质层119，以制备所述引出栅结构。Referring to FIGS. 3-17, as an example, the method for preparing the trench field effect transistor structure further includes a step of preparing a gate structure, and the epitaxial layer 101 also defines a terminal region, wherein the formation of the At the same time as the gate trench 108, an extraction gate trench 110 is also prepared in the terminal region. The extraction gate trench 110 includes a first extraction trench 104 and a second extraction trench 109 connected up and down, and formed The first device trench 103 is formed at the same time as the first extraction trench 104, the second device trench 107 is formed at the same time as the second extension trench 109 is formed, and the gate dielectric layer 111 is formed at the same time An extraction gate dielectric layer 112 is formed on the inner wall of the second extraction trench 109. When the gate layer 114 is formed, an extraction gate layer 115 is formed in the second extraction trench 109 to form the shielding dielectric layer 118. At the same time, a shielding extraction dielectric layer 119 is formed in the first extraction trench 104 to prepare the extraction gate structure.
作为示例，如图15所示，形成所述遮蔽介质层118及所述遮蔽引出介质层119的同时还至少在所述遮蔽引出介质层119上形成中间介质层120。作为示例，如图16所示，形成所述源极接触孔122之后还包括步骤：于所述引出栅极层115上基于第三光刻版形成显露所述引出栅极层115的栅极接触孔123，所述栅极接触孔123贯穿所述中间介质层120及所述遮蔽引出介质层119。As an example, as shown in FIG. 15, while forming the shielding medium layer 118 and the shielding and drawing-out dielectric layer 119, at least an intermediate dielectric layer 120 is formed on the shielding and drawing-out medium layer 119. As an example, as shown in FIG. 16, after forming the source contact hole 122, the method further includes the step of forming a gate contact that exposes the extraction gate layer 115 on the extraction gate layer 115 based on a third photolithography. A hole 123, the gate contact hole 123 penetrates the intermediate dielectric layer 120 and the shielding and drawing dielectric layer 119.
具体的，参见图3所示，在一示例中，还在所述外延层101中制备所述引出栅沟槽110，在一可选示例中，所述外延层101对应的区域预先划分为器件区B和终端区A，其中，在所述器件区B制备所述栅极沟槽108，在所述终端区A制备所述引出沟槽，二者可以基于同一工艺及掩膜制备，即在一示例中，在所述沟第一掩膜102上形成这两种沟槽的图案，再基于该图案进行刻蚀，也就是说，基于所述第一掩膜102形成所述第一器件沟槽103时，也形成了所述第一引出沟槽104，另外，形成侧壁氧化层106时还同时形成在了所述第一引出沟槽104的侧壁上，进而可以基于其形成所述第二引出沟槽109，相关描述参见所述栅极沟槽108的制备。Specifically, referring to FIG. 3, in an example, the extraction gate trench 110 is also prepared in the epitaxial layer 101. In an optional example, the area corresponding to the epitaxial layer 101 is pre-divided into devices Region B and terminal region A, wherein the gate trench 108 is prepared in the device region B, and the extraction trench is prepared in the terminal region A. Both can be prepared based on the same process and mask, that is, In an example, these two trench patterns are formed on the trench first mask 102, and then etching is performed based on the patterns, that is, the first device trench is formed based on the first mask 102. When the groove 103 is formed, the first lead-out trench 104 is also formed. In addition, when the sidewall oxide layer 106 is formed, it is also formed on the sidewall of the first lead-out trench 104, so that the first lead-out trench 104 can be formed based on it. For the second extraction trench 109, refer to the preparation of the gate trench 108 for related description.
进一步，参见图8所示，形成所述栅介质层111的同时于所述引出沟槽的底部及侧壁形成引出栅介质层112，参见图9所示，形成所述栅极层114采用的栅极材料层113同时形成在了所述引出栅沟槽110中，以制备引出栅极层115，相关制备过程参见对栅极层114的描述，在此不再赘述。另外，形成所述遮蔽介质层118时，同时在所述第一引出沟槽104中制备形成了所述遮蔽引出介质层119以及所述中间介质层120，在一示例中，采用所述第二光刻版进行刻蚀时，去掉了有源区对应的所述遮蔽介质材料层117，从而在核心区的所述第一器件沟槽103中形成了所述遮蔽介质层118，同时保留了终端区的遮蔽介质材料层117，填充在所述第一引出沟槽104中的材料层形成了所述遮蔽引出介质层119，位于所述终端区的所述外延层101之上的所述遮蔽材料层形成了所述中间介质层120，另外，需要说明的，本领域技术人员可以理解的，器件区B和终端区A界面范围内的遮蔽介质层118的刻蚀是可以依据实际选择的，如图13所述，遮蔽材料层的去除停留在了交界范围内最外侧的栅极沟槽108上方。Further, referring to FIG. 8, an extraction gate dielectric layer 112 is formed on the bottom and sidewalls of the extraction trench while the gate dielectric layer 111 is formed. As shown in FIG. 9, the gate layer 114 is formed by The gate material layer 113 is simultaneously formed in the lead-out gate trench 110 to prepare the lead-out gate layer 115. For the relevant preparation process, please refer to the description of the gate layer 114, which will not be repeated here. In addition, when the shielding dielectric layer 118 is formed, the shielding extraction dielectric layer 119 and the intermediate dielectric layer 120 are simultaneously prepared and formed in the first extraction trench 104. In one example, the second When the photolithography plate is etched, the shielding dielectric material layer 117 corresponding to the active area is removed, so that the shielding dielectric layer 118 is formed in the first device trench 103 in the core area while retaining the terminal The shielding dielectric material layer 117 in the terminal region, the material layer filled in the first extraction trench 104 forms the shielding extraction dielectric layer 119, and the shielding material located on the epitaxial layer 101 in the terminal region The layer forms the intermediate dielectric layer 120. In addition, it should be noted that those skilled in the art can understand that the etching of the shielding dielectric layer 118 in the interface range of the device region B and the terminal region A can be selected according to actual conditions, such as As shown in FIG. 13, the removal of the shielding material layer stays above the outermost gate trench 108 in the boundary range.
作为示例，如图17所示，所述导电材料层还填充于所述栅极接触孔123中并延伸至所述栅极接触孔123周围的所述中间介质层120上以及延伸至所述源极接触孔122周围的所述遮蔽介质层118上，其中，所述制备方法还包括基于第四光刻版对所述导电材料层进行图形化以形成栅极电极结构125以及所述源极电极结构124的步骤。As an example, as shown in FIG. 17, the conductive material layer is also filled in the gate contact hole 123 and extends to the intermediate dielectric layer 120 around the gate contact hole 123 and extends to the source On the shielding dielectric layer 118 around the electrode contact hole 122, wherein the preparation method further includes patterning the conductive material layer based on a fourth photolithography plate to form a gate electrode structure 125 and the source electrode Structure 124 steps.
具体的，在一示例中，还包括基于第三光刻版制备栅极接触孔123的步骤，其中，所述栅极接触孔123的底部可以与第一引出沟槽104底部平齐，刚刚显露引出栅极层115，也可以是延伸至所述引出栅极层115中。另外，如图16所示，在所述终端区还可以制备终端接触孔，如图中终端区栅极接触孔旁边所制备的通孔，所述终端接触孔延伸至所述外延层中，用作终端接衬底时的连接通孔。另外，参见图17所示，在一示例中，采用在所述核心区及所述终端区上沉积整片导电材料层的方式形成所述源极电极结构124和所述栅极电极结构125， 当沉积整片导电材料层，再基于所述第四光刻版进行刻蚀，定义出相隔离的所述源极电极结构124和所述栅极电极结构125，在一示例中，所述导电材料层的厚度介于0.8微米-2微米之间，可以是1微米或1.5微米等，这里的厚度是指所述导电材料层形成在所述外延层101上的厚度，如图17中的n所示。Specifically, in an example, it further includes the step of preparing a gate contact hole 123 based on a third photolithography, wherein the bottom of the gate contact hole 123 may be flush with the bottom of the first extraction trench 104, which has just been revealed The lead-out gate layer 115 may also extend into the lead-out gate layer 115. In addition, as shown in FIG. 16, terminal contact holes can also be prepared in the terminal area, such as the through hole prepared next to the gate contact hole in the terminal area, and the terminal contact hole extends into the epitaxial layer. Used as a connection through hole when the terminal is connected to the substrate. In addition, referring to FIG. 17, in an example, the source electrode structure 124 and the gate electrode structure 125 are formed by depositing a whole piece of conductive material layer on the core region and the terminal region. When the entire conductive material layer is deposited, and then etched based on the fourth photolithography, the source electrode structure 124 and the gate electrode structure 125 are defined to be separated. In one example, the conductive material The thickness of the material layer is between 0.8 μm and 2 μm, and can be 1 μm or 1.5 μm, etc. The thickness here refers to the thickness of the conductive material layer formed on the epitaxial layer 101, as shown in n in FIG. 17 Shown.
实施例二：Embodiment two:
如图17所示，并参见图1-16，本发明还提供一种沟槽型场效应晶体管结构，其中，所述场效应晶体管结构优选采用本发明的沟槽型场效应晶体管的制备方法制备得到，所述沟槽型场效应晶体管结构包括：As shown in FIG. 17 and referring to FIGS. 1-16, the present invention also provides a trench field effect transistor structure, wherein the field effect transistor structure is preferably prepared by the trench field effect transistor manufacturing method of the present invention Obtained, the trench field effect transistor structure includes:
第一掺杂类型的衬底100；A substrate 100 of the first doping type;
所述第一掺杂类型的外延层101，所述外延层101形成于所述衬底100上，所述外延层101中形成有若干个栅极沟槽108，每个所述栅极沟槽108均包括上下连通设置的第一器件沟槽103及第二器件沟槽107，所述第二器件沟槽107的宽度小于所述第一器件沟槽103的宽度；The epitaxial layer 101 of the first doping type is formed on the substrate 100, and a plurality of gate trenches 108 are formed in the epitaxial layer 101, and each of the gate trenches Each 108 includes a first device trench 103 and a second device trench 107 connected up and down, and the width of the second device trench 107 is smaller than the width of the first device trench 103;
栅极氧化层，形成于所述第二器件沟槽107的内壁上；A gate oxide layer formed on the inner wall of the second device trench 107;
栅极层114，形成于所述栅极氧化层的表面，所述栅极层114填充所述第二器件沟槽107；The gate layer 114 is formed on the surface of the gate oxide layer, and the gate layer 114 fills the second device trench 107;
遮蔽介质层118，填充于所述第一器件沟槽103中；The shielding dielectric layer 118 is filled in the first device trench 103;
第二掺杂类型的体区116，形成于相邻所述栅极沟槽108之间的所述外延层101中；The body region 116 of the second doping type is formed in the epitaxial layer 101 between adjacent gate trenches 108;
所述第一掺杂类型的源区121，形成于相邻所述栅极沟槽108之间的所述体区116中并与所述栅极沟槽108相接触，所述源区121中形成有贯穿所述源区121并显露所述体区116的源极接触孔122；The source region 121 of the first doping type is formed in the body region 116 between adjacent gate trenches 108 and is in contact with the gate trench 108, in the source region 121 A source contact hole 122 that penetrates the source region 121 and exposes the body region 116 is formed;
源极电极结构124，至少填充于所述源极接触孔122中；以及The source electrode structure 124 is filled at least in the source contact hole 122; and
下电极结构，形成于所述衬底100远离所述外延层101的一侧并与所述衬底100电连接。The bottom electrode structure is formed on the side of the substrate 100 away from the epitaxial layer 101 and is electrically connected to the substrate 100.
具体的，所述第一掺杂类型(即第一导电类型)可以是P型掺杂，也可以是N型掺杂，可以为采用离子注入工艺在衬底100中注入第一掺杂类型(P型或N型)的离子而形成的衬底100，以实际器件需求设定，在本示例中，选择为N型掺杂衬底100，另外，在一示例中，可以为重掺杂衬底100，如可以是在所述衬底100中掺杂的第一掺杂类型离子的浓度大于等于1×10 16/cm 3。需要说明的，所述衬底100可以为硅衬底100、锗硅衬底100、碳化硅衬底100等，在本示例中，所述衬底100选用为N++型掺杂的硅衬底100。其中，第一掺杂类型与后续提到的第二掺杂类型(即第二导电类型)为相反的掺杂类型，当所述第一掺杂类型(第一导电类型)半导体为N型半导体、第二掺杂类型(第二导电类型)半导体为P型半导体时， 本发明的沟槽MOSFET器件为N型器件；反之，本发明沟槽MOSFET器件为P型器件。 Specifically, the first doping type (ie, the first conductivity type) may be P-type doping or N-type doping, and may be implanting the first doping type ( The substrate 100 formed by ions of P-type or N-type) is set according to actual device requirements. In this example, the N-type doped substrate 100 is selected. In addition, in one example, it may be a heavily doped substrate. The bottom 100, for example, may be that the concentration of the first doping type ions doped in the substrate 100 is greater than or equal to 1×10 16 /cm 3 . It should be noted that the substrate 100 may be a silicon substrate 100, a silicon germanium substrate 100, a silicon carbide substrate 100, etc. In this example, the substrate 100 is selected as an N++ type doped silicon substrate 100 . Wherein, the first doping type and the second doping type (ie, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (first conductivity type) semiconductor is an N-type semiconductor When the second doping type (second conductivity type) semiconductor is a P-type semiconductor, the trench MOSFET device of the present invention is an N-type device; conversely, the trench MOSFET device of the present invention is a P-type device.
具体的，所述外延层101的掺杂类型与所述衬底100的掺杂类型一致，在一示例中，所述外延层101的掺杂浓度低于所述衬底100的掺杂浓度，其中，可以先采用外延工艺在所述第一掺杂类型的所述衬底100的上表面形成本征外延层101，然后再通过离子注入工艺在所述本征外延层101内注入第一掺杂类型的离子以形成所述第一掺杂类型的外延层101；在另一示例中，还可以采用外延工艺直接在所述第一掺杂类型的衬底100的上表面外延形成所述第一掺杂类型的外延层101。本示例中，所述外延层101选用为N-型单晶硅外延层101。Specifically, the doping type of the epitaxial layer 101 is consistent with the doping type of the substrate 100. In an example, the doping concentration of the epitaxial layer 101 is lower than the doping concentration of the substrate 100, Wherein, the intrinsic epitaxial layer 101 may be formed on the upper surface of the substrate 100 of the first doping type by an epitaxial process, and then the first dopant is implanted into the intrinsic epitaxial layer 101 through an ion implantation process. Doped ions to form the epitaxial layer 101 of the first doping type; in another example, an epitaxial process can also be used to directly epitaxially form the second doping type on the upper surface of the substrate 100 of the first doping type. An epitaxial layer 101 of doping type. In this example, the epitaxial layer 101 is selected as an N-type monocrystalline silicon epitaxial layer 101.
具体的，在一示例中，所述第一器件沟槽103的宽度可以是0.3微米之间，所述第一器件沟槽103的深度可以是0.25微米，这里宽度指的是横向尺寸，如图3中的w，深度指的是所述第一器件沟槽103埋入所述外延层101中的尺寸，如图3中的d所示。另外，所述第一器件沟槽103的数量及布局可以依据实际需求进行选择。需要说明的，本发明形成的所述栅极沟槽108，包括所述第一器件沟槽103及所述第二器件沟槽107，也即形成了类似碗口的上大下小的结构，从而可以有利于后续的自对准工艺的实施。Specifically, in an example, the width of the first device trench 103 may be between 0.3 micrometers, and the depth of the first device trench 103 may be 0.25 micrometers, where the width refers to the lateral dimension, as shown in FIG. The w in 3, depth refers to the size of the first device trench 103 buried in the epitaxial layer 101, as shown in d in FIG. 3. In addition, the number and layout of the first device trenches 103 can be selected according to actual requirements. It should be noted that the gate trench 108 formed in the present invention includes the first device trench 103 and the second device trench 107, that is, it forms a structure similar to a bowl with a large top and a small bottom. This can facilitate the implementation of the subsequent self-alignment process.
具体的，对于所述栅介质层111，所述栅介质层111可以仅形成于所述第二器件沟槽107的内壁上，也可以形成于整个所述栅极沟槽108的内壁上，还可以进一步延伸至所述栅极沟槽108周围的所述外延层101上，优选所述栅介质层111连续的形成在所述栅极沟槽108的内壁上及所述栅极沟槽108周围的所述外延层101上，这里内壁包括侧壁和底部，其厚度可以是150埃-500埃，如可以是200埃、300埃等。另外，所述栅极层114形成在所述第二器件沟槽107的所述栅介质层111的表面，并填充满所述第二器件沟槽107，所述栅极层114(如多晶硅)填充深沟槽(所述第二器件沟槽107)，所述栅极层114的上表面与所述第二器件沟槽107的上开口相平齐，该示例中该多晶硅表面与深沟槽上开口齐平，所述栅极层114的材料包括但不限于多晶硅。Specifically, for the gate dielectric layer 111, the gate dielectric layer 111 may be formed only on the inner wall of the second device trench 107, or may be formed on the entire inner wall of the gate trench 108, and It can be further extended to the epitaxial layer 101 around the gate trench 108, preferably the gate dielectric layer 111 is continuously formed on the inner wall of the gate trench 108 and around the gate trench 108 On the epitaxial layer 101, where the inner wall includes the side wall and the bottom, the thickness can be 150-500 angstroms, such as 200 angstroms, 300 angstroms, and so on. In addition, the gate layer 114 is formed on the surface of the gate dielectric layer 111 of the second device trench 107 and fills the second device trench 107. The gate layer 114 (such as polysilicon) Fill the deep trench (the second device trench 107). The upper surface of the gate layer 114 is flush with the upper opening of the second device trench 107. In this example, the polysilicon surface is flush with the deep trench. The upper opening is flush, and the material of the gate layer 114 includes but is not limited to polysilicon.
作为示例，所述体区116的深度不超过所述栅极沟槽108的深度。As an example, the depth of the body region 116 does not exceed the depth of the gate trench 108.
作为示例，所述源区121的深度大于所述第一器件沟槽103的深度。As an example, the depth of the source region 121 is greater than the depth of the first device trench 103.
具体的，在所述外延层101中进行离子注入以形成体区116，其中，具体的，所述第二掺杂类型表示与所述第一掺杂类型相反的掺杂类型，如所述第一掺杂类型为N型，则所述第二掺杂类型为P型，如所述第一掺杂类型为P型，则所述第二掺杂类型为N型，所述体区116的掺杂类型与所述外延层101及所述衬底100的掺杂类型相反，在一示例中，所述体区116的深度小于所述栅极沟槽108的深度，所述体区116底部与所述栅极层114底部之间具有一高度差，也就是说，所述体区116的底部距所述外延层101底部的距离大于所述栅极沟槽108 的底部距所述外延层101底部的距离，在本示例中，所述体区116选择为P型轻掺杂。另外，所述体区116形成之后，于所述体区116中形成器件的源区121，即制备沟槽型场效应晶体管的源极，其中，所述源区121形成于相邻所述栅极沟槽108之间并与所述栅极沟槽108相接触，在一示例中，形成所述源区121的离子注入对所述体区116进行，所述源区121形成在所述体区116中，且所述源区121的上表面与所述体区116的上表面平齐，本示例中，形成浓掺杂(例如，n+)的器件源区121。Specifically, ion implantation is performed in the epitaxial layer 101 to form the body region 116, wherein, specifically, the second doping type represents a doping type opposite to the first doping type, as in the first doping type. If the first doping type is N-type, the second doping type is P-type. If the first doping type is P-type, the second doping type is N-type. The doping type is opposite to the doping type of the epitaxial layer 101 and the substrate 100. In an example, the depth of the body region 116 is smaller than the depth of the gate trench 108, and the bottom of the body region 116 There is a height difference between the bottom of the gate layer 114 and the bottom of the gate layer 114, that is, the distance between the bottom of the body region 116 and the bottom of the epitaxial layer 101 is greater than that between the bottom of the gate trench 108 and the epitaxial layer. The distance from the bottom of 101, in this example, the body region 116 is selected to be P-type lightly doped. In addition, after the body region 116 is formed, the source region 121 of the device is formed in the body region 116, that is, the source electrode of the trench field effect transistor is prepared, wherein the source region 121 is formed adjacent to the gate. Between the electrode trenches 108 and in contact with the gate trench 108. In one example, ion implantation to form the source region 121 is performed on the body region 116, and the source region 121 is formed in the body region. In the region 116, and the upper surface of the source region 121 is flush with the upper surface of the body region 116, in this example, a heavily doped (for example, n+) device source region 121 is formed.
作为示例，所述源极接触孔122的开口边缘邻接对应的所述源区121的边缘，即所述源极接触孔122的宽度等于相邻的两个所述第一器件沟槽103之间的距离，所述接触孔122的侧壁为倾斜侧壁，所述源极接触孔122的截面形状包括倒梯形。As an example, the opening edge of the source contact hole 122 is adjacent to the edge of the corresponding source region 121, that is, the width of the source contact hole 122 is equal to that between two adjacent first device trenches 103 The sidewall of the contact hole 122 is an inclined sidewall, and the cross-sectional shape of the source contact hole 122 includes an inverted trapezoid.
形成了上大下小的所述栅极沟槽108，并在所述第一器件沟槽103中形成了遮蔽介质层118，从而可以以所述遮蔽介质层118作为掩膜对所述外延层101进行刻蚀，从而可以使得器件的横向间距可以降低，如降低到1微米以下，增加了器件元胞的密度，降低了器件的源漏极导通电阻，在一示例中，所述源极接触孔122的开口和对应的所述源区121的边缘相接触，即所述源极接触孔122的开口的大小即为相邻所述第一器件沟槽103之间的距离，如图15所示，形成所述第一器件沟槽103、所述源极接触孔102交替排列设置的结构，且第一器件沟槽103与源极接触孔102紧密邻接，如第一个所述第一器件沟槽103的右侧边缘邻接第一个所述源极接触孔102的左侧边缘，第一个所述源极接触孔102的右侧边缘邻接第二个所述第一器件沟槽103的左侧边缘，以此类推，可选地，所述源极接触孔122的纵截面形状可以是倒梯形，在一可选示例中，所述源极接触孔122贯穿所述源区121延伸至所述体区116中，从而可以提高器件的电学稳定性。The gate trench 108 is formed with a large upper and a lower gate, and a shielding dielectric layer 118 is formed in the first device trench 103, so that the shielding dielectric layer 118 can be used as a mask for the epitaxial layer 101 is etched, so that the lateral spacing of the device can be reduced, for example, reduced to less than 1 micron, which increases the density of the device cell and reduces the on-resistance of the source and drain of the device. In one example, the source The opening of the contact hole 122 is in contact with the edge of the corresponding source region 121, that is, the size of the opening of the source contact hole 122 is the distance between the adjacent first device trenches 103, as shown in FIG. 15 As shown, a structure in which the first device trench 103 and the source contact hole 102 are arranged alternately is formed, and the first device trench 103 is closely adjacent to the source contact hole 102, as described in the first one. The right edge of the device trench 103 is adjacent to the left edge of the first source contact hole 102, and the right edge of the first source contact hole 102 is adjacent to the second first device trench 103 Optionally, the longitudinal cross-sectional shape of the source contact hole 122 may be an inverted trapezoid. In an optional example, the source contact hole 122 extends through the source region 121 Into the body region 116, thereby improving the electrical stability of the device.
具体的，形成所述源极接触孔122后，在其中进行导电材料层的填充，从而形成所述源极电极，以将所述源区121及所述体区116电性引出，在一示例中，所述源极接触孔122中填充的所述导电材料层还相连接，以实现源极之间的共同连接。另外，在所述衬底100的另外一面形成下电极结构，从而作为器件的漏极引出，其中，所述导电材料层的材料可以是多晶硅或者金属，但并不以此为限。Specifically, after the source contact hole 122 is formed, a conductive material layer is filled therein to form the source electrode to electrically lead out the source region 121 and the body region 116, as an example In this case, the conductive material layer filled in the source contact hole 122 is also connected to realize a common connection between the sources. In addition, a lower electrode structure is formed on the other side of the substrate 100 to serve as the drain of the device. The material of the conductive material layer may be polysilicon or metal, but it is not limited to this.
作为示例，所述沟槽型场效应晶体管结构还包括引出栅结构，且所述外延层101中定义有终端区，其中，所述引出栅结构形成于所述终端区中，所述引出栅结构包括：引出栅沟槽110，所述引出栅沟槽110包括第一引出沟槽104及与其上下连通的第二引出沟槽109；形成于所述第二引出沟槽109的内壁的引出栅介质层112；形成于所述引出栅介质层112表面的引出栅极层115，所述引出栅极层115填充所述第二引出沟槽109；以及填充于所述第一引出 沟槽104中的遮蔽引出介质层119。As an example, the trench field effect transistor structure further includes an extraction gate structure, and a terminal region is defined in the epitaxial layer 101, wherein the extraction gate structure is formed in the terminal region, and the extraction gate structure It includes: a lead-out gate trench 110, which includes a first lead-out trench 104 and a second lead-out trench 109 connected up and down; a lead-out gate dielectric formed on the inner wall of the second lead-out trench 109 Layer 112; an extraction gate layer 115 formed on the surface of the extraction gate dielectric layer 112, the extraction gate layer 115 filling the second extraction trench 109; and filling in the first extraction trench 104 The dielectric layer 119 is drawn out by shielding.
作为示例，所述遮蔽引出介质层119上还形成有中间介质层120，所述沟槽型场效应晶体管结构还包括栅极接触孔123及栅极电极结构125，其中，所述栅极接触孔123依次贯穿所述中间介质层120、所述遮蔽引出介质层119至所述引出栅极层115，并显露所述引出栅极层115，所述栅极电极结构125至少填充于所述栅极接触孔123中。As an example, an intermediate dielectric layer 120 is further formed on the shielding extraction dielectric layer 119, and the trench field effect transistor structure further includes a gate contact hole 123 and a gate electrode structure 125, wherein the gate contact hole 123 successively penetrates the intermediate dielectric layer 120, the shielding extraction dielectric layer 119 to the extraction gate layer 115, and reveals the extraction gate layer 115, and the gate electrode structure 125 at least fills the gate In the contact hole 123.
具体的，参见图3所示，在一示例中，还在所述外延层101中制备所述引出栅沟槽110，在一可选示例中，所述外延层101对应的区域预先划分为器件区B和终端区A，其中，在所述器件区制备所述栅极沟槽108，在所述终端区制备所述引出沟槽，其中，所述第一引出沟槽104与所述第一器件沟槽103，所述第二引出沟槽109与所述第二器件沟槽107，所述栅介质层111与所述引出栅介质层112，所述栅极层114与所述引出栅极层115，所述遮蔽介质层118与所述遮蔽引出介质层119，均可以是基于同一工艺形成，大小尺寸一致，另外，需要说明的，本领域技术人员可以理解的，核心区与终端区界面范围内的遮蔽介质层118的刻蚀是可以依据实际选择的，如图13所述，遮蔽材料层的去除停留在了交界范围内最外侧的栅极沟槽108上方。Specifically, referring to FIG. 3, in an example, the extraction gate trench 110 is also prepared in the epitaxial layer 101. In an optional example, the area corresponding to the epitaxial layer 101 is pre-divided into devices Region B and terminal region A, wherein the gate trench 108 is prepared in the device region, and the extraction trench is prepared in the terminal region, wherein the first extraction trench 104 and the first The device trench 103, the second extraction trench 109 and the second device trench 107, the gate dielectric layer 111 and the extraction gate dielectric layer 112, the gate layer 114 and the extraction gate The layer 115, the shielding dielectric layer 118 and the shielding extraction dielectric layer 119 can all be formed based on the same process and have the same size. In addition, it should be noted that those skilled in the art can understand that the interface between the core area and the terminal area The etching of the shielding dielectric layer 118 within the range can be selected according to actual conditions. As shown in FIG. 13, the removal of the shielding material layer stays above the outermost gate trench 108 in the boundary range.
具体的，在一示例中，还包括栅极接触孔123，所述栅极接触孔123的底部可以与第一引出沟槽104底部平齐，刚刚显露引出栅极层115，也可以是延伸至所述引出栅极层115中。另外，参见图17所示，在一示例中，采用在所述核心区及所述终端区上沉积整片导电材料层的方式形成所述源极电极结构124和所述栅极电极结构125，当沉积整片导电材料层，再基于所述第四光刻版进行刻蚀，定义出相隔离的所述源极电极结构124和所述栅极电极结构125，在一示例中，所述导电材料层的厚度介于0.8微米-2微米之间，可以是1微米或1.5微米等，这里的厚度是指所述导电材料层形成在所述外延层101上的厚度，如图17中的n所示。Specifically, in an example, it further includes a gate contact hole 123. The bottom of the gate contact hole 123 may be flush with the bottom of the first extraction trench 104, and the extraction gate layer 115 has just been exposed, or it may extend to The lead out gate layer 115. In addition, referring to FIG. 17, in an example, the source electrode structure 124 and the gate electrode structure 125 are formed by depositing a whole piece of conductive material layer on the core region and the terminal region. When the entire conductive material layer is deposited, and then etched based on the fourth photolithography, the source electrode structure 124 and the gate electrode structure 125 are defined to be separated. In one example, the conductive material The thickness of the material layer is between 0.8 μm and 2 μm, and can be 1 μm or 1.5 μm, etc. The thickness here refers to the thickness of the conductive material layer formed on the epitaxial layer 101, as shown in n in FIG. 17 Shown.
综上所述，本发明在形成栅极沟槽刻蚀时，先形成了一个开口较大的第一器件沟槽，并继续刻蚀形成了一个开口较小的第二器件沟槽，并在第一器件沟槽中形成遮蔽介质层，通过工艺设计在器件的有源区形成自对准的源极接触孔，元胞的横向尺寸可以减小到1微米以下，从而可以增加器件的元胞密度，降低器件的导通电阻，适用于沟槽型MOSFET、沟槽型IGBT等沟槽型器件。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。To sum up, in the present invention, when the gate trench is formed and etched, a first device trench with a larger opening is first formed, and then a second device trench with a smaller opening is formed by the etching. A shielding dielectric layer is formed in the trench of the first device, and a self-aligned source contact hole is formed in the active area of the device through process design. The lateral size of the cell can be reduced to less than 1 micron, thereby increasing the cell size of the device. Density, reduce the on-resistance of the device, suitable for trench-type devices such as trench-type MOSFET and trench-type IGBT. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (15)

  1. 一种沟槽型场效应晶体管的制备方法，其特征在于，所述制备方法包括如下步骤：A method for manufacturing a trench field effect transistor, characterized in that the manufacturing method includes the following steps:
    提供第一掺杂类型的衬底，所述衬底具有相对的第一表面和第二表面；Providing a substrate of the first doping type, the substrate having a first surface and a second surface opposite to each other;
    于所述衬底的第一表面上形成所述第一掺杂类型的外延层；Forming the epitaxial layer of the first doping type on the first surface of the substrate;
    于所述外延层中形成若干个第一器件沟槽；Forming a plurality of first device trenches in the epitaxial layer;
    于所述第一器件沟槽的侧壁形成侧壁氧化层；Forming a sidewall oxide layer on the sidewall of the first device trench;
    基于所述侧壁氧化层对所述外延层进行刻蚀，以形成与所述第一器件沟槽连通的第二器件沟槽，且所述第二器件沟槽的宽度小于所述第一器件沟槽的宽度；The epitaxial layer is etched based on the sidewall oxide layer to form a second device trench communicating with the first device trench, and the width of the second device trench is smaller than that of the first device The width of the groove;
    去除所述侧壁氧化层以显露所述第一器件沟槽及所述第二器件沟槽，对应的所述第一器件沟槽及所述第二器件沟槽构成栅极沟槽；Removing the sidewall oxide layer to expose the first device trench and the second device trench, and the corresponding first device trench and the second device trench form a gate trench;
    至少于所述第二器件沟槽的内壁形成栅介质层，并于所述栅介质层表面形成栅极层，所述栅极层填充所述第二器件沟槽中；Forming a gate dielectric layer at least on the inner wall of the second device trench, and forming a gate layer on the surface of the gate dielectric layer, and the gate layer fills the second device trench;
    于所述外延层中形成第二掺杂类型的体区，所述体区位于相邻的所述栅极沟槽之间；Forming a body region of the second doping type in the epitaxial layer, the body region being located between the adjacent gate trenches;
    于所述第一器件沟槽中填充遮蔽介质层，并基于所述遮蔽介质层于所述体区中形成源区，所述源区邻接所述栅极沟槽；Filling a shielding dielectric layer in the first device trench, and forming a source region in the body region based on the shielding dielectric layer, and the source region is adjacent to the gate trench;
    基于所述遮蔽介质层于所述外延层中形成自对准的源极接触孔，所述源极接触孔贯穿所述源区至所述体区，并显露所述体区；以及Forming a self-aligned source contact hole in the epitaxial layer based on the shielding dielectric layer, the source contact hole penetrates the source region to the body region and exposes the body region; and
    至少于所述源极接触孔中填充导电材料层以形成源极电极结构，并于所述衬底的第二表面上形成与所述衬底电连接的下电极结构。At least a conductive material layer is filled in the source contact hole to form a source electrode structure, and a lower electrode structure electrically connected to the substrate is formed on the second surface of the substrate.
  2. 根据权利要求1所述的沟槽型场效应晶体管的制备方法，其特征在于，所述的于所述外延层中形成若干个第一器件沟槽，还包括：The method for manufacturing a trench field effect transistor according to claim 1, wherein the forming a plurality of first device trenches in the epitaxial layer further comprises:
    于所述外延层表面形成掩膜材料层，其中，所述掩膜材料层包括氧化硅层，所述掩膜材料层的厚度范围为8000埃至15000埃；Forming a mask material layer on the surface of the epitaxial layer, wherein the mask material layer includes a silicon oxide layer, and the thickness of the mask material layer ranges from 8000 angstroms to 15000 angstroms;
    基于第一光刻版对所述掩膜材料层进行图形化以形成第一掩膜，所述第一掩膜定义出待形成的所述第一器件沟槽；以及Patterning the mask material layer based on a first photolithography plate to form a first mask, the first mask defining the first device trench to be formed; and
    基于所述第一掩膜对所述外延层进行刻蚀以于所述外延层中形成所述第一器件沟槽，其中，所述第一器件沟槽的宽度范围为0.2微米至0.4微米，所述第一器件沟槽的深度范围为0.2微米至0.4微米。The epitaxial layer is etched based on the first mask to form the first device trench in the epitaxial layer, wherein the width of the first device trench ranges from 0.2 μm to 0.4 μm, The depth of the trench of the first device ranges from 0.2 μm to 0.4 μm.
  3. 根据权利要求1所述的沟槽型场效应晶体管的制备方法，其特征在于，所述的于所述第一器件沟槽的侧壁形成侧壁氧化层，还包括：于所述第一器件沟槽的内壁形成表面氧化层，并 去除所述第一器件沟槽底部的所述表面氧化层形成所述侧壁氧化层。The method of manufacturing a trench field effect transistor according to claim 1, wherein the forming a sidewall oxide layer on the sidewall of the trench of the first device further comprises: applying a sidewall oxide layer on the sidewall of the first device trench. The inner wall of the trench forms a surface oxide layer, and the surface oxide layer at the bottom of the first device trench is removed to form the sidewall oxide layer.
  4. 根据权利要求1所述的沟槽型场效应晶体管的制备方法，其特征在于，所述至少于所述第二器件沟槽的内壁形成栅介质层，还包括：所述栅介质层还延伸至所述第一器件沟槽的内壁及所述第一器件沟槽周围的所述外延层表面。The method of manufacturing a trench field effect transistor according to claim 1, wherein the forming a gate dielectric layer at least on the inner wall of the trench of the second device further comprises: the gate dielectric layer further extends to The inner wall of the first device trench and the epitaxial layer surface around the first device trench.
  5. 根据权利要求1所述的沟槽型场效应晶体管的制备方法，其特征在于，所述并于所述栅介质层表面形成栅极层，所述栅极层填充所述第二器件沟槽中，还包括：于所述栅介质层表面沉积栅极材料层，并对所述栅极材料层进行回刻，去除所述第一器件沟槽内及所述第一器件沟槽周围的所述外延层上的所述栅极材料层以形成所述栅极层。The method for manufacturing a trench field effect transistor according to claim 1, wherein the gate layer is formed on the surface of the gate dielectric layer, and the gate layer fills the trench of the second device , Further comprising: depositing a gate material layer on the surface of the gate dielectric layer, and etch back the gate material layer to remove the first device trench in and around the first device trench The gate material layer on the epitaxial layer forms the gate layer.
  6. 根据权利要求1所述的沟槽型场效应晶体管的制备方法，其特征在于，所述于所述第一器件沟槽中填充遮蔽介质层，并基于所述遮蔽介质层于所述体区中形成源区，还包括：The method for manufacturing a trench field effect transistor according to claim 1, wherein the first device trench is filled with a shielding dielectric layer, and the shielding dielectric layer is placed in the body region based on the shielding dielectric layer. The formation of the source area also includes:
    于所述第一器件沟槽及所述第一器件沟槽周围的所述外延层上形成遮蔽介质材料层，并基于第二光刻版对所述遮蔽介质材料层进行图形化以定义出有源区，对所述有源区进行离子注入以形成所述源区，所述图形化后剩余的填充在所述第一器件沟槽中的所述遮蔽介质材料层构成所述遮蔽介质层，其中，进行所述离子注入的注入能量范围为60Kev至120Kev，注入角度范围为7度至30度。A shielding dielectric material layer is formed on the first device trench and the epitaxial layer around the first device trench, and the shielding dielectric material layer is patterned based on a second photolithography to define a Source region, performing ion implantation on the active region to form the source region, and the shielding dielectric material layer filled in the trenches of the first device after the patterning constitutes the shielding dielectric layer, Wherein, the implantation energy range for performing the ion implantation is 60Kev to 120Kev, and the implantation angle range is 7 degrees to 30 degrees.
  7. 根据权利要求1所述的沟槽型场效应晶体管的制备方法，其特征在于，所述沟槽型场效应晶体管结构的制备方法还包括制备引出栅结构的步骤，且所述外延层中还定义有终端区，其中，形成所述栅极沟槽的同时还于所述终端区中制备引出栅沟槽，所述引出栅沟槽包括第一引出沟槽及与其上下连通的第二引出沟槽，且形成所述第一器件沟槽的同时形成所述第一引出沟槽，形成所述第二器件沟槽的同时形成所述第二引出沟槽，形成所述栅介质层的同时于所述第二引出沟槽内壁形成引出栅介质层，形成所述栅极层的同时于所述第二引出沟槽中形成引出栅极层，形成所述遮蔽介质层的同时于所述第一引出沟槽中形成遮蔽引出介质层，以制备所述引出栅结构。The method for manufacturing a trench field effect transistor according to claim 1, wherein the method for manufacturing the trench field effect transistor structure further comprises a step of preparing a gate structure, and the epitaxial layer also defines There is a terminal region, wherein when the gate trench is formed, an extraction gate trench is also prepared in the terminal region, and the extraction gate trench includes a first extraction trench and a second extraction trench connected up and down , And the first extraction trench is formed at the same time as the first device trench is formed, the second extraction trench is formed at the same time as the second device trench is formed, and the gate dielectric layer is formed at the same time as the An extraction gate dielectric layer is formed on the inner wall of the second extraction trench, an extraction gate layer is formed in the second extraction trench when the gate layer is formed, and the shielding dielectric layer is formed at the same time as the first extraction A shielding extraction dielectric layer is formed in the trench to prepare the extraction gate structure.
  8. 一种沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构包括：A trench field effect transistor structure, characterized in that the trench field effect transistor structure includes:
    衬底，具有第一掺杂类型，所述衬底具有相对的第一表面和第二表面；A substrate having a first doping type, the substrate having a first surface and a second surface opposite to each other;
    外延层，具有所述第一掺杂类型，所述外延层形成于所述衬底的第一表面上，所述外 延层中形成有若干个栅极沟槽，每个所述栅极沟槽均包括上下连通设置的第一器件沟槽及第二器件沟槽，所述第二器件沟槽的宽度小于所述第一器件沟槽的宽度；An epitaxial layer having the first doping type, the epitaxial layer is formed on the first surface of the substrate, a plurality of gate trenches are formed in the epitaxial layer, each of the gate trenches Each includes a first device trench and a second device trench that are connected up and down, and the width of the second device trench is smaller than the width of the first device trench;
    栅极氧化层，形成于所述第二器件沟槽的内壁上；A gate oxide layer formed on the inner wall of the second device trench;
    栅极层，形成于所述栅极氧化层的表面，所述栅极层填充所述第二器件沟槽；A gate layer formed on the surface of the gate oxide layer, and the gate layer fills the second device trench;
    遮蔽介质层，填充于所述第一器件沟槽中；A shielding dielectric layer is filled in the trench of the first device;
    体区，具有第二掺杂类型，形成于相邻所述栅极沟槽之间的所述外延层中；A body region having a second doping type and formed in the epitaxial layer between adjacent gate trenches;
    源区，具有所述第一掺杂类型，形成于所述体区中并邻接所述栅极沟槽，所述源区中形成有贯穿所述源区并显露所述体区的源极接触孔；A source region having the first doping type is formed in the body region and adjacent to the gate trench, and a source contact that penetrates the source region and exposes the body region is formed in the source region hole;
    源极电极结构，至少填充于所述源极接触孔中；以及The source electrode structure is filled at least in the source contact hole; and
    下电极结构，形成于所述衬底的第二表面上，并与所述衬底电连接。The bottom electrode structure is formed on the second surface of the substrate and is electrically connected to the substrate.
  9. 根据权利要求8所述的沟槽型场效应晶体管结构，其特征在于，所述源区的深度大于所述第一器件沟槽的深度；所述体区的深度小于或等于栅极沟槽的深度。The trench field effect transistor structure of claim 8, wherein the depth of the source region is greater than the depth of the first device trench; the depth of the body region is less than or equal to that of the gate trench depth.
  10. 根据权利要求8所述的沟槽型场效应晶体管结构，其特征在于，所述源极接触孔的宽度等于相邻的所述第一器件沟槽之间的距离。8. The trench field effect transistor structure of claim 8, wherein the width of the source contact hole is equal to the distance between adjacent trenches of the first device.
  11. 根据权利要求8所述的沟槽型场效应晶体管结构，其特征在于，所述源极接触孔的截面形状包括倒梯形，且所述源极接触孔的上部开口尺寸大于所述源极接触孔的底部尺寸。8. The trench field effect transistor structure of claim 8, wherein the cross-sectional shape of the source contact hole comprises an inverted trapezoid, and the upper opening size of the source contact hole is larger than that of the source contact hole. The bottom size.
  12. 根据权利要求8所述的沟槽型场效应晶体管结构，其特征在于，所述栅极沟槽的所述第二器件沟槽的深度小于所述栅极沟槽的所述第一器件沟槽的深度。8. The trench field effect transistor structure of claim 8, wherein the depth of the second device trench of the gate trench is smaller than that of the first device trench of the gate trench depth.
  13. 根据权利要求8所述的沟槽型场效应晶体管结构，其特征在于，所述源极接触孔与所述栅极沟槽交替排列设置。8. The trench field effect transistor structure of claim 8, wherein the source contact holes and the gate trenches are arranged alternately.
  14. 根据权利要求8所述的沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构还包括引出栅结构，且所述外延层中定义有终端区，其中，所述引出栅结构形成于所述终端区中，所述引出栅结构包括：引出栅沟槽，所述引出栅沟槽包括第一引出沟槽及与其上下连通的第二引出沟槽；形成于所述第二引出沟槽的内壁的引出栅介质层；形成于所述引出栅介质层表面的引出栅极层，所述引出栅极层填充所述第二引出沟槽；以及填充于所述第 一引出沟槽中的遮蔽引出介质层。8. The trench field effect transistor structure of claim 8, wherein the trench field effect transistor structure further comprises an extraction gate structure, and a terminal region is defined in the epitaxial layer, wherein the extraction A gate structure is formed in the terminal region, the extraction gate structure includes: an extraction gate trench, the extraction gate trench includes a first extraction trench and a second extraction trench connected up and down; formed in the first extraction trench Two extraction gate dielectric layer on the inner wall of the extraction trench; an extraction gate layer formed on the surface of the extraction gate dielectric layer, the extraction gate layer filling the second extraction trench; and filling the first extraction The shielding in the trench leads to the dielectric layer.
  15. 根据权利要求14所述的沟槽型场效应晶体管结构，其特征在于，所述遮蔽引出介质层上还形成有中间介质层，所述沟槽型场效应晶体管结构还包括栅极接触孔及栅极电极结构，其中，所述栅极接触孔依次贯穿所述中间介质层、所述遮蔽引出介质层至所述引出栅极层，所述栅极电极结构至少填充于所述栅极接触孔中。The trench field effect transistor structure of claim 14, wherein an intermediate dielectric layer is further formed on the shielding extraction dielectric layer, and the trench field effect transistor structure further includes a gate contact hole and a gate electrode. An electrode structure, wherein the gate contact hole sequentially penetrates the intermediate dielectric layer, the shielding extraction dielectric layer to the extraction gate layer, and the gate electrode structure is at least filled in the gate contact hole .
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