CN115841989A - Process method for preparing stepped trench semiconductor device - Google Patents
Process method for preparing stepped trench semiconductor device Download PDFInfo
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- CN115841989A CN115841989A CN202211464587.2A CN202211464587A CN115841989A CN 115841989 A CN115841989 A CN 115841989A CN 202211464587 A CN202211464587 A CN 202211464587A CN 115841989 A CN115841989 A CN 115841989A
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Abstract
The invention discloses a process method for preparing a stepped trench semiconductor device, which comprises the following steps: preparing a substrate, forming an epitaxial layer on the substrate, and sequentially forming a first oxide layer and a first nitride layer on the epitaxial layer; etching to form a first region, and performing thermal oxidation on the first region to form a second oxide layer; forming a second nitride layer; etching again to form a second region, wherein the first region and the second region are communicated with each other to form a groove; performing thermal oxidation to form a third oxide layer; removing the first nitride layer and the second nitride layer; forming a fourth oxide layer; and depositing polycrystalline silicon to fill the groove, and etching back the polycrystalline silicon to form first polycrystalline silicon. The invention can omit the Qtime control step, more accurately control the thickness of the oxide layer, reduce the process difficulty and simultaneously improve the performance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a process method for preparing a stepped trench semiconductor device.
Background
Currently, in the semiconductor device technology, an Oxide-diffused OB (Oxide-diffused OB) technology of a trench structure is widely used, and in devices such as a medium-low voltage MOSFET and a trench schottky (TMBS), FRD and IGBT devices are also used. Typical mass production products such as SGT devices have nonuniform electric field distribution in the drift region of the trench-side Oxide-nitride (Oxide-b) MOSFET, and have a difference from the Super Junction structure, so that the design concept of the Graded Oxide by-passivated GOB (Graded Oxide by-passivated GOB) structure is provided.
In the prior art, a process for manufacturing a stepped trench semiconductor device is provided, and as shown in fig. 1A to fig. 1H, the process for manufacturing the stepped trench semiconductor device includes the following steps:
preparing a substrate 1, forming an epitaxial layer 2 on the substrate 1, and forming a hard mask layer 3 on the epitaxial layer 2, as shown in fig. 1A;
etching the epitaxial layer 2 and the hard mask layer 3 to form a trench 4, as shown in fig. 1B;
removing the hard mask layer 3, as shown in FIG. 1C;
forming an oxide layer 5 on the surface of the epitaxial layer 2 and on the side walls and the bottom of the trench 4 by a thermal oxidation or CVD process, and depositing polysilicon 6 to fill the trench 4, as shown in fig. 1D;
back-etching the polysilicon 6 to form bottom polysilicon as shown in fig. 1E;
thinning the oxide layer 5 above the bottom polysilicon by wet etching, as shown in fig. 1F;
after removing the native oxide layer by Q time control, re-filling the trench 4 with polysilicon, and etching back to form a first polysilicon 6-1, as shown in fig. 1G;
after forming the inter-electrode oxide layer on the first polysilicon 6-1, continuously re-filling the trench 4 with polysilicon, and etching back to form a second polysilicon 6-2, as shown in fig. 1H;
in the above manufacturing process, in the process of thinning the oxide layer 5 by wet etching shown in fig. 1F, the wet etching has large variation in the production process, and the etching rate can also gradually change as the time and the number of times of use of the etching solution increase, resulting in unstable thickness of the oxide layer 5, but the thickness of the oxide layer 5 is a key parameter of the stepped trench semiconductor device, and the consistency of the device can be maintained only by accurately controlling the thickness. Also in the process of forming the first polysilicon 6-1 in two steps as shown in fig. 1G, since the polysilicon is easily oxidized naturally and forms a natural oxide layer, a strict Q time control is required here, which greatly increases the difficulty of the process.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a process for manufacturing a stepped trench semiconductor device, which can omit the Q time control step, control the thickness of the oxide layer more accurately, reduce the process difficulty, and improve the performance of the device.
In order to achieve the above object, the present invention provides a process for preparing a stepped trench semiconductor device, comprising the steps of:
preparing a substrate, forming an epitaxial layer on the substrate, and sequentially forming a first oxide layer and a first nitride layer on the epitaxial layer;
etching the epitaxial layer, the first oxide layer and the first nitride layer to form a first region, wherein the first region opening is positioned on the surface of the first nitride layer, and thermal oxidation is carried out on the side wall and the bottom wall of the first region to form a second oxide layer;
forming a second nitride layer on the side wall of the first area;
etching again to form a second region on the bottom wall of the first region, wherein the first region and the second region are communicated with each other to form a groove, and the line width size of the second region is determined by the thickness of the second nitride layer;
performing thermal oxidation on the side wall and the bottom wall of the second region to form a third oxide layer, where the thickness of the third oxide layer is determined according to the thicknesses of the second nitride layer and the second oxide layer, and generally, the optimal thickness of the third oxide layer is twice the sum of the thicknesses of the second nitride layer and the second oxide layer, so as to cut and align the epitaxial layer interface (on this basis, a person skilled in the art can appropriately adjust the thickness according to actual product performance parameters), so as to form a step-shaped trench side wall structure in a subsequent step;
removing the first nitride layer and the second nitride layer;
forming a fourth oxide layer on the first oxide layer, the second oxide layer and the third oxide layer;
and depositing polycrystalline silicon to fill the groove, and etching back the polycrystalline silicon to form first polycrystalline silicon, wherein the first polycrystalline silicon at least occupies a part of the first area.
When the step-shaped separation gate (Stepper SGT) semiconductor device is prepared by using the process method provided by the invention, at least one part of the first region is not occupied by the first polysilicon after the first polysilicon is formed; and the process steps further comprise: and removing the fourth oxide layer on the side wall of the part of the first area not occupied by the first polycrystalline silicon, forming a fifth oxide layer on the surface of the first polycrystalline silicon, depositing polycrystalline silicon again to fill the groove, and etching back the polycrystalline silicon to form second polycrystalline silicon.
The stepped groove Schottky (TMBS) semiconductor device is prepared by using the process method provided by the invention, and when the first polysilicon is formed, the groove is filled with the first polysilicon; and the process steps further comprise: and sequentially forming a barrier layer and a metal layer on the surface of the epitaxial layer.
Preferably, the process of forming the fourth oxide layer is a CVD process.
Preferably, the forming of the second nitride layer on the sidewall of the first region specifically includes: and depositing and forming a nitride layer on the side wall and the bottom wall of the first region, and removing the nitride layer on the bottom wall to obtain a second nitride layer.
The invention has the beneficial effects that:
(1) By adopting the cooperation of two-step etching and nitride process, the grid polysilicon of the stepped trench semiconductor device can be formed at one time, thereby avoiding the influence of natural oxidation of the polysilicon on the device performance, and improving BV/R dson Meanwhile, the process steps are saved, and the cost is reduced;
(2) The oxide layer is formed by the CVD process, so that the thickness of the oxide layer can be controlled more accurately;
(3) The process method is suitable for both SGT devices and TMBS devices.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIGS. 1A to 1H are schematic diagrams of a prior art process for preparing a Stepper SGT;
fig. 2A to fig. 2J are schematic diagrams illustrating a process for fabricating a stepped trench semiconductor device according to a first embodiment of the present invention;
FIGS. 3A to 3B are schematic views of a process for preparing TMBS according to the second embodiment of the present invention;
wherein:
1, a substrate; 2, an epitaxial layer; 3 hard mask layer; 4, grooves; 4-1 a first region; 4-2 a second region; 5, oxidizing layer; 5-1 a first oxide layer; 5-2 second oxide layer; 5-3 a third oxidation layer; 5-4 fourth oxide layer; 5-5 a fifth oxide layer; 6, polycrystalline silicon; 6-1 a first polysilicon; 6-2 second polysilicon; 7-1 a first nitride layer; 7-2 a second nitride layer; 8 a barrier layer; 9 metal layer.
Detailed Description
The core of the invention is to provide a process method for preparing the stepped trench semiconductor device, which can save the Q time control step, more accurately control the thickness of an oxide layer, reduce the process difficulty and simultaneously improve the performance of the device.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 2A to fig. 2J show a process method for preparing a stepped trench semiconductor device according to this embodiment, which includes the following steps:
step S1: as shown in fig. 2A, a substrate 1 is prepared, an epitaxial layer 2 is formed on the substrate 1, and a first oxide layer 5-1 and a first nitride layer 7-1 are sequentially formed on the epitaxial layer 2.
Step S2: as shown in fig. 2B, the epitaxial layer 2, the first oxide layer 5-1 and the first nitride layer 7-1 are etched to form a first region 4-1, and the first region 4-1 is opened on the surface of the first nitride layer 7-1.
And step S3: as shown in FIG. 2C, a second oxide layer 5-2 is formed on the sidewall and bottom wall of the first region 4-1 by thermal oxidation.
And step S4: as shown in fig. 2D, a nitride layer is deposited on the sidewalls and bottom wall of the first region 4-1 and the nitride layer on the bottom wall is removed, resulting in a second nitride layer 7-2.
Step S5: as shown in FIG. 2E, a second region 4-2 is etched again from the bottom wall of the first region 4-1, and the first region 4-1 and the second region 4-2 are connected to each other to form a trench 4.
Step S6: as shown in FIG. 2F, a third oxide layer 5-3 is formed on the sidewall and the bottom wall of the second region 4-2 by thermal oxidation.
Step S7: as shown in fig. 2G, the first nitride layer 7-1 and the second nitride layer 7-2 are removed.
Step S8: as shown in fig. 2H, a fourth oxide layer 5-4 is formed on the first oxide layer 5-1, the second oxide layer 5-2, and the third oxide layer 5-3 by a CVD process.
Step S9: as shown in fig. 2I, a deposition of polysilicon is performed to fill the trench 4 and the polysilicon is etched back to form a first polysilicon 6-1, only a portion of the first region 4-1 being occupied by the first polysilicon 6-1.
Step S10: as shown in fig. 2J, the fourth oxide layer 5-4 on the sidewall of the portion of the first region 4-1 not occupied by the first polysilicon 6-1 is removed (the fourth oxide layer 5-4 on the surface of the epitaxial layer 2 is removed in this step), a fifth oxide layer 5-5 is formed on the surface of the first polysilicon 6-1, the polysilicon is deposited again to fill the trench, and the polysilicon is etched back to form the second polysilicon 6-2.
Compared with the scheme in the prior art, the diameter of the second region 4-2 is smaller than that of the first region 4-1 through nitride deposition, the stepped trench wall structure is formed after the nitride layer is removed after the third oxide layer 5-3 grows, and the stepped structure is further formed on the inner surface of the fourth oxide layer 5-4 formed through a CVD (chemical vapor deposition) process, so that the stepped first polysilicon 6-1 can be further deposited, the process steps are saved, and the cost is reduced.
Example two
Different from the first embodiment, this embodiment is a processing method for preparing a TMBS semiconductor device with a stepped trench, and this embodiment replaces step S9 of the first embodiment with: as shown in fig. 3A, the trench 4 is filled with deposited polysilicon, and the polysilicon is etched back to form a first polysilicon 6-1, and the first polysilicon 6-1 is flush with the epitaxial layer 2.
Step S10 is replaced with: as shown in fig. 3B, a barrier layer 8 and a metal layer 9 are sequentially formed on the surface of the epitaxial layer 2 (the fourth oxide layer 5-4 on the surface of the epitaxial layer 2 may be removed before the barrier layer 8 is formed).
The beneficial effects of this embodiment are the same as those of the first embodiment, and are not described herein again.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A process method for preparing a stepped trench semiconductor device is characterized by comprising the following steps:
preparing a substrate, forming an epitaxial layer on the substrate, and sequentially forming a first oxide layer and a first nitride layer on the epitaxial layer;
etching the epitaxial layer, the first oxide layer and the first nitride layer to form a first region, wherein the first region opening is positioned on the surface of the first nitride layer, and thermal oxidation is carried out on the side wall and the bottom wall of the first region to form a second oxide layer;
forming a second nitride layer on the side wall of the first area;
etching again to form a second region on the bottom wall of the first region, wherein the first region and the second region are communicated with each other to form a groove, and the line width size of the second region is determined by the thickness of the second nitride layer;
performing thermal oxidation on the side wall and the bottom wall of the second region to form a third oxide layer, wherein the thickness of the third oxide layer is determined according to the thicknesses of the second nitride layer and the second oxide layer;
removing the first nitride layer and the second nitride layer;
forming a fourth oxide layer on the first oxide layer, the second oxide layer and the third oxide layer;
and depositing polycrystalline silicon to fill the groove, and etching back the polycrystalline silicon to form first polycrystalline silicon, wherein the first polycrystalline silicon at least occupies a part of the first area.
2. The process for preparing a stepped trench semiconductor device according to claim 1, wherein after forming the first polysilicon, at least a portion of the first region is unoccupied by the first polysilicon;
the method also comprises the following steps: and removing the fourth oxide layer on the side wall of the part of the first area not occupied by the first polycrystalline silicon, forming a fifth oxide layer on the surface of the first polycrystalline silicon, depositing polycrystalline silicon again to fill the groove, and etching back the polycrystalline silicon to form second polycrystalline silicon.
3. The process for preparing a stepped trench semiconductor device according to claim 1, wherein the first polysilicon is formed to fill the trench when the first polysilicon is formed;
the method also comprises the following steps: and sequentially forming a barrier layer and a metal layer on the surface of the epitaxial layer.
4. The process method for preparing a stepped trench semiconductor device according to claim 2 or 3, wherein the process for forming the fourth oxide layer is a CVD process.
5. The process method for preparing a stepped trench semiconductor device according to claim 2 or 3, wherein a second nitride layer is formed on the sidewall of the first region, specifically: and depositing and forming a nitride layer on the side wall and the bottom wall of the first region, and removing the nitride layer on the bottom wall to obtain a second nitride layer.
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| CN202211464587.2A CN115841989A (en) | 2022-11-22 | 2022-11-22 | Process method for preparing stepped trench semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
| CN117410173B (en) * | 2023-12-15 | 2024-03-08 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
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