CN116487418B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN116487418B CN116487418B CN202310732567.7A CN202310732567A CN116487418B CN 116487418 B CN116487418 B CN 116487418B CN 202310732567 A CN202310732567 A CN 202310732567A CN 116487418 B CN116487418 B CN 116487418B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 374
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 230000003647 oxidation Effects 0.000 claims abstract description 57
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000011241 protective layer Substances 0.000 claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 230000001629 suppression Effects 0.000 claims abstract description 15
- 230000005764 inhibitory process Effects 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 24
- 230000002401 inhibitory effect Effects 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000006388 chemical passivation reaction Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 6
- 239000003112 inhibitor Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present disclosure relates to a semiconductor structure and a method of fabricating the same. The preparation method of the semiconductor structure comprises the following steps. A substrate is provided and a trench is formed in the substrate. And forming a protective layer which covers the bottom of the groove along with the shape. And forming a suppression layer which covers the side wall of the groove and is contacted with the protection layer. And removing the protective layer. Forming a first gate oxide layer at the bottom of the groove by adopting a thermal oxidation process, and forming a second gate oxide layer by synchronizing the thermal oxidation inhibition layers; the thickness of the first gate oxide layer is larger than that of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together constitute a gate oxide layer. The preparation method of the semiconductor structure increases the thickness of the gate oxide layer at the bottom of the groove, so that the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the groove is solved, thereby reducing the gate-drain capacitance at the bottom of the groove and improving the high-frequency performance of the corresponding semiconductor device.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.
Background
In the manufacturing process of a trench type metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET for short), a gate oxide layer and a gate electrode are formed inside the trench for controlling the on and off of the MOSFET. Thus, the preparation of the gate oxide and the gate electrode is a very important process.
However, the gate oxide layer of the trench sidewall is thicker than the gate oxide layer of the trench bottom in the MOSFET due to the stress at the trench bottom. In this way, the gate oxide layer at the bottom of the trench is not sufficiently stressed and is easily broken down. And too thin gate oxide layer at the bottom of the trench can easily cause too large gate-drain capacitance at the location, which limits the use of the corresponding semiconductor device in high frequency applications.
Therefore, how to improve the voltage withstand capability of the gate oxide layer is a problem to be solved.
Disclosure of Invention
Based on the above, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, so as to effectively improve the voltage-resistant capability of a gate oxide layer.
Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including the following steps:
providing a substrate, and forming a groove in the substrate;
forming a protective layer which covers the bottom of the groove along with the shape;
forming a suppression layer which covers the side wall of the groove and is in contact with the protection layer;
removing the protective layer;
forming a first gate oxide layer at the bottom of the groove;
and forming a second gate oxide layer covering the side wall of the groove based on the inhibition layer.
In the embodiment of the disclosure, the protection layer covering the bottom of the groove along with the shape is formed, then the inhibition layer covering the side wall of the groove is formed, and the inhibition layer is contacted with the protection layer. The unexpected effect is that after removal of the protective layer, a suppression layer is obtained that covers only the trench sidewalls. Thus, the thickness of the second gate oxide layer covering the side wall of the trench, which is formed on the basis of the inhibition layer, can be controlled by controlling the formation thickness of the inhibition layer. In this way, the thickness difference between the first gate oxide layer at the bottom of the trench and the second gate oxide layer at the side wall of the trench can be easily adjusted. For example, the thickness of the first gate oxide layer formed at the bottom of the trench is made larger than the thickness of the second gate oxide layer formed at the side wall of the trench. Based on the above, the thickness of the gate oxide layer at the bottom of the groove can be simply increased by the preparation method of the semiconductor structure, so that the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the groove is solved, the gate-drain capacitance at the bottom of the groove is reduced, and the high-frequency performance of the corresponding semiconductor device is improved.
Optionally, the step of forming the protective layer includes:
forming an initial protection layer, wherein the initial protection layer covers the inner wall of the groove along with the shape;
forming a mask layer, wherein the mask layer fills the bottom of the groove to define a forming area of the protective layer;
patterning the initial protective layer based on the mask layer to form a protective layer;
the mask layer is removed.
In the embodiment of the disclosure, the protection layer covers the bottom of the groove along with the shape, and is formed based on the initial protection layer and the mask layer in a patterning way, so that the formation area of the protection layer can be accurately defined, and the formation area of the inhibition layer on the side wall of the groove can be accurately defined. Therefore, the formation areas of the second gate oxide layer and the first gate oxide layer can be effectively controlled by controlling the formation areas of the inhibition layer, and the thickness of the first gate oxide layer at the bottom of the groove and the thickness of the second gate oxide layer on the side wall of the groove are precisely controlled. And the protective layer is obtained based on the mask layer in a patterning way, so that the preparation process is simplified, and the production efficiency is improved.
Optionally, the material of the mask layer includes photoresist.
Optionally, the second gate oxide layer is formed by an oxidation inhibiting layer.
Optionally, the first gate oxide layer is formed by a thermal oxidation process; the second gate oxide layer is formed by forming the first gate oxide layer and simultaneously forming the synchronous oxidation inhibiting layer.
In the embodiment of the disclosure, when the structure after the protection layer is removed is oxidized by adopting a thermal oxidation process, the thickness of the first gate oxide layer formed at the bottom of the trench is greater than the thickness of the second gate oxide layer formed at the side wall of the trench because the side wall of the trench is covered with the inhibition layer. Thus, the thickness of the gate oxide layer at the bottom of the groove is increased, and the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the groove is further improved.
Optionally, the oxidation rate of forming the first gate oxide layer is greater than the oxidation rate of forming the second gate oxide layer. Therefore, the thickness of the first gate oxide layer formed at the bottom of the groove is ensured to be larger than that of the second gate oxide layer formed on the side wall of the groove through the same thermal oxidation process, and the problem of insufficient voltage resistance of the gate oxide layer at the bottom of the groove is solved.
Optionally, the range of values of the ratio of the oxidation rate of forming the first gate oxide layer to the oxidation rate of forming the second gate oxide layer includes: 19-21. Therefore, the ratio of the oxidation rates between the first gate oxide layer and the second gate oxide layer can be reasonably selected, and the ratio of the thicknesses of the first gate oxide layer at the bottom of the groove and the second gate oxide layer on the side wall of the groove can be reasonably controlled, so that the formation thicknesses of the first gate oxide layer and the second gate oxide layer can be ensured to meet the performance requirements of the semiconductor structure.
Optionally, after forming the second gate oxide layer, the method for preparing the semiconductor structure further includes: and oxidizing the surface of the substrate close to the first gate oxide layer and the second gate oxide layer by adopting a thermal oxidation process to form a third gate oxide layer. Wherein the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together form a gate oxide layer.
In the embodiment of the disclosure, the third gate oxide layer is formed on the surface of the substrate, which is close to the first gate oxide layer and the second gate oxide layer, so that the thickness of the gate oxide layer at the bottom of the trench can be further increased, and the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench can be further improved.
Optionally, the material of the substrate comprises highly doped silicon; the material of the inhibiting layer comprises silicon carbide or low doped silicon.
In the embodiment of the disclosure, the substrate is made of high-doped silicon, the inhibition layer is made of silicon carbide or low-doped silicon, and the oxidation rate of the substrate can be ensured to be higher than that of the inhibition layer, so that the thickness of the first gate oxide layer formed at the bottom of the groove is ensured to be larger than that of the second gate oxide layer formed at the side wall of the groove.
Optionally, the inhibiting layer is formed using a selective epitaxial growth process.
Based on the same inventive concept, the present disclosure also provides a semiconductor structure obtained by the preparation method in some embodiments. The semiconductor structure includes: the semiconductor device comprises a substrate, a first gate oxide layer and a second gate oxide layer. The substrate has a trench therein. The first gate oxide layer is filled at the bottom of the trench. And the second gate oxide layer covers the side wall of the groove and is connected with the first gate oxide layer. Wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer. The first gate oxide layer and the second gate oxide layer together constitute a gate oxide layer.
In the embodiment of the disclosure, the semiconductor structure is configured as described above, and the technical effects that can be achieved by the semiconductor structure are the same as those that can be achieved by the method for manufacturing a semiconductor structure in the foregoing embodiment, which is not described in detail herein.
Optionally, the semiconductor structure further includes: and a third gate oxide layer. The third gate oxide layer is located between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer. Wherein the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together form a gate oxide layer.
In the embodiment of the disclosure, the thickness of the gate oxide layer at the bottom of the trench is further increased by the third gate oxide layer between the substrate and the first gate oxide layer and between the substrate and the second gate oxide layer, so that the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench is further improved.
As described above, according to the semiconductor structure and the method for manufacturing the same provided in the embodiments of the present disclosure, by forming the protective layer covering the bottom of the trench in a conformal manner, and then forming the inhibition layer covering the sidewall of the trench and making the inhibition layer contact with the protective layer, unexpected effects can be obtained after removing the protective layer and forming the gate oxide layer: the thickness of the gate oxide layer at the bottom of the groove is simply and effectively increased, so that the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the groove is solved, the gate-drain capacitance at the bottom of the groove is reduced, and the high-frequency performance of a corresponding semiconductor device is improved; and the protective layer is obtained based on the mask layer in a patterning way, which is also beneficial to simplifying the preparation process of the semiconductor structure so as to improve the production efficiency.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure obtained in step S10 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 3 is a flow chart illustrating a method for forming a passivation layer in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 4 is a schematic cross-sectional view of a semiconductor structure obtained in step S21 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 5 is a schematic cross-sectional view of a semiconductor structure obtained in step S22 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 6 is a schematic cross-sectional view of a semiconductor structure obtained in step S23 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 7 is a schematic cross-sectional view of a semiconductor structure obtained in step S24 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 8 is a schematic cross-sectional view of a semiconductor structure obtained in step S30 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 9 is a schematic cross-sectional view of a semiconductor structure obtained in step S40 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 10 is a schematic cross-sectional view of a semiconductor structure obtained in step S50 in a method for fabricating a semiconductor structure according to an embodiment; FIG. 10 is a schematic cross-sectional view of a semiconductor structure according to an embodiment;
FIG. 11 is a schematic cross-sectional view of another structure obtained in step S50 in a method for fabricating a semiconductor structure according to an embodiment; fig. 11 is a schematic cross-sectional view of another semiconductor structure according to an embodiment.
Reference numerals illustrate:
1-a substrate; 11-grooves;
20-a protective layer; 200-an initial protective layer;
30-a mask layer;
40-a suppression layer;
50-gate oxide; 51-a first gate oxide layer; 52-a second gate oxide; 53-a third gate oxide;
60-gate.
Description of the embodiments
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Embodiments of the present disclosure are illustrated in the accompanying drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short).
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
In the manufacturing process of a trench type metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET for short), a gate oxide layer and a gate electrode are formed inside the trench for controlling the on and off of the MOSFET. Thus, the preparation of the gate oxide and the gate electrode is a very important process.
However, the gate oxide layer of the trench sidewall is thicker than the gate oxide layer of the trench bottom in the MOSFET due to the stress at the trench bottom. In this way, the gate oxide layer at the bottom of the trench is not sufficiently stressed and is easily broken down. And too thin gate oxide layer at the bottom of the trench can easily cause too large gate-drain capacitance at the location, which limits the use of the corresponding semiconductor device in high frequency applications.
Therefore, how to improve the voltage withstand capability of the gate oxide layer is a problem to be solved.
In view of the foregoing deficiencies of the related art, an object of an embodiment of the present disclosure is to provide a semiconductor structure and a method for manufacturing the same, so as to effectively improve the voltage-withstanding capability of a gate oxide layer.
Referring to fig. 1, in some embodiments, some embodiments of the present disclosure provide a method of fabricating a semiconductor structure, the method comprising the following steps.
S10: a substrate is provided and a trench is formed in the substrate.
S20: and forming a protective layer which covers the bottom of the groove along with the shape.
S30: and forming a suppression layer which covers the side wall of the groove and is contacted with the protection layer.
S40: and removing the protective layer.
S50: forming a first gate oxide layer at the bottom of the trench;
s60: a second gate oxide layer is formed overlying the trench sidewalls based on the inhibit layer.
In the embodiment of the disclosure, the protection layer covering the bottom of the groove along with the shape is formed, then the inhibition layer covering the side wall of the groove is formed, and the inhibition layer is contacted with the protection layer. The unexpected effect is that after removal of the protective layer, a suppression layer is obtained that covers only the trench sidewalls. Thus, the thickness of the second gate oxide layer covering the side wall of the trench, which is formed on the basis of the inhibition layer, can be controlled by controlling the formation thickness of the inhibition layer. In this way, the thickness difference between the first gate oxide layer at the bottom of the trench and the second gate oxide layer at the side wall of the trench can be easily adjusted. For example, the thickness of the first gate oxide layer formed at the bottom of the trench is made larger than the thickness of the second gate oxide layer formed at the side wall of the trench. Based on the above, the thickness of the gate oxide layer at the bottom of the groove can be simply increased by the preparation method of the semiconductor structure, so that the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the groove is solved, the gate-drain capacitance at the bottom of the groove is reduced, and the high-frequency performance of the corresponding semiconductor device is improved.
The following describes in detail the method for manufacturing the semiconductor structure provided in the embodiment of the present disclosure with reference to fig. 2 to 11.
In step S10, referring to S10 in fig. 1 and fig. 2, a substrate 1 is provided, and a trench 11 is formed in the substrate 1.
In some examples, substrate 1 may include, but is not limited to, a silicon substrate. And, the trench 11 may be divided into a trench 11 bottom and a trench 11 sidewall according to the shape distribution of the trench 11 within the substrate 1; namely: a virtual boundary may be considered to be provided between the bottom of the trench 11 and the sidewall of the trench 11, so as to define the respective formation positions of the first gate oxide layer and the second gate oxide layer correspondingly.
In some examples, the surface of the bottom of the trench 11 is curved.
Alternatively, a dry etching process may be used to form the trench 11 in the substrate 1.
In step S20, referring to S20 in fig. 1 and fig. 3 to 6, a protection layer 20 is formed, and the protection layer 20 covers the bottom of the trench 11.
Here, the protection layer 20 covers the bottom of the trench 11 in a conformal manner, which means: the protective layer 20 has a thin layer structure, and the surface of the protective layer 20 is shaped to the surface of the bottom of the trench 11, so that the surface shape of the protective layer 20 is similar to the surface shape of the bottom of the trench 11.
In some embodiments, referring to fig. 3, forming the protective layer 20 includes the following steps.
S21: and forming an initial protection layer which covers the inner wall of the groove along with the shape.
S22: and forming a mask layer, wherein the mask layer fills the bottom of the groove to define a forming region of the protective layer.
S23: patterning the initial protective layer based on the mask layer to form a protective layer.
S24: the mask layer is removed.
In the embodiment of the disclosure, the protection layer 20 covers the bottom of the trench 11 in a conformal manner, and is formed based on the patterning of the initial protection layer and the mask layer, so that the formation region of the protection layer 20 can be accurately defined, and thus the formation region of the inhibition layer on the sidewall of the trench 11 can be accurately defined. In this way, the formation areas of the second gate oxide layer and the first gate oxide layer can be effectively controlled by controlling the formation areas of the inhibition layer, so that the thickness of the first gate oxide layer at the bottom of the trench 11 and the thickness of the second gate oxide layer on the side wall of the trench 11 are precisely controlled. In addition, the protective layer 20 is obtained based on the mask layer patterning, which is also beneficial to simplifying the preparation process thereof so as to improve the production efficiency.
In step S21, referring to fig. 4, an initial protection layer 200 is formed, and the initial protection layer 200 conformally covers the inner wall of the trench 11.
In some embodiments, the initial protective layer 200 also extends over the upper surface of the substrate 1.
Optionally, the thickness range of the initial protective layer 200 includes: 200-1000 angstroms. For example: the thickness of the initial protective layer 200 may be 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms, or the like.
Alternatively, the material of the initial protective layer 200 may include, but is not limited to, silicon oxide.
Alternatively, the initial protective layer 200 is formed using a thermal oxidation process.
In step S22, referring to fig. 5, a mask layer 30 is formed, and the mask layer 30 fills the bottom of the trench 11 to define a formation region of the protection layer 20.
In some embodiments, forming mask layer 30 includes: forming an initial mask layer (not shown in fig. 5) that fills at least the trench 11; a portion of the initial mask layer 300 is removed to form the mask layer 30.
Optionally, an etch back process may be used to remove portions of the initial mask layer 300.
Optionally, the material of mask layer 30 includes, but is not limited to, photoresist.
In step S23, referring to fig. 6, the initial protection layer 200 is patterned based on the mask layer 30 to form the protection layer 20.
In some embodiments, an etching process may be used to remove the trench 11 sidewalls and the initial protective layer 200 on the upper surface of the substrate 1 based on the mask layer 30 to form the protective layer 20.
In step S24, referring to fig. 7, the mask layer 30 is removed.
Alternatively, the mask layer 30 may be removed using an etch back process.
In step S30, referring to S30 in fig. 1 and fig. 8, a suppression layer 40 is formed, and the suppression layer 40 covers the sidewall of the trench 11 and contacts the protection layer 20.
Optionally, the material of the substrate 1 comprises highly doped silicon and the material of the inhibiting layer 40 comprises silicon carbide or low doped silicon. It should be noted that, when the material of the substrate 1 is highly doped silicon and the material of the inhibitor layer 40 is low doped silicon, the oxidation rate of the inhibitor layer 40 is about 10% to 20% slower than the oxidation rate of the substrate 1. When the material of the substrate 1 is highly doped silicon and the material of the inhibition layer 40 is silicon carbide, the oxidation rate of the inhibition layer 40 is only 5% -10% of the oxidation rate of the substrate 1.
In the embodiment of the disclosure, the material of the substrate 1 is high doped silicon, and the material of the inhibiting layer 40 is silicon carbide or low doped silicon, so that the oxidation rate of the substrate 1 can be ensured to be higher than that of the inhibiting layer 40, so as to ensure that the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than that of the second gate oxide layer 52 formed at the side wall of the trench 11.
In some embodiments, the inhibiting layer 40 also extends over the upper surface of the substrate 1.
Optionally, the inhibiting layer 40 is formed using a selective epitaxial growth process.
In some embodiments, the film thickness of the inhibiting layer 40 depends on the difference Δh in height of the bottom of the trench 11 and the sidewall of the trench 11. Where Δh is equal to the difference between the height H1 of the trench 11 sidewall and the height H2 of the trench 11 bottom.
Illustratively, the ratio of the oxidation rate of the inhibiting layer 40 to the oxidation rate of the substrate 1 at the bottom of the trench 11 is 1:20, and the thickness of the inhibiting layer 40 is about 1/19 of the aforementioned height difference ΔH, irrespective of the influence of the film thickness of the inhibiting layer 40 on the oxidation rate.
It should be noted that, after the subsequent inhibiting layer 40 is completely oxidized, the substrate 1 at the sidewall of the trench 11 and the substrate 1 at the bottom of the trench 11 may be further oxidized to form a third gate oxide layer. At this time, since the second gate oxide layer formed at the side wall of the trench 11 based on the stopper layer 40 is thinner and the first gate oxide layer formed at the bottom of the trench 11 is thicker, the oxidation rate of the substrate 1 at the side wall of the trench 11 may be greater than the oxidation rate of the substrate 1 at the bottom of the trench 11 while the thermal oxidation process is continuously performed, so that the difference in thickness between the oxide layer at the side wall of the trench 11 and the oxide layer at the bottom of the trench 11 is reduced. Here, the oxide layer at the side wall of the trench 11 includes a second gate oxide layer and a third gate oxide layer at the side wall of the trench 11; the bottom oxide layer of the trench 11 includes a first gate oxide layer and a third gate oxide layer at the bottom of the trench 11.
Based on this, in some embodiments, the thickness of the inhibiting layer 40 may be increased reasonably, for example, such that the thickness of the inhibiting layer 40 is greater than 1/19 of the aforementioned height difference ΔH.
In step S40, referring to S40 in fig. 1 and fig. 9, the protection layer 20 is removed.
Alternatively, a wet etching process may be used to remove the protective layer 20.
Illustratively, the wet etching solution may include, but is not limited to, a buffered oxide etching solution (Buffered Oxide Etch, BOE for short) and a hydrofluoric acid etching solution (the ratio of hydrofluoric acid to water therein may be, for example, 100:1).
In step S50, referring to S50 in fig. 1 and fig. 10, a first gate oxide layer 51 is formed at the bottom of the trench 11.
In step S60, referring to S60 in fig. 1 and fig. 10, a second gate oxide layer 52 is formed to cover the sidewalls of the trench 11 based on the suppression layer 40.
In some embodiments, the second gate oxide 52 is formed by the oxidation inhibiting layer 40.
In some embodiments, the first gate oxide layer 51 is formed using a thermal oxidation process; the second gate oxide layer 52 is formed by simultaneously forming the first gate oxide layer 51 and the simultaneous oxidation inhibiting layer 40.
In the embodiment of the disclosure, when the structure after removing the protection layer 30 is oxidized by adopting the thermal oxidation process, the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is greater than the thickness of the second gate oxide layer 52 formed at the side wall of the trench 11 because the side wall of the trench 11 is covered with the inhibition layer 40. Thus, the thickness of the gate oxide layer at the bottom of the trench 11 is increased, and the problem of insufficient withstand voltage of the gate oxide layer at the bottom of the trench is further improved.
In some embodiments, the inhibiting layer 40 also extends over the upper surface of the substrate 1, and correspondingly, the second gate oxide layer 52 formed based on the inhibiting layer 40 also extends over the upper surface of the substrate 1.
In some embodiments, the oxidation rate of forming the first gate oxide layer 51 is greater than the oxidation rate of forming the second gate oxide layer 52. In this way, the thickness of the first gate oxide layer 51 formed at the bottom of the trench 11 is ensured to be greater than the thickness of the second gate oxide layer 52 formed at the sidewall of the trench 11 by the same thermal oxidation process, thereby improving the problem of insufficient withstand voltage of the gate oxide layer 50 at the bottom of the trench 11.
In some examples, the range of values of the ratio of the oxidation rate at which the first gate oxide layer 51 is formed to the oxidation rate at which the second gate oxide layer 52 is formed includes: 19-21.
It should be noted that, the oxidation rate of forming the first gate oxide layer is the oxidation rate of the substrate 1 at the bottom of the trench 11, and the oxidation rate of forming the second gate oxide layer is the oxidation rate of the inhibitor layer 40.
In the embodiment of the disclosure, by reasonably selecting the ratio of the oxidation rates between the first gate oxide layer 51 and the second gate oxide layer 52, the ratio of the thicknesses of the first gate oxide layer 51 at the bottom of the trench 11 and the second gate oxide layer 52 on the side wall of the trench 11 can be reasonably controlled, so as to ensure that the formation thicknesses of the first gate oxide layer 51 and the second gate oxide layer 52 meet the performance requirements of the semiconductor structure.
In some embodiments, referring to fig. 11, after forming the second gate oxide layer 52, the method further includes: the surface of the substrate 10 adjacent to the first gate oxide layer 51 and the second gate oxide layer 52 is oxidized using a thermal oxidation process to form a third gate oxide layer 53. Wherein the first gate oxide layer 51, the second gate oxide layer 52, and the third gate oxide layer 53 together constitute the gate oxide layer 50.
Here, after the suppression layer 40 is completely oxidized to form the second gate oxide layer 52, the substrate 1 at the side wall of the trench 11 and the substrate 1 at the bottom of the trench 11 may also be continuously oxidized to form the third gate oxide layer 53. That is, the aforementioned thermal oxidation process for forming the third gate oxide 53 and the thermal oxidation process for forming the second gate oxide 52 and the first gate oxide 51 may be the same thermal oxidation process.
In the embodiment of the disclosure, the third gate oxide 53 is formed on the surface of the substrate 1, which is close to the first gate oxide 51 and the second gate oxide 52, so that the thickness of the gate oxide 50 at the bottom of the trench 11 can be further increased, thereby further improving the problem of insufficient withstand voltage of the gate oxide 50 at the bottom of the trench 11.
Alternatively, the material of the gate oxide layer 50 (including the first gate oxide layer 51, the second gate oxide layer 52, or the third gate oxide layer 53) may include, but is not limited to, silicon oxide.
In some embodiments, referring to fig. 10 and 11, after forming gate oxide layer 50, the method further includes: a gate 60 filling at least the trench 11 is formed on the surface of the gate oxide layer 50 facing away from the substrate 10.
Illustratively, the gate 60 is formed of a conductive material having excellent electrical properties, such as doped polysilicon, metallic copper, or metallic tungsten.
Based on the same inventive concept, please refer to fig. 10 and 11, the present disclosure also provides a semiconductor structure obtained by using the preparation methods in some embodiments. The semiconductor structure includes: substrate 1, first gate oxide 51 and second gate oxide 52. The substrate 1 has a trench 11 therein. The first gate oxide layer 51 fills the bottom of the trench 11. The second gate oxide layer 52 covers the sidewall of the trench 11 and is connected to the first gate oxide layer 51. Wherein the thickness of the first gate oxide layer 51 is greater than the thickness of the second gate oxide layer 52. The first gate oxide layer 51 and the second gate oxide layer 52 together constitute the gate oxide layer 50.
In the embodiment of the disclosure, the semiconductor structure is configured as described above, and the technical effects that can be achieved by the semiconductor structure are the same as those that can be achieved by the method for manufacturing a semiconductor structure in the foregoing embodiment, which is not described in detail herein.
Optionally, the material of the substrate 1 comprises highly doped silicon. The second gate oxide layer 52 is obtained based on the oxidation of the suppression layer 40. The material of the inhibiting layer 40 comprises silicon carbide or low doped silicon. It should be noted that, when the material of the substrate 1 is highly doped silicon and the material of the inhibitor layer 40 is low doped silicon, the oxidation rate of the inhibitor layer 40 is about 10% to 20% slower than the oxidation rate of the substrate 1. When the material of the substrate 1 is highly doped silicon and the material of the inhibition layer 40 is silicon carbide, the oxidation rate of the inhibition layer 40 is only 5% -10% of the oxidation rate of the substrate 1.
In some embodiments, the thickness of the second gate oxide layer 52 (i.e., the film thickness of the stopper layer 40) depends on the difference Δh in height between the bottom of the trench 11 and the sidewalls of the trench 11. Where Δh is equal to the difference between the height H1 of the trench 11 sidewall and the height H2 of the trench 11 bottom. For example, if the ratio of the oxidation rate of the stopper layer 40 to the oxidation rate of the substrate 1 at the bottom of the trench 11 is 1:20, the thickness of the second gate oxide layer 52 (i.e., the film thickness of the stopper layer 40) may be 1/19 of the aforementioned height difference Δh, regardless of the influence of the film thickness on the oxidation rate.
In some examples, the surface of the bottom of the trench 11 is curved.
In some embodiments, referring to fig. 11, the semiconductor structure further includes: and a third gate oxide layer 53. The third gate oxide 53 is located between the substrate 1 and the first gate oxide 51, and between the substrate 1 and the second gate oxide 52. Wherein the first gate oxide layer 51, the second gate oxide layer 52 and the third gate oxide layer 53 together constitute a gate oxide layer.
In the embodiment of the disclosure, the third gate oxide 53 between the substrate 1 and the first gate oxide 51, and between the substrate 1 and the second gate oxide 52 further increases the thickness of the gate oxide 50 at the bottom of the trench 11, thereby further improving the problem of insufficient withstand voltage of the gate oxide 50 at the bottom of the trench 11.
Alternatively, the material of the gate oxide layer 50 (including the first gate oxide layer 51, the second gate oxide layer 52, or the third gate oxide layer 53) may include, but is not limited to, silicon oxide.
In some embodiments, referring to fig. 10 and 11, the semiconductor structure further includes: and a gate 60 disposed on the surface of the gate oxide layer 50 facing away from the substrate 10 and filling at least the trench 11.
Illustratively, the gate 60 is formed of a conductive material having excellent electrical properties, such as doped polysilicon, metallic copper, or metallic tungsten.
In summary, according to the semiconductor structure and the method for manufacturing the same provided in the embodiments of the present disclosure, by forming the protection layer 20 covering the bottom of the trench 11 in a conformal manner, and then forming the inhibition layer 40 covering the sidewall of the trench 11 and making the inhibition layer 40 contact with the protection layer 20, the unexpected effect can be obtained after removing the protection layer 20 and forming the gate oxide layer 50: the thickness of the gate oxide layer 50 at the bottom of the groove 11 is simply and effectively increased to solve the problem of insufficient withstand voltage of the gate oxide layer 50 at the bottom of the groove 11, thereby reducing the gate-drain capacitance at the bottom of the groove 11 and improving the high-frequency performance of the corresponding semiconductor device; in addition, the protective layer 20 is obtained based on the mask layer 30 in a patterning way, which is also beneficial to simplifying the preparation process of the semiconductor structure so as to improve the production efficiency.
In the description of the present specification, the technical features of the above-described embodiments may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description of the present specification.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (11)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a groove in the substrate;
forming a protective layer which covers the bottom of the groove along with the shape;
forming a suppression layer, wherein the suppression layer covers the side wall of the groove and is in contact with the protection layer;
removing the protective layer;
forming a first gate oxide layer at the bottom of the groove;
forming a second gate oxide layer covering the side wall of the groove based on the inhibition layer; the second gate oxide layer is formed by oxidizing the suppression layer; the thickness of the first gate oxide layer is larger than that of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together form a gate oxide layer.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein the step of forming the protective layer comprises:
forming an initial protection layer, wherein the initial protection layer covers the inner wall of the groove along with the shape;
forming a mask layer, wherein the mask layer fills the bottom of the groove to define a forming area of the protective layer;
patterning the initial protective layer based on the mask layer to form a protective layer;
and removing the mask layer.
3. The method of claim 2, wherein the material of the mask layer comprises a photoresist.
4. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein,
the first gate oxide layer is formed by adopting a thermal oxidation process;
the second gate oxide layer is formed by simultaneously oxidizing the suppression layer while forming the first gate oxide layer.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein an oxidation rate at which the first gate oxide layer is formed is greater than an oxidation rate at which the second gate oxide layer is formed.
6. The method of manufacturing a semiconductor structure according to claim 1, wherein the range of values of the ratio of the oxidation rate at which the first gate oxide layer is formed to the oxidation rate at which the second gate oxide layer is formed includes: 19-21.
7. The method of manufacturing a semiconductor structure according to claim 1, wherein after forming the second gate oxide layer, the method further comprises:
oxidizing the surface of the substrate, which is close to the first gate oxide layer and the second gate oxide layer, by adopting a thermal oxidation process to form a third gate oxide layer;
wherein the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together form a gate oxide layer.
8. The method of fabricating a semiconductor structure of claim 1, wherein the material of the substrate comprises highly doped silicon; the material of the inhibition layer comprises silicon carbide or low-doped silicon.
9. The method of claim 8, wherein the inhibiting layer is formed by a selective epitaxial growth process.
10. A semiconductor structure, characterized in that it is prepared by the preparation method according to any one of claims 1 to 9; the semiconductor structure includes:
a substrate having a trench therein;
the first gate oxide layer is filled at the bottom of the groove;
the second gate oxide layer covers the side wall of the groove and is connected with the first gate oxide layer;
wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; the first gate oxide layer and the second gate oxide layer together form a gate oxide layer.
11. The semiconductor structure of claim 10, further comprising:
a third gate oxide layer between the substrate and the first gate oxide layer, and between the substrate and the second gate oxide layer;
wherein the first gate oxide layer, the second gate oxide layer and the third gate oxide layer together form a gate oxide layer.
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| US6849898B2 (en) * | 2001-08-10 | 2005-02-01 | Siliconix Incorporated | Trench MIS device with active trench corners and thick bottom oxide |
| US20080296673A1 (en) * | 2007-05-29 | 2008-12-04 | Alpha & Omega Semiconductor, Ltd | Double gate manufactured with locos techniques |
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| JPH07326755A (en) * | 1994-04-06 | 1995-12-12 | Nippondenso Co Ltd | Semiconductor device and manufacture thereof |
| US5770878A (en) * | 1996-04-10 | 1998-06-23 | Harris Corporation | Trench MOS gate device |
| CN101558499A (en) * | 2005-06-24 | 2009-10-14 | 飞兆半导体公司 | Structure and method for forming laterally extending dielectric layer in a trench-gate FET |
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