CN109065625A - A kind of groove type MOS transistor, preparation method and the electronic device comprising it - Google Patents
A kind of groove type MOS transistor, preparation method and the electronic device comprising it Download PDFInfo
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- CN109065625A CN109065625A CN201810822227.2A CN201810822227A CN109065625A CN 109065625 A CN109065625 A CN 109065625A CN 201810822227 A CN201810822227 A CN 201810822227A CN 109065625 A CN109065625 A CN 109065625A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of groove type MOS transistors, it is prepared on substrate, the groove of the MOS transistor is divided into two sections: first segment groove and second segment groove, first grid material and second grid material are filled respectively in first segment groove and in second segment groove, first grid material and second grid material are physically isolated by gate insulating layer realization, and the gate metal of MOS transistor is drawn from first grid material.The structure of the embodiment of the present invention reduces the parasitic capacitance before grid and source electrode by being embedded to grid material in channel bottom with this.Invention additionally discloses a kind of preparation methods of groove type MOS transistor and a kind of electronic device.
Description
Technical field
The present invention relates to groove type MOS device preparation field, more particularly to a kind of groove type MOS device of small size
Preparation.
Background technique
Groove type MOS device is in power semiconductor field, trench mosfet
(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) compared to plane MOSFET,
Gully density can be significantly improved, reduces specific on-resistance, therefore, trench MOSFET has been widely adopted.
Fig. 1 is a kind of existing MOSFET structure, wherein 1 is terminal area, 2 be cell region, and 100 be substrate, and 101 are
Epitaxial layer, 102 be etching barrier layer, and 103 be polysilicon layer, and 104 be body area, and 105 be well region, and 107 be separation layer, and 109 be to connect
Metal is touched, 110 be the first wiring layer, and 111 be the second wiring layer.In this configuration, MOSFET element grid and drain electrode between and
Parasitic capacitance is larger between grid and source electrode, causes MOSFET element HF switch performance poor, and device drive loss is larger.Especially
It is in the application of high voltagehigh frequency, parasitic capacitance will cause biggish switch damage between grid and drain electrode and between drain electrode and source electrode
Consumption.
Summary of the invention
The technical problem to be solved by the invention is in order to improve MOS transistor because parasitic capacitance presence caused by damage
Larger problem is consumed, a kind of MOS switch structure is provided.
The embodiment of the invention provides a kind of groove type MOS transistor, prepare on substrate, the MOS transistor
Groove is divided into two sections: first segment groove and second segment groove, fills the in the first segment groove and in second segment groove respectively
One grid material and second grid material, the first grid material and the second grid material realize object by gate insulating layer
It is isolated in reason, the gate metal of the MOS transistor is drawn from the first grid material.
The groove type MOS transistor of the embodiment of the present invention, using the setting of both ends formula groove, so that the structure is in trench bottom
Portion channel bottom be embedded to one layer of grid material, with this come reduce grid and drain electrode between parasitic capacitance.
Optionally, the width of the first segment groove is greater than the width of the second segment groove.Such structure can make to make
Standby simple process, the photoetching number of plies will be reduced compared with the prior art.
Optionally, the first segment groove width is between 3:1 to the 5:1 of the second segment groove width.
Optionally, the second segment trench depth is not more than the first segment trench depth.
Optionally, the grid oxygen insulating layer is located in the first segment groove.
The present invention also provides a kind of embodiments of the preparation method of groove type MOS transistor comprising:
One substrate is provided, an epitaxial layer is grown in the substrate face, includes scheduled termination environment on the epitaxial layer
Domain and cell region；
First segment groove and second segment groove are formed on said epitaxial layer there, wherein first segment groove and the second segment ditch
Slot connection, and have the first segment groove and second segment groove in the terminal area and the cell region；
First grid material and second grid material are respectively formed in the first segment groove and second segment groove, and
The grid oxygen insulating layer of the first grid material and second grid material is isolated；
Body area, well region are formed in the epitaxial layer；
Source region metal and gate metal are formed in the substrate face, wherein the gate metal and the first grid material
Material is electrically connected；
Drain metal is formed in the substrate back.
Since gate metal is drawn from first grid material, second grid material is there is no external, and design is in ditch in this way
Trench bottom be embedded to one layer of grid material, with this come reduce grid and drain electrode between parasitic capacitance, so as to improve switching speed.
Optionally, first segment groove and second segment groove are formed on said epitaxial layer there, wherein first segment groove and described
The connection of second segment groove, and have the first segment groove and second segment groove in the terminal area and the cell region,
Specifically:
The epitaxial layer is etched, first segment groove is formed；
Etching barrier layer is formed in the epi-layer surface and the first segment groove；
The epitaxial layer and first segment trench wall are etched again, form second segment groove and are located at the first segment groove
The barrier layer side wall of side wall.
Optionally, first grid material and second grid material are respectively formed in the first segment groove and second segment groove
Material, and the grid oxygen insulating layer of isolation the first grid material and second grid material, specially；
The first grid oxide layer is formed in the second segment trench wall；
The grid material is deposited for the first time to filling up the first segment groove and second segment groove；
It returns and carves in the grid material to the first segment groove；
Remove the barrier layer side wall in the first segment groove；
In the first segment groove and the grid material surface forms the second grid oxide layer；
The grid material is deposited for the second time to the first segment groove is filled up, and is returned and is carved removal excess gate material described
Second grid material is formed in first segment groove.
Optionally, the second grid oxide layer is formed with the grid material surface in the first segment groove, using hot oxygen work
Skill；
After removing the barrier layer side wall in the first segment groove, further includes:
In ion implantation technology, inject ion in the epi-layer surface and the first segment groove, wherein inject from
The conduction type of son is identical with the conduction type of the epitaxial layer.
The present invention further provides a kind of electronic devices, including above-mentioned groove type MOS transistor.
Detailed description of the invention
Fig. 1 is the cross section structure schematic diagram of existing groove type MOS transistor；
Fig. 2 is the cross section structure schematic diagram of the groove type MOS transistor of one embodiment of the invention；
Fig. 3 is the preparation method flow chart of the groove type MOS transistor of one embodiment of the invention；
Fig. 4 to Figure 22 is the cross-sectional view for the structure that the preparation method correlation step of one embodiment of the invention is formed.
Wherein appended drawing reference is
Existing structure: 100 be substrate；101 be epitaxial layer；1 is terminal area；2 be cell region；102 be etching resistance
Barrier；103 be polysilicon layer；104 be body area；105 be well region；107 be separation layer；109 be contact metal；110 be the first cloth
Line layer；111 be the second wiring layer.
The embodiment of the present invention:
3 be terminal area；4 be cell region；200 be substrate；201 be epitaxial layer；202 be etching barrier layer；203 be
One section of groove；204 be second segment groove；205 be side wall；206 be first grid material layer；207 be gate insulating layer；2071 are
First grid separation layer；208 be second grid material layer；209 be body area；210 be well region；212 be buffer layer；213 are
Contact hole；214 be contact metal；215 be the first wiring layer；216 be the second wiring layer；S1 is substrate face；S2 is substrate back
Face.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiments.
First embodiment of the invention is related to a kind of groove type MOS transistor (as shown in Figure 2), prepares in substrate
On 200, including terminal area 3 and cell region 4, wherein the groove of MOS transistor is divided into two sections: first segment groove 203 and
Two sections of grooves 204, are separately filled with grid material 206,208 in the first segment groove and in second segment groove, and described two sections
Grid material in groove is physically isolated by the realization of gate insulating layer 207.By being embedded to one layer of grid material in channel bottom
Layer reduces grid and drain electrode capacitance with this, so that parasitic capacitance is become smaller, to promote the speed of mos transistor switch.
The width and depth of first segment groove and second segment groove can design as desired, in a specific embodiment
In, the width of first segment groove is greater than the width of second segment groove, and second segment trench depth is not more than first segment trench depth, example
It is between 3:1~5:1 of second segment groove width such as first segment groove width.Design is so that MOS transistor preparation is more held in this way
Easily.In a specific embodiment, the width of first segment groove is 0.5~1.5um, the width of second segment groove is 0.3~
1.2um, specific size will select as the case may be.The depth of first segment groove is between 1~2um, second segment groove
Depth between 0.5um~1um.This design is so that MOS transistor is easier to prepare.First grid material layer and the is isolated
The grid oxygen insulating layer of two gate material layers can be set in any one position, be located in the first segment groove.Have at one
In body embodiment, grid oxygen insulating layer is arranged in first segment groove.
Second embodiment of the present invention provides a kind of preparation method of groove type MOS transistor, as shown in figure 3, including
Following steps:
S301: a substrate with the first conduction type is provided, includes on substrate face growing epitaxial layers, epitaxial layer
Scheduled terminal area and cell region；
S302: first segment groove and second segment groove are formed on epitaxial layer, wherein first segment groove and second segment groove
Connection, and have first segment groove and second segment groove in terminal area and cell region；
S303: first grid material and second grid material are respectively formed in the first segment groove and second segment groove
Material, and the grid oxygen insulating layer of isolation the first grid material and second grid material；
S304: the well region in the body area, the first conduction type with the second conduction type, as device are formed in the epitaxial layer
Source region；
S305: source region metal, gate metal are formed in substrate face, wherein gate metal is electrically connected with first grid material
It is logical；
S306: drain metal is formed in substrate back.
The MOS transistor prepared through the above steps is subtracted because being embedded to one layer of gate material layers in channel bottom with this
Few grid and drain electrode capacitance, make parasitic capacitance become smaller, to promote the speed of mos transistor switch.
In another specific embodiment, in first segment groove and grid material surface forms the second grid oxide layer, can be with
Using hot oxygen technique；And after the barrier layer side wall in removal first segment groove, it can also include: ion implantation technology, outside
Prolong and inject ion in layer surface and first segment groove, wherein the conduction type of injection ion is identical with the conduction type of epitaxial layer.
Because of the increase of ion implantation technology, so that the partial region being ion implanted is easier to be oxidized in hot oxygen technique, with
The second grid oxide layer thickness that this is formed in the same time is thicker, to reduce the parasitic capacitance between grid and drain electrode.
Below with reference to Fig. 4 to Figure 22, the preparation method of second embodiment is further described.
In step S301, a substrate 200 with the first conduction type is provided, substrate has front S1 and back side S2
(see Fig. 4).The material of substrate 200 can be silicon substrate, be also possible to germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate.
Those skilled in the art can according to need selection substrate, therefore the type of substrate should not limit the scope of the invention.This
Substrate 200 in embodiment is preferably silicon substrate.The positive S1 and back side S2 of substrate are located at the opposite sides of substrate 200.It is serving as a contrast
Epitaxial layer 201 is formed on bottom 200, definition has terminal area and cell region in epitaxial layer 201.The material of epitaxial layer 201 is
Semiconductor material can be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or the binary or three of other iii-vs
First compound.In the present embodiment, the material of epitaxial layer 201 is Si.Epitaxial layer 201 also has the first conduction type.In this implementation
In example, the first conduction type is N-type, and the substrate with the first conduction type is N-type substrate.
The method that the known any suitable selective epitaxial growth of those skilled in the art can be used forms the extension
Layer 201, for example, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor
Outside deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam
Prolong one of (MBE).The selective epitaxial growth can carry out in UHV/CVD reaction chamber.
The thickness of epitaxial layer 201 can carry out reasonable set, illustratively, epitaxial layer 201 according to the demand of specific device
Thickness can be 5000 angstroms~50000 angstroms, above-mentioned numberical range is only as an example, can also be other suitable ranges.
In step s 302, first segment groove 203 and second segment groove 204 (referring to Fig. 6) are formed on epitaxial layer 201,
There are groove, specific step in middle cell region and terminal area are as follows: sequentially form sacrifice on the surface of the epitaxial layer 201
Layer and hard mask layer (not shown), form patterned photoresist layer, the patterned photoresist layer on hard mask layer
In include several openings, the opening is used to define the positions and dimensions of the groove of predetermined formation.Specifically, the sacrificial layer
Material can be any suitable material well known to those skilled in the art, and in the present embodiment, the material of the sacrificial layer includes
Silica.The hard mask layer includes silicon nitride (SiN), SiCN, SiC, amorphous carbon (a-C), boron nitride (BN), SiOF and SiON
One or more of.In the present embodiment, preferably, the material of the hard mask layer includes SiN.Chemical vapor deposition can be used
The suitable technique such as area method (CVD), atomic layer deposition method (ALD) or physical vaporous deposition (PVD) forms the sacrificial layer
With the hard mask layer.Patterned photoresist layer is formed on hard mask layer, and it is patterned can to form this by photoetching process
Photoresist layer, including the spin coating photoresist layer on hard mask layer, and the processes such as exposure development are carried out, so that patterned photoresist
Layer forms several openings, the positions and dimensions of those predetermined deep trench formed of opening definition.
Then, using patterned photoresist layer as exposure mask, hard mask layer, sacrificial layer and partial epitaxial layer 201 are successively etched,
To form first segment groove 203 in the epitaxial layer 201, and the patterned photoresist layer is removed, hard mask layer and sacrificial
Domestic animal layer, forms structure as shown in Figure 4.
Etching barrier layer then is deposited in epitaxial layer front, forms structure as shown in Figure 5.Then it carries out carving for second
Erosion forms second segment groove 204 and positioned at 203 side wall of first segment groove in 203 inner wall of epitaxial layer 201 and first segment groove
Barrier layer side wall 205 forms structure as shown in FIG. 6.
Wherein, the depth bounds of first segment groove can also be able to be any other suitable numerical value between 1~2um,
The depth bounds of second segment groove can be between 0.5~1um.The width and depth of first segment groove 203 and second segment groove 204
Degree can design as desired, and in a specific embodiment, the width of first segment groove is greater than the width of second segment groove, the
Two sections of trench depths are not more than first segment trench depth, such as first segment groove width is 3:1~5:1 of second segment groove width
Between.Design is so that MOS transistor preparation is easier in this way.In a specific embodiment, the width of first segment groove is
The width of 0.5~1.5um, second segment groove are 0.3~1.2um, and specific size will select as the case may be.
First grid material 206 and are respectively formed in first segment groove 203 and second segment groove 204 in step S303
Two grid materials 208, and the grid oxygen insulating layer 207 of isolation first grid material and second grid material, specifically:
First grid separation layer 2071 is formed in the second segment trench wall, forms structure as shown in Figure 7；
First time deposition of gate material is to filling up first segment groove 203 (referring to Fig. 8)；It returns and carves deposited gate material layers
In to the first segment groove, formed first grid material 206 (referring to Fig. 9)；
Remove the barrier layer side wall 205 in first segment groove (referring to Figure 10)；
With 206 surface of first grid material in first segment groove 203, formed gate isolation 207 (referring to Figure 11)；?
In one specific embodiment, gate isolation is silica, is realized using thermal oxidation technology, before carrying out thermal oxidation technology,
Ion implantation technology can be first carried out, injects ion, ion implantation concentration 1E12 in first segment groove and first grid surface
Between~1E13, injection ion can be P- or B+, and in thermal oxidation technology, reaction speed is very fast on the surface that ion implanting is crossed,
So thicker silicon oxide layer can be formed, the parasitic capacitance between grid and source electrode can be further decreased.
Second of deposition of gate material returns to first segment groove (referring to Figure 12) is filled up and carves removal excess gate material in institute
It states in first segment groove 203 and forms second grid material 208 (referring to Figure 13).
Etching barrier layer 202 may include any one of several etch stopper materials, including but not limited to: silica is carved
Lose barrier material and silicon nitride etch barrier material, in the present embodiment, etching barrier layer preferably includes silica and silicon nitride
Mixed layer is as etch stopper material.It can be used including but not limited to: thermal oxidation technology, chemical vapor deposition method or physics
The method of vapor deposition method forms etching barrier layer.In general, etching barrier layer has the thickness from about 200 to 1000 angstroms.
Gate material layers are deposited twice, are in the present embodiment polysilicon layer.The forming method of polysilicon layer can be selected low
Press chemical vapor deposition (LPCVD) technique.It is silane (SiH4), silicon that the process conditions for forming polysilicon layer, which include: reaction gas,
The range of flow of alkane can be 100~200 cc/mins (sccm), such as 150sccm；Temperature range can be 700 in reaction chamber
~750 degrees Celsius；Reacting cavity pressure can be 250~350 millimetress of mercury (mTorr), such as 300mTorr；May be used also in reaction gas
Including buffer gas, buffer gas can be helium or nitrogen, and the range of flow of the helium and nitrogen can be 5~20 liters/min
(slm), such as 8slm, 10slm or 15slm.Due to the presence of groove, so that there are V-type recess on the surface of polysilicon layer.It can also be with
Polysilicon layer is formed using existing any method, it is not limited here.
First grid material 206 and second grid material 208 can all use polysilicon layer, more in its forming process
Crystal silicon layer etch back process can use dry etching or dry etching.In a specific embodiment of the invention, it can adopt
Etch back process is executed with dry etching, dry method etch technology includes but is not limited to: reactive ion etching (RIE), ion beam erosion
Quarter, plasma etching or laser cutting.For example, by using plasma etching, etching gas can be using based on oxygen (O2-
Based gas).Specifically, using lower RF energy and low pressure and highdensity plasma gas can be generated come real
Existing dry etching.As an example, using plasma etch process, the etching gas used is based on oxygen (O2-
Based gas), the range of flow of etching gas can be 50 cc/mins (sccm)~150 cc/min
(sccm), reaction room pressure can be 5 millitorrs (mTorr)~20 millitorr (mTorr).Wherein, the etching gas of dry etching is also
It can be bromination hydrogen, carbon tetrafluoride gas or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only
Illustratively, it is not limited to which this method, those skilled in the art can also select other common methods.
In step S304, the body area 209 (referring to Figure 14) with the second conduction type, the first conduction are formed in the epitaxial layer
The well region 210 (referring to Figure 15) of type, well region 210 are the source region of MOS transistor device, concretely:
It carries out ion implantation technology twice: being initially formed body area, form source region afterwards.Wherein body area has the second conduction type,
It is in the present embodiment N-type.The implanted dopant of body area ion implanting can be B or P ion, and 100~200kev energy can be used, and infuse
Entering ion concentration can be per cubic centimeter for 5E12~5E13.Source region has the first conduction type, heavily doped for p-type in the present embodiment
It is miscellaneous.The implanted dopant of source region ion implanting can be As or B, and 20~150Kev energy can be used in injection process, inject ion
Concentration can be per cubic centimeter for 1E15~1E16.By ion implanting twice, body area and source region are formed on epitaxial layer.
Step S305: forming source region metal and gate metal in substrate face, concretely:
First at substrate face layer deposited isolating 212 (see Figure 16).The material of separation layer can be any suitable insulation material
Material, non-limiting example include oxide, nitride and nitrogen oxides, especially, silica, silicon nitride and silicon oxynitride,
It can be the insulating materials comprising polyvinyl phenol, polyimides or siloxanes etc..In the present embodiment, the material of separation layer
Material includes silicon nitride.Including but not limited to chemical vapor deposition method can be used and physical gas-phase deposite method forms isolation
Layer, for example, separation layer can be formed using the method for high density plasma CVD (HDP).
Separation layer is performed etching, is formed contact hole 213 (see Figure 17).Any existing side can be used in the etching of contact hole
Method.
In some embodiments, before etching contact hole, planarizing process also is carried out to separation layer, using chemical machinery
The surface of grinding technics (CMP process) planarizing process separation layer 212, forms contact hole on separation layer.The chemistry of separation layer
Mechanical milling tech can be not specifically limited herein using a kind of existing arbitrary mode.
And then, metal deposit is carried out, contact metal 214 is formed with filling contact hole 213.Contact gold in the present embodiment
Belong to and use tungsten W, draws it with good filling capacity.Certainly other any metal such as copper that can be used to fill can also be used
Alloy etc..(see Figure 18) after the deposition of tungsten forms metal layer, metal layer is tungsten layer in the present embodiment, will do it tungsten layer and returns quarter
It removes extra tungsten, forms contact metal (see Figure 19).
Redeposited first wiring layer 215 (see Figure 20), forms gate metal and source region metal.In a specific embodiment
In, also it can form passivation layer 216 in front portion region (see Figure 21).First wiring layer 210 by cupric metal film etc.
Conductive material formed, metal film of the cupric etc. include copper as main component.The metal film of cupric may include silver.Contain
The metal film of copper can further include selected from by Al, Au, Pt, Cr, Mo, W, Mg, Be, Zn, Pd, Cd, Hg, Si, Zr, Ti and Sn structure
At the different element of one or both of group.For example, the metal film of cupric can be formed by electroplating technology.For example, can be
Silicide film is formed on the surface of the metal film of cupric.Material and preparation process conventional in semiconductor preparation can be used in passivation layer
To complete.
S306 forms drain metal in substrate back, concretely:
Substrate back is first carried out reduction processing (see Figure 22), mechanical thinning process can be used in reduction processing, can also be used
Any other method that can be thinning by substrate thickness.
Then the second wiring layer 216 is deposited on the substrate back after being thinned, forms the drain electrode gold of groove type MOS transistor
Belong to, ultimately forms groove type MOS transistor structure as shown in Figure 2.The material selection of second metal layer and technique are all the same,
This is repeated no more.
The present invention also provides a kind of electronic devices, including the MOS transistor for using a kind of method of previous embodiment to be formed.
The electronic device of the present embodiment, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP or equipment, can also
For any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to having used above-mentioned MOS transistor, because
And there is better performance.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of groove type MOS transistor, preparation is on substrate, which is characterized in that the groove of the MOS transistor is divided into two
Section: first segment groove and second segment groove fill first grid material in the first segment groove and in second segment groove respectively
With second grid material, the first grid material and the second grid material are physically isolated by gate insulating layer realization,
The gate metal of the MOS transistor is drawn from the first grid material.
2. groove type MOS transistor as described in claim 1, it is characterised in that: the width of the first segment groove is greater than institute
State the width of second segment groove.
3. groove type MOS transistor as claimed in claim 2, it is characterised in that: the first segment groove width is described the
Between 3:1~5:1 of two sections of groove widths.
4. groove type MOS transistor as described in claim 1, it is characterised in that: the second segment trench depth is not more than institute
State first segment trench depth.
5. groove type MOS transistor as described in claim 1, it is characterised in that: the grid oxygen insulating layer is located at described first
In section groove.
6. a kind of preparation method of groove type MOS transistor characterized by comprising
One substrate is provided, grows an epitaxial layer in the substrate face, include on the epitaxial layer scheduled terminal area and
Cell region；
First segment groove and second segment groove are formed on said epitaxial layer there, and wherein first segment groove and the second segment groove connect
It is logical, and have the first segment groove and second segment groove in the terminal area and the cell region；
First grid material and second grid material, and isolation are respectively formed in the first segment groove and second segment groove
The grid oxygen insulating layer of the first grid material and second grid material；
Body area, well region are formed in the epitaxial layer；
Source region metal and gate metal are formed in the substrate face, wherein the gate metal and first grid material electricity
Connection；
Drain metal is formed in the substrate back.
7. the preparation method of groove type MOS transistor as claimed in claim 6, it is characterised in that: shape on said epitaxial layer there
At first segment groove and second segment groove, wherein first segment groove is connected to the second segment groove, and in the terminal area
There are the first segment groove and second segment groove with the cell region, specifically:
The epitaxial layer is etched, first segment groove is formed；
Etching barrier layer is formed in the epi-layer surface and the first segment groove；
The epitaxial layer and first segment trench wall are etched again, form second segment groove and are located at the first segment trenched side-wall
Barrier layer side wall.
8. the preparation method of groove type MOS transistor as claimed in claim 7, it is characterised in that: in the first segment groove
Be respectively formed first grid material and second grid material in second segment groove, and the isolation first grid material and the
The grid oxygen insulating layer of two grid materials, specially；
The first grid oxide layer is formed in the second segment trench wall；
The grid material is deposited for the first time to filling up the first segment groove and second segment groove；
It returns and carves in the grid material to the first segment groove；
Remove the barrier layer side wall in the first segment groove；
In the first segment groove and the grid material surface forms the second grid oxide layer；
The grid material is deposited for the second time to the first segment groove is filled up, and is returned and is carved removal excess gate material described first
Second grid material is formed in section groove.
9. the preparation method of groove type MOS transistor as claimed in claim 8, it is characterised in that:
In the first segment groove and the grid material surface forms the second grid oxide layer, using hot oxygen technique；
After removing the barrier layer side wall in the first segment groove, further includes:
In ion implantation technology, ion is injected in the epi-layer surface and the first segment groove, wherein injection ion
Conduction type is identical with the conduction type of the epitaxial layer.
10. a kind of electronic device, which is characterized in that including the groove type MOS transistor as described in claim 1 to 5.
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| CN113517232A (en) * | 2021-07-08 | 2021-10-19 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
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| CN105742185A (en) * | 2016-02-23 | 2016-07-06 | 深圳尚阳通科技有限公司 | Shielding grid power device and fabrication method thereof |
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| CN100437942C (en) * | 2002-05-31 | 2008-11-26 | Nxp股份有限公司 | Trench-gate semiconductor device and method of manufacturing |
| US20120292694A1 (en) * | 2011-05-16 | 2012-11-22 | Force Mos Technology Co. Ltd. | High switching trench mosfet |
| US20130168731A1 (en) * | 2011-12-30 | 2013-07-04 | Force Mos Technology Co., Ltd. | Semiconductor power device having wide termination trench and self-aligned source regions for mask saving |
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