CN115566078A - Semiconductor dielectric layer structure and manufacturing method - Google Patents
Semiconductor dielectric layer structure and manufacturing method Download PDFInfo
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- CN115566078A CN115566078A CN202211380807.3A CN202211380807A CN115566078A CN 115566078 A CN115566078 A CN 115566078A CN 202211380807 A CN202211380807 A CN 202211380807A CN 115566078 A CN115566078 A CN 115566078A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 77
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 77
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 66
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 60
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 60
- 238000011065 in-situ storage Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 42
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000002441 reversible effect Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 13
- 230000009471 action Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
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Abstract
The invention discloses a semiconductor dielectric layer structure and a manufacturing method thereof. The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a first thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the first thermal oxidation layer adjacent to the grooves, a second thermal oxidation layer is arranged on the surface of the silicon nitride layer, a deposited oxidation layer is arranged on the surface of the second thermal oxidation layer, the silicon nitride layer at the bottom of the second thermal oxidation layer and a part of the first thermal oxidation layer are hollowed to form a contact hole, the middle part of the bottom end in the contact hole extends to the surface of the epitaxial layer, the top of the epitaxial layer is exposed, the edge of the bottom end in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon, and the gate oxidation layer on the inner wall of the grooves is exposed. The invention can achieve the purpose of reducing reverse leakage current.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor dielectric layer structure and a manufacturing method thereof.
Background
The schottky diode has the advantages of low on-state voltage and high switching speed, but also has the defect of large reverse leakage current. The power loss of the schottky diode in the circuit includes: forward loss, turn-on loss, turn-off loss, reverse loss. Since the reverse leakage current of the schottky diode is large, the reverse loss is the main source of power loss. In terms of structural principles. The trench MOS Schottky utilizes the electric field shielding effect, so that the electric field at the Schottky contact position can be effectively reduced, and the influence of the Schottky barrier lowering effect is weakened. Because the Schottky leakage current and the electric field are in an exponential dependence relationship, the groove MOS Schottky structure can greatly reduce the leakage current compared with a plane Schottky.
In the aspect of manufacturing process. The planar Schottky is usually subjected to a wet etching process in the contact hole etching, so that the damage to the surface of a semiconductor is small, and the surface of the semiconductor is ideal. Due to the particularity of the oxide layer structure of the trench MOS Schottky, dry etching is often required for etching the contact hole. In order to ensure that the oxide layer is etched cleanly, a certain over-etching amount needs to be ensured, and the process can cause damage to the surface of a semiconductor and increase reverse leakage current. As shown in fig. 14, the following briefly describes the process steps from the production flow to the contact hole etching of the conventional trench MOS schottky:
1) A thermal oxide layer 2 is grown on the semiconductor epitaxial layer 1. The thermal oxidation layer 2 is used as a masking layer for etching the groove, and the thickness of the thermal oxidation layer is adjusted according to the selection ratio of the groove etching, and is generally 600 nm-800 nm;
2) And etching a window of the groove on the thermal oxidation layer 2 through photoetching and etching processes, wherein the remained thermal oxidation layer 2 is used as a masking medium for etching the groove. Completely removing the photoresist after etching;
3) Etching a groove pattern by using the thermal oxidation layer 2 as a mask;
4) Growing a thermal oxidation layer 2 as a gate oxide layer 3 of the trench MOS, wherein the wet etching rate of the thermal oxidation layer 2 is not different from that of the thermal oxidation layer;
5) After the in-situ doped polysilicon 4 is deposited, back etching is carried out on the in-situ doped polysilicon 4, and the remained in-situ doped polysilicon 4 is used as a filling material of the groove and is used as a grid contact material of the groove MOS;
6) And depositing an oxide layer 5 as a dielectric layer of the semiconductor and the top metal. The wet etching rate of the deposited oxide layer 5 can reach 7 times of that of the thermal oxide layer, and the difference is large. The dry etching rates of the two are not greatly different;
7) And coating photoresist 6 and photoetching to form the photoresist 6 to be used as a masking layer for etching the contact hole. It can be seen that the deposited oxide layer 5 and the thermal oxide layer 2 need to be stripped in the contact hole etching process, and then the contact hole can be formed with the surface of the semiconductor;
8) Because of the oxide layer structure of the contact hole to be etched, the contact hole etching generally adopts a dry etching method; if wet etching is used, the deposited oxide layer 5 is etched clean in advance, and then serious over-etching is caused to the thermal oxide layer 3 (gate oxide layer), so that the device is failed;
9) Removing the photoresist after etching the contact hole;
10 The schottky barrier, the top metal, the passivation layer, etc. will be continued to be fabricated later and will not be described here.
Disclosure of Invention
The embodiment of the invention provides a semiconductor dielectric layer structure and a manufacturing method thereof, and aims to solve the problem that the existing Schottky diode has more reverse electric leakage.
The invention provides a semiconductor dielectric layer structure which comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a first thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the first thermal oxidation layer adjacent to the grooves, a second thermal oxidation layer is arranged on the surface of the silicon nitride layer, a deposited oxidation layer is arranged on the surface of the second thermal oxidation layer, the deposited oxidation layer, the second thermal oxidation layer, the silicon nitride layer at the bottom of the second thermal oxidation layer and a part of the first thermal oxidation layer are hollowed out to form a contact hole, the middle part of the bottom end in the contact hole extends to the surface of the epitaxial layer to expose the top of the epitaxial layer, the edge of the bottom end in the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer on the inner wall of the grooves, the filling height of the polycrystalline silicon in the grooves in the contact hole area is 0-20 nm below the surface interface of the top part of the epitaxial layer, and the polycrystalline silicon outside the contact hole area is in the thickness range of the silicon nitride layer.
Further, the thickness of the first thermal oxidation layer is 27-33 nm.
Furthermore, the thickness of the silicon nitride layer is 180-220 nm.
Further, the thickness of the second thermal oxide layer is 549 to 671nm.
Furthermore, the thickness of the oxide layer is 330-470 nm.
In another aspect, the present application further provides a method for manufacturing a semiconductor dielectric layer structure as described in any one of the above, where the method includes:
growing a first thermal oxidation layer on an epitaxial layer of a semiconductor, depositing a silicon nitride layer on the surface of the first thermal oxidation layer, depositing undoped in-situ polycrystalline silicon on the surface of the silicon nitride layer, and completely oxidizing the undoped in-situ polycrystalline silicon on the silicon nitride to generate a second thermal oxidation layer;
etching windows of the grooves on the first thermal oxidation layer, the silicon nitride layer and the second thermal oxidation layer through an etching process, and completely removing the photoresist after etching is finished;
etching grooves on the epitaxial layer by using the window, and generating a thermal oxidation layer on the inner wall of each groove to serve as a gate oxidation layer of the groove MOS;
depositing in-situ doped polysilicon, and carrying out first back etching on the in-situ doped polysilicon to enable an in-situ doped polysilicon interface to fall within the thickness range of the silicon nitride layer;
depositing the second thermal oxide layer and the surface of the in-situ doped polysilicon after the etch back is finished to generate a deposited oxide layer;
sixthly, photoresist coating and photoetching are carried out on the surface of the deposited oxide layer, and the formed photoresist pattern is used as a masking layer for etching the contact hole;
seventhly, etching the deposited oxide layer and the second thermal oxide layer at corresponding positions by dry etching based on the photoresist pattern until the silicon nitride layer and the in-situ doped polysilicon are exposed;
step eight, removing the photoresist, carrying out secondary back etching on the in-situ doped polysilicon through dry etching until the surface of the in-situ doped polysilicon is 0-20 nm below the surface interface of the top of the epitaxial layer, exposing the first thermal oxidation layer below the silicon nitride layer, and finally, using the remained in-situ doped polysilicon as a filling material of the trench and a gate contact material of the trench MOS;
and step nine, corroding the silicon nitride layer in the contact hole by a wet method, and then corroding the first thermal oxidation layer in the contact hole until the epitaxial layer is exposed, so as to obtain the semiconductor medium layer structure.
Furthermore, the assembly holes also comprise a plurality of second assembly holes, and the thickness of the undoped in-situ polysilicon is 245-295 nm.
Furthermore, the accommodating groove is circular, the capacitor is also circular, and wet etching is performed on the silicon nitride layer in the contact hole through hot phosphoric acid.
Further, the first thermal oxide layer in the contact hole is etched through wet etching.
Further, the wet etching amount of the first thermal oxide layer is controlled to be 120%.
The embodiment of the invention provides a semiconductor dielectric layer structure and a manufacturing method thereof. The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a first thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the first thermal oxidation layer adjacent to the grooves, a second thermal oxidation layer is arranged on the surface of the silicon nitride layer, a deposited oxidation layer is arranged on the surface of the second thermal oxidation layer, a part of the silicon nitride layer at the bottom of the second thermal oxidation layer and a part of the first thermal oxidation layer are hollowed out to form a contact hole, the middle part of the bottom end in the contact hole extends to the surface of the epitaxial layer to expose the top of the epitaxial layer, the edge of the bottom end in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer on the inner wall of the grooves, the filling height of the polycrystalline silicon in the grooves outside the contact hole area is 0-20 nm below the surface interface of the top surface of the epitaxial layer, and the filling height of the polycrystalline silicon in the grooves outside the contact hole area is within the thickness range of the silicon nitride layer. Compared with the prior art, the semiconductor dielectric layer structure of this application, a part fretwork based on the silicon nitride layer of oxide layer and oxide layer bottom and first thermal oxidation layer forms the contact hole, and the bottom middle part in the contact hole extends to the epitaxial layer surface, makes the epitaxial layer top expose, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon, exposes trench inner wall's gate oxide, can guarantee that the schottky diode of using this semiconductor dielectric layer structure possesses the contact surface of more ideal, reaches the purpose that reverse leakage current reduces.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is an overall schematic view of a semiconductor dielectric layer structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 10 is a schematic structural diagram illustrating a method for fabricating a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 12 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 13 is a schematic structural diagram illustrating a method for fabricating a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 14 is a schematic structural diagram illustrating an embodiment of a method for forming a semiconductor dielectric layer structure in the prior art.
The figure is as follows: 1. an epitaxial layer; 2. a first thermal oxide layer; 3. a silicon nitride layer; 4. undoped in-situ polysilicon; 5. a second thermal oxidation layer; 6. a gate oxide layer; 7. in-situ doping polycrystalline silicon; 8. a deposited oxide layer; 9. and (7) photoresist.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to fig. 1, an embodiment of the present invention provides a semiconductor dielectric layer structure, which includes a semiconductor substrate, an epitaxial layer 1 is disposed on a surface of the semiconductor substrate, the epitaxial layer 1 is provided with a plurality of trenches, a first thermal oxide layer 2 is disposed on a surface of the epitaxial layer 1, in-situ doped polysilicon 7 is filled in the trenches, a gate oxide layer 6 is formed between the in-situ doped polysilicon 7 and the trenches, a silicon nitride layer 3 is disposed on a surface of the first thermal oxide layer 2 adjacent to the trenches, a second thermal oxide layer 5 is disposed on a surface of the silicon nitride layer 3, a deposited oxide layer 8 is disposed on a surface of the second thermal oxide layer 5, the deposited oxide layer 8, the thermal oxide layer 5, the silicon nitride layer 3 at a bottom of the thermal oxide layer 5, and a portion of the first thermal oxide layer 2 are hollowed out to form contact holes, a bottom middle portion in each contact hole extends to a surface of the epitaxial layer 1 to expose a top of the epitaxial layer 1, a bottom edge in the bottom of the contact hole extends to the in-situ doped polysilicon 7 to expose a gate oxide layer 6 on an inner wall of the trench, a filling height of the contact hole region within a range of 0 to 20nm below a top surface of the epitaxial layer, and a filling height of polysilicon in the trenches outside the silicon nitride layer. Compared with the prior art, the semiconductor dielectric layer structure of this application is based on deposited oxide layer 8 and thermal oxidation layer 5 and silicon nitride layer 3 and the partly fretwork of first thermal oxidation layer 2 of thermal oxidation layer 5 bottom and forms the contact hole, and bottom middle part in the contact hole extends to epitaxial layer 1 surface, make 1 top of epitaxial layer expose, and bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 7, expose trench inner wall's gate oxide 6, can guarantee that the schottky diode of using this semiconductor dielectric layer structure possesses the contact surface of more ideal, reach the purpose that reverse leakage current reduces.
In one embodiment, the thickness of the first thermal oxide layer 2 is preferably 27 to 33nm, the thickness of the silicon nitride layer 3 is preferably 180 to 220nm, the thickness of the second thermal oxide layer 5 is preferably 549 to 671nm, and the thickness of the deposited oxide layer 8 is preferably 330 to 470nm.
Fig. 2 is a schematic flow chart of a method for manufacturing the semiconductor dielectric layer structure according to an embodiment of the present invention.
Step one, growing a first thermal oxidation layer 2 with the thickness of 27-33 nm on an epitaxial layer 1 of a semiconductor; then depositing a silicon nitride layer 3 with the thickness of 180-220 nm on the surface of the first thermal oxidation layer 2; then, undoped in-situ polysilicon 4 with the thickness of 549-671 nm is deposited on the surface of the silicon nitride layer 3, as shown in FIG. 2; finally, the undoped in-situ polysilicon 4 on the silicon nitride layer 3 is completely oxidized to form a second thermal oxide layer 5, as shown in fig. 3. Since the silicon nitride layer 3 can effectively block oxygen, the thickness of the dielectric layer below the silicon nitride layer 3 does not change, and only the undoped in-situ polysilicon 4 is oxidized into the second thermal oxide layer 5. Typically the second thermal oxide layer 5 on the silicon nitride layer 3 is obtained by deposition, the deposited second thermal oxide layer 5 being of a lesser quality. The undoped in-situ polysilicon 4 is deposited on the silicon nitride layer, and then the undoped in-situ polysilicon 4 is completely oxidized, so that the high-quality second thermal oxidation layer 5 on the high-quality silicon nitride layer is obtained.
Step two, as shown in fig. 4, a window of the trench is etched on the first thermal oxide layer 2, the silicon nitride layer 3 and the second thermal oxide layer 5 by an etching process, wherein the portion of the second thermal oxide layer 5 that is not etched will play a role in shielding the trench during etching. After the window etching is completed, the photoresist 9 is completely removed.
Step three, as shown in fig. 5, etching a groove on the epitaxial layer 1 according to the window; as shown in fig. 6, a thermal oxide layer is formed on the inner wall of each trench as a gate oxide layer 6 of the trench MOS.
Step four, as shown in fig. 7, the in-situ doped polysilicon 7 is deposited and is etched back for the first time. Wherein the etch back amount needs to be controlled such that the in-situ doped polysilicon 7 interface falls within the thickness range of the silicon nitride layer 3.
And step five, as shown in fig. 8, depositing on the second thermal oxide layer 5 and the surface of the in-situ doped polysilicon 7 after the etching back is finished to generate a deposited oxide layer 8 with the thickness of 630-770 nm.
And step six, as shown in fig. 9, coating and photoetching a photoresist 9 on the surface of the deposited oxide layer 8, and taking the formed photoresist 9 pattern as a masking layer for etching the contact hole. The contact hole needs to etch the deposited oxide layer 8, the second thermal oxide layer 5, the deposited silicon nitride and the thermal oxide layer 2 clean.
And seventhly, as shown in fig. 10, etching the oxide layer 8 and the second thermal oxide layer 5 deposited at the corresponding positions by dry etching based on the photoresist 9 pattern until the silicon nitride layer 3 and the in-situ doped polysilicon 7 are exposed. Wherein, because the silicon nitride layer 3, the in-situ doped polysilicon 7 and the deposited oxide layer 8, the second thermal oxide layer 5 have higher selection ratio, the etching end point can be easily dropped on the interface of the deposited silicon nitride layer 3, the in-situ doped polysilicon 7.
Step eight, as shown in fig. 11, the photoresist 9 is removed; the in-situ doped polysilicon 7 is etched back by dry etching for the second time until the surface of the in-situ doped polysilicon 7 is within 20nm below the interface, exposing the first thermal oxide layer 2 under the silicon nitride layer 3, and finally leaving the in-situ doped polysilicon as the filling material of the trench and the gate contact material of the trench MOS, as shown in fig. 12. Wherein the interface refers to the top surface of the epitaxial layer 1.
Step nine, as shown in fig. 13, the silicon nitride layer 3 in the contact hole is etched by a wet method, and finally, as shown in fig. 1, the first thermal oxide layer 2 in the contact hole is etched until the epitaxial layer 1 is exposed, so that the semiconductor medium layer structure is obtained. Wherein, when the silicon nitride layer 3 is etched by the wet method, hot phosphoric acid is used for wet etching so as to ensure that the deposited oxide layer 8 and the in-situ doped polysilicon 7 are not etched. The thickness uniformity of the first thermal oxide layer 2 is good, and the wet etching can be controlled to be 120% to ensure that the first thermal oxide layer 2 on the surface of the semiconductor is etched cleanly, and the thickness of the finally deposited oxide layer 8 is lost by about 300nm. And finally, the surface of the semiconductor is exposed through wet etching, so that a more ideal surface state can be ensured, and the aim of reducing reverse leakage current is fulfilled.
It is to be noted that the wet etching control for the first thermal oxide layer 2 is 120%, meaning that the wet etching time is controlled by 120% of the thickness of the first thermal oxide layer 2.
The utility model discloses a semiconductor dielectric layer structure, some fretwork based on silicon nitride layer 3 and first thermal oxidation layer 2 of deposited oxide layer 8 and second thermal oxidation layer 5 bottom forms the contact hole, and the bottom middle part in the contact hole extends to epitaxial layer 1 surface, make 1 top of epitaxial layer expose, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 7, expose trench inner wall's gate oxide 6, can guarantee to use this semiconductor dielectric layer structure's schottky diode to possess more ideal contact surface, reach the purpose that reverse leakage current reduces.
The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it is possible to make various improvements and modifications to the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion.
It should be noted that the present invention is not limited to the particular embodiments described herein, and that the present invention includes all embodiments that are within the scope of the present invention. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A semiconductor medium layer structure is characterized in that the semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a first thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the first thermal oxidation layer adjacent to the grooves, a second thermal oxidation layer is arranged on the surface of the silicon nitride layer, a deposited oxidation layer is arranged on the surface of the second thermal oxidation layer, the deposited oxidation layer, the second thermal oxidation layer, the silicon nitride layer at the bottom of the second thermal oxidation layer and a part of the first thermal oxidation layer are hollowed out to form a contact hole, the middle part of the bottom end in the contact hole extends to the surface of the epitaxial layer, the top of the epitaxial layer is exposed, the edge of the bottom end in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer on the inner wall of the grooves, the filling height of the polycrystalline silicon in the grooves outside the contact hole area is 0-20 nm below the interface of the top surface of the epitaxial layer.
2. The semiconductor dielectric layer structure of claim 1, wherein the thickness of the first thermal oxide layer is 27-33 nm.
3. The semiconductor dielectric layer structure of claim 1, wherein the silicon nitride layer has a thickness of 180 nm to 220nm.
4. The semiconductor dielectric layer structure of claim 1, wherein the second thermal oxide layer is 549-671 nm thick.
5. The semiconductor dielectric layer structure of claim 1, wherein the thickness of the deposited oxide layer is 330-470 nm.
6. A method for fabricating a semiconductor dielectric layer structure according to any one of claims 1 to 5, wherein the method for fabricating comprises:
growing a first thermal oxidation layer on an epitaxial layer of a semiconductor, depositing a silicon nitride layer on the surface of the first thermal oxidation layer, depositing undoped in-situ polycrystalline silicon on the surface of the silicon nitride layer, and completely oxidizing the undoped in-situ polycrystalline silicon on the silicon nitride to generate a second thermal oxidation layer;
etching windows of the grooves on the first thermal oxidation layer, the silicon nitride layer and the second thermal oxidation layer through an etching process, and completely removing the photoresist after etching is finished;
etching grooves on the epitaxial layer by using the windows, and generating a thermal oxidation layer on the inner wall of each groove to serve as a gate oxidation layer of the groove MOS;
depositing in-situ doped polysilicon, and carrying out first back etching on the in-situ doped polysilicon to enable an in-situ doped polysilicon interface to fall within the thickness range of the silicon nitride layer;
depositing the second thermal oxide layer and the surface of the in-situ doped polysilicon after the etch back is finished to generate a deposited oxide layer;
sixthly, photoresist coating and photoetching are carried out on the surface of the deposited oxide layer, and the formed photoresist pattern is used as a masking layer for etching the contact hole;
seventhly, etching the deposited oxide layer and the second thermal oxide layer at corresponding positions by dry etching based on the photoresist pattern until the silicon nitride layer and the in-situ doped polysilicon are exposed;
step eight, removing the photoresist, carrying out secondary back etching on the in-situ doped polysilicon through dry etching until the surface of the in-situ doped polysilicon is 0-20 nm below the surface interface of the top of the epitaxial layer, exposing the first thermal oxidation layer below the silicon nitride layer, and finally, using the remained in-situ doped polysilicon as a filling material of the trench and a gate contact material of the trench MOS;
and step nine, corroding the silicon nitride layer in the contact hole by a wet method, and then corroding the first thermal oxidation layer in the contact hole until the epitaxial layer is exposed, so as to obtain the semiconductor medium layer structure.
7. The method of claim 6, wherein the undoped in-situ polysilicon has a thickness of 245-295 nm.
8. The method of claim 6, wherein the silicon nitride layer in the contact hole is wet etched by hot phosphoric acid.
9. The method of claim 6, wherein the etching of the first thermal oxide layer in the contact hole is performed by wet etching.
10. The method of claim 9, wherein the wet etching amount of the first thermal oxide layer is controlled to be 120%.
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