CN115360193B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN115360193B CN115360193B CN202211290258.0A CN202211290258A CN115360193B CN 115360193 B CN115360193 B CN 115360193B CN 202211290258 A CN202211290258 A CN 202211290258A CN 115360193 B CN115360193 B CN 115360193B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 174
- 238000002955 isolation Methods 0.000 claims abstract description 46
- 230000008021 deposition Effects 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 277
- 238000005530 etching Methods 0.000 claims description 97
- 239000011241 protective layer Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 22
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 14
- 238000000151 deposition Methods 0.000 description 34
- 239000007789 gas Substances 0.000 description 30
- 239000000463 material Substances 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 239000000243 solution Substances 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000635 electron micrograph Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910010093 LiAlO Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- YUCFVHQCAFKDQG-UHFFFAOYSA-N fluoromethane Chemical compound F[CH] YUCFVHQCAFKDQG-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- YQNQTEBHHUSESQ-UHFFFAOYSA-N lithium aluminate Chemical compound [Li+].[O-][Al]=O YQNQTEBHHUSESQ-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure at least comprises: a substrate; the shallow trench isolation structure is arranged on the substrate and comprises a convex part, and the convex part exceeds the surface of the substrate; a stack structure disposed on the substrate and on the shallow trench isolation structure; a deposition channel contacting the surface of the substrate and/or the protrusion through the stacked structure, the deposition channel being disposed on the high-voltage device region of the substrate; the step structure is arranged on the convex part and is positioned in the deposition channel, the surface of the step structure is higher than the surface of the substrate, and the height of the step structure is smaller than that of the convex part; the gate oxide layer is arranged on the substrate, is positioned in the deposition channel and has a gap with the step structure; and a polysilicon layer covering the gate oxide layer and the step structure. The invention provides a semiconductor structure and a manufacturing method thereof, which can improve the electrical performance of a semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for manufacturing the same.
Background
Gate Oxide Integrity (GOI) is one of the most important features in CMOS integrated circuit processes. The chip is provided with High Voltage (HV) and Low Voltage (LV) working devices, and the thickness of the gate oxide required by different working devices is different. The high voltage device oxide will be thicker and the low voltage device oxide will be thinner. The gate process that contains both HV and LV devices is referred to as a discrete gate process.
In the gate manufacturing process of the high-voltage device, overetching of the high-voltage device before the gate oxide layer is formed often damages the substrate, and the problem of silicon nitride residue near the shallow trench isolation structure and at the edge of the Active Area (AA) cannot be completely solved, which affects the electrical performance of the high-voltage device.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, so as to improve the electrical performance of a semiconductor device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a semiconductor structure, at least comprising:
a substrate;
the shallow trench isolation structure is arranged in the substrate and comprises a convex part, and the convex part exceeds the surface of the substrate;
a stack structure disposed on the substrate and on the shallow trench isolation structure;
a deposition channel in contact with a surface of the substrate and/or the protrusion through the stacked structure, the deposition channel disposed in a high voltage device region of the substrate;
the step structure is arranged on the convex part and is positioned in the deposition channel, the surface of the step structure is higher than the surface of the substrate, and the height of the step structure is smaller than that of the convex part;
the gate oxide layer is arranged on the substrate, the gate oxide layer is positioned in the deposition channel, and a gap is formed between the gate oxide layer and the step structure; and
and the polycrystalline silicon layer covers the gate oxide layer and the step structure.
In an embodiment of the present invention, a sidewall of the deposition channel is disposed on the protrusion.
In an embodiment of the present invention, the stacked structure includes a substrate oxide layer, the substrate oxide layer is disposed on the substrate, and a thickness of the substrate oxide layer is smaller than a height difference between a surface of the step structure and a surface of the substrate.
In an embodiment of the present invention, the stacked structure includes a protection layer disposed on the substrate oxide layer, and a sum of thicknesses of the substrate oxide layer and the protection layer is smaller than a thickness of the gate oxide layer.
In an embodiment of the present invention, the stacked structure includes a hard mask layer disposed on the protection layer.
In an embodiment of the invention, the height of the convex part is 1/10 to 1/5 of the depth of the shallow trench isolation structure.
The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a substrate;
forming a substrate oxide layer on the substrate;
forming a shallow trench isolation structure on the substrate, wherein the shallow trench isolation structure comprises a convex part, and the convex part exceeds the surface of the substrate;
forming a protective layer on the substrate oxide layer and the shallow trench isolation structure, and forming a hard mask layer on the protective layer;
etching the hard mask layer, the protective layer and the substrate oxide layer for multiple times to form a deposition channel, and forming a step structure on the convex part, wherein the deposition channel is in contact with the surface of the substrate and/or the convex part, and the surface of the step structure is higher than the surface of the substrate; and
and forming a gate oxide layer on the substrate, and forming a polycrystalline silicon layer on the gate oxide layer and the step structure.
In an embodiment of the present invention, the step of forming the deposition channel includes: and thinning the hard mask layer by using first plasma gas, wherein the etching amount of the thinned hard mask layer is 3/5-4/5 of the thickness of the hard mask layer.
In an embodiment of the present invention, after the hard mask layer is thinned, the hard mask layer and the protection layer are etched by using a second plasma gas until the hard mask layer located at the seam between the substrate and the protrusion is removed.
In an embodiment of the present invention, before removing the hard mask layer located at the joint between the substrate and the protrusion, the hard mask layer is etched by the second plasma gas until the hard mask layer located at a position corresponding to the surface of the substrate is removed.
In an embodiment of the invention, after removing the hard mask layer, the substrate oxide layer and the protection layer are etched, and the protrusion is etched at the same time until the substrate oxide layer is removed.
As described above, the present invention provides a method for manufacturing a semiconductor structure, which can avoid the residue of a mask material while not damaging a working region, thereby facilitating the improvement of the electrical performance of the semiconductor structure and reducing the occurrence of leakage current. The manufacturing method of the semiconductor structure provided by the invention can improve the flatness of the laid gate oxide layer, and the formed high-voltage device has good stability. According to the semiconductor structure provided by the invention, a high-voltage device can be efficiently manufactured on the substrate, rework and material waste are avoided, and the semiconductor structure is high in manufacturing yield and good in electrical performance. The semiconductor structure provided by the invention is suitable for various circuit layouts.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a structure for forming a first hard mask layer on a substrate.
Fig. 2 is a schematic structural diagram of an isolation trench formed in a substrate.
Fig. 3 is a schematic diagram of a shallow trench isolation structure formed in a substrate.
Figure 4 is a schematic diagram of the shallow trench isolation structure after the first hard mask layer is removed.
Fig. 5 is a schematic diagram of a structure for forming a well region in a substrate.
FIG. 6 is a schematic diagram of a structure for forming a second hard mask layer on a substrate.
FIG. 7 is a schematic diagram of a structure for forming a first patterned photoresist.
FIG. 8 is a schematic view of a semiconductor structure with a second hard mask layer and a protection layer etched.
FIG. 9 is a schematic view of the semiconductor structure after the second hard mask layer is etched to form a planar segment.
Fig. 10 is a semiconductor structure obtained without using the method for manufacturing a semiconductor structure according to the present invention.
FIG. 11 is a schematic diagram of a semiconductor structure after removing the second hard mask layer.
FIG. 12 is a schematic view of a structure for forming a deposition channel.
Figure 13 is an electron micrograph of a substrate oxide and shallow trench isolation structure.
Fig. 14 is a schematic structural diagram of forming a gate oxide layer.
Fig. 15 is a schematic structural view of forming a polysilicon layer and a second pattern photoresist.
Fig. 16 is a schematic view of a semiconductor structure for forming a high voltage gate according to an embodiment of the invention.
Fig. 17 is an electron micrograph of the gate oxide and polysilicon layers formed.
In the figure: 10. a substrate; 101. a substrate oxide layer; 102. a first hard mask layer; 103. a first etch window; 104. isolating the trench; 105. a well region; 11. a high voltage device region; 12. a low voltage device region; 20. a shallow trench isolation structure; 201. a convex portion; 202. a step structure; 30. a protective layer; 301. a working section; 302. an isolation section; 40. a second hard mask layer; 50. a first pattern photoresist; 501. a second etch window; 502. a second pattern photoresist; 60. a deposition channel; 70. a gate oxide layer; 701. a gap; 80. a polysilicon layer; 801. a first deposition part; 802. a second deposition portion; 803. a third deposition portion; 90. and a high voltage grid.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A Field Effect Transistor (FET) is a semiconductor device that controls an output loop current by controlling an electric Field Effect of an input loop. All field effect transistors have three ends of a grid electrode, a drain electrode and a source electrode, and correspond to a base electrode, a collector electrode and an emitter electrode of a bipolar transistor. Wherein a gate may be considered as a switch controlling a physical gate. The gate may allow or block electrons from flowing from the source to the drain by fabricating or eliminating a channel between the source and the drain. When the gate voltage is sufficiently high, the conductive channel conducts. Wherein a field effect transistor controls the flow of electrons or holes from the source to the drain by affecting the size and shape of the conducting channel.
Referring to fig. 1 and 2, the accuracy of the fabrication of the semiconductor structure greatly affects the stability of the gate voltage and the electrical performance of the device. Accordingly, the present invention provides a method for fabricating a semiconductor structure, which includes providing a substrate 10, and disposing a substrate oxide layer 101 on the substrate 10. The substrate 10 is, for example, a silicon substrate forming a semiconductor structure. The substrate 10 may include a base material and a silicon layer disposed over the base material. The substrate is, for example, silicon (Si), silicon carbide (SiC), sapphire (Al) 2 O 3 ) Gallium arsenide (GaAs), lithium aluminate (LiAlO) 2 ) The semiconductor substrate material and the silicon layer is an epitaxial material grown on a substrate and formed over the substrate. In this embodiment, phosphorus ions or arsenic ions may be implanted into the silicon layer to form an N-type semiconductor. The application does not limit the material and thickness of the substrate 10. In other embodiments of the present invention, a trace amount of a 3-valent element, such as indium or aluminum, may also be implanted into the substrate 10 to form a P-type semiconductor. In the present embodiment, the substrate oxide layer 101 may be formed by depositing an oxide material on the substrate 10 by Chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), or the like, so as to protect the surface of the substrate 10 from contamination when forming the shallow trench isolation structure 20. The material of the substrate oxide layer 101 may be, for example, silicon oxide. The thickness of the substrate oxide layer 101 is, for example, 60 to 80 angstroms, and specifically, the thickness of the substrate oxide layer 101 is, for example, 73 angstroms.
Referring to fig. 1 and 2, in an embodiment of the invention, a method for fabricating a semiconductor structure includes forming a first hard mask layer 102 on a substrate oxide layer 101, and etching the substrate using the first hard mask layer 102 as a maskA bottom oxide layer 101 and a substrate 10, and an isolation trench 104 is formed on the substrate 10. Specifically, a mask material, such as silicon nitride (SiN) or silicon nitride (Si), is deposited on the surface of the substrate oxide layer 101 by plasma enhanced chemical vapor deposition 3 N 4 ) And so on to form a first hard mask layer 102 on the substrate oxide layer 101. The first hard mask layer 102 has a thickness of, for example, 200 to 240 angstroms, and specifically, the first hard mask layer 102 has a thickness of, for example, 225 angstroms. The first hard mask layer 102 is a pattern after photolithography. For example, a photoresist layer is formed on the first hard mask layer 102, and the first hard mask layer 102 is etched using the photoresist layer as a mask, thereby forming a first etching window 103. Then, the substrate oxide layer 101 and the substrate 10 are etched using the first hard mask layer 102 as a mask, thereby forming an isolation trench 104. In which a high-voltage device region 11 and a low-voltage device region 12 are provided on a substrate 10, and the different device regions are separated by an isolation trench 104, according to an integrated circuit design of a semiconductor device.
Referring to fig. 3 and 4, in an embodiment of the present invention, the method for fabricating the semiconductor structure includes filling the isolation trench 104 to form the shallow trench isolation structure 20. Wherein the shallow trench isolation structure comprises a convex portion 201, and the convex portion 201 protrudes from the surface of the substrate 10. Specifically, an oxide, such as silicon oxide or silicon dioxide, is deposited into the isolation trenches 104 by chemical vapor deposition or plasma enhanced chemical vapor deposition until the oxide material overflows the isolation trenches 104. The first hard mask layer 102 is used as a barrier layer, and a portion of the oxide material overflowing the isolation trench 104 is removed by chemical-mechanical polishing (CMP), so as to form the shallow trench isolation structure 20. The first hard mask layer 102 is then removed by an etchant. The etching solution may be a mixed solution of phosphoric acid and hydrofluoric acid, and the first hard mask layer 102 is etched and removed under a high temperature condition. After etching, whether the first hard mask layer 102 is completely removed is checked, and if not, the first hard mask layer 102 can be processed again by using an etching solution until the first hard mask layer 102 is completely removed. Before removing the first hard mask layer 102, the surface of the first hard mask layer 102 may cover the surface oxide layer due to air oxidation, etc. Therefore, in the present embodiment, the surface oxide layer is removed by the hydrofluoric acid solution, so that the phosphoric acid can rapidly etch and remove the first hard mask layer 102. Wherein, the convex portion 201 is etched by the hydrofluoric acid solution while the surface oxide layer is removed. The corners of the protrusions 201 have a small angle, and thus the shape changes more significantly during the processing of the etching solution. The rounded shape is formed at the corners after the projections 201 are etched. In the present invention, the cross-sectional shape of the projection 201 is not limited.
Referring to fig. 5 and 6, in an embodiment of the present invention, a method for fabricating a semiconductor structure includes forming a protection layer 30 on a substrate oxide layer 101 and on a shallow trench isolation structure 20, and forming a second hard mask layer 40 on the protection layer 30. Specifically, the protective layer 30 is formed by depositing tetraethyl silicate on the substrate oxide layer 101 and on the shallow trench isolation structure 20 by chemical vapor deposition. The thickness of the protective layer 30 is, for example, 200 angstroms to 250 angstroms, and specifically, the thickness of the protective layer 30 is, for example, 225 angstroms. Silicon nitride is then deposited on the protective layer 30 by chemical vapor deposition to form a second hard mask layer 40. The second hard mask layer 40 has a thickness of, for example, 400 to 600 angstroms. Specifically, the second hard mask layer 40 is, for example, 500 angstroms. In the present embodiment, before forming the protective layer 30, ions are implanted into the substrate 10 to form the well region 105 in the substrate 10. The substrate 10 may be an intrinsic semiconductor, and the ions contained in the well region 105 may be donor impurities or acceptor impurities. Here, the substrate 10 may be an N-type semiconductor, and acceptor impurities are implanted to form the well region 105. The substrate 10 may be a P-type semiconductor, and donor impurities may be implanted to form the well region 105. The substrate 10 is provided with a shallow trench isolation structure 20 and a working area, and the shallow trench isolation structure 20 and the working area are distributed at intervals.
Referring to fig. 7 and 8, in an embodiment of the present invention, the method of fabricating the semiconductor structure includes forming a first patterned photoresist 50 on the second hard mask layer 40, and etching a portion of the second hard mask layer 40 using the first patterned photoresist 50 as a mask. Specifically, a photoresist is spin-coated on the second hard mask layer 40 to form a photoresist layer, and the photoresist layer is exposed to form a first pattern photoresist 50 and a plurality of second etchings are formedA window 501. Wherein the second etch window 501 is located in the high voltage device region 11. Wherein etching the second hard mask layer 40 and the protective layer 30 comprises etching a portion of the second hard mask layer 40 with a first plasma gas. Wherein the first plasma gas is carbon tetrafluoride (CF) 4 ) Trifluoromethane (CHF) 3 ) And helium (He). The etching amount of the first plasma gas to the second hard mask layer 40 is a first etching amount, and the first etching amount is, for example, 3/5 to 4/5 of the thickness of the second hard mask layer 40. In the present embodiment, the first etching amount is, for example, 400 angstroms. By etching the second hard mask layer 40 with the low selectivity of the first plasma gas, a portion of the second hard mask layer 40 can be quickly and uniformly removed, thereby thinning the second hard mask layer 40. The etching amounts of the second hard mask layer 40 covering the protrusion 201 and the second hard mask layer 40 covering the substrate oxide layer 101 are kept uniform within the second etching window 501. As shown in FIG. 8, the first etching amount is L 1 。
Referring to fig. 7 to 9, in an embodiment of the present invention, the step of etching the second hard mask layer 40 and the protection layer 30 includes etching the second hard mask layer 40 by the second plasma gas until the second hard mask layer 40 corresponding to the surface of the substrate 10 is removed. Since it is difficult to grow an oxide layer at the joint of the substrate 10 and the protrusion 201, when the substrate oxide layer 101 is deposited, a concave structure of the substrate oxide layer 101 at the joint of the protrusion 201 and the substrate 10 is very likely to occur. Moreover, during the etching process, since the concave structure is close to the convex portion 201, the material filled in the concave structure is more difficult to be etched clean in the dry anisotropic etching. Similarly, in the process of depositing the second hard mask layer 40, a recess structure is more likely to occur at the corresponding position of the second hard mask layer 40 at the joint of the substrate 10 and the protrusion 201. Therefore, the second hard mask layer 40 includes a flat section and a concave section, wherein the position of the concave section corresponds to the joint of the substrate 10 and the convex portion 201, and the position of the flat section corresponds to the surface of the substrate 10. In this embodiment, after the etching process is performed to remove the flat portion of the second hard mask layer 40, the recessed portion of the second hard mask layer 40 is shown in FIG. 9. Wherein the second plasma gas is fluoromethane (CH) 3 F) Oxygen (O) 2 ) And heliumA mixed gas of gas (He). As shown in FIG. 8, the second etching amount of the second plasma gas is L 2 The sum of the first etching amount and the second etching amount is less than or equal to the thickness of the flat section of the second hard mask layer 40. After the first plasma gas thins the second hard mask layer 40, the second hard mask layer 40 is etched by the second plasma gas, with the etch stop surface being disposed as close as possible to the surface of the protection layer 30. In the present embodiment, the second etching amount is, for example, 110 angstroms. The height of the protruding portion 201 is, for example, 1/10 to 1/5 of the depth of the shallow trench isolation structure 20.
Referring to fig. 7 to 10, in an embodiment of the invention, fig. 10 is an Electron Microscope (TEM) image obtained by observing a cross section of a semiconductor structure with a Transmission Electron Microscope (TEM). In this embodiment, fig. 10 shows a semiconductor structure formed without using the method for manufacturing a semiconductor structure according to the present invention. As shown in fig. 10, it is apparent that at the joint between the projection 201 and the surface of the substrate 10, in the case where the projection has been damaged, the mask material remains. To ensure that the masking material is etched clean, an over-etch operation must be performed. In the current structure, however, the active region is inevitably damaged by continuing the overetch operation, and the protrusion 201 and even the shallow trench isolation structure 20 may be etched below the surface of the substrate 10. With such a semiconductor structure, the electrical properties of the final device product may be affected, for example, by the occurrence of leakage currents. Therefore, in the present invention, the second hard mask layer 40 is etched by the second plasma gas with a high selectivity ratio, and after the second hard mask layer 40 in the second etching window 501 is etched and removed, the protection layer 30 and the protruding portion 301 are not involved in the second etching as much as possible, so that the protruding portion 201 and the protection layer 30 both have a good etching margin under the condition that the mask material silicon nitride of the second hard mask layer 40 remains.
Referring to fig. 7 to 10, in an embodiment of the present invention, the step of removing the second hard mask layer 40 and the protection layer 30 removes the second hard mask layer 40 by a second plasma gas and etches a portion of the protection layer 30. In the present embodiment, under the etching action of the second plasma gas with a high selectivity, the etching amount of the second hard mask layer 40 is much larger than that of the etching protection layer 30. Therefore, in the etching process of the second plasma gas, the second plasma gas first etches and removes the flat sections of the second hard mask layer 40, and then etches the protection layer 30 and the recessed sections of the second hard mask layer 40. Due to the high selectivity of the second plasma gas, the recessed portions of the second hard mask layer 40 are etched more when the protection layer 30 is etched, and the protection layer 30 is not over-etched. It is to be noted that the protective layer 30 also has a concave structure, and therefore the protective layer 30 also has a flat section and a concave section. In the embodiment, while the second hard mask layer 40 etches the recessed portion of the second hard mask layer 40, the flat portion of the protection layer 30 is removed by etching, and after the recessed portion of the second hard mask layer 40 is removed, the height difference between the flat portion and the recessed portion of the protection layer 30 is also reduced, so that the surface of the protection layer 30 becomes smoother after being etched by the second plasma gas.
Referring to fig. 7 to 10, in an embodiment of the invention, the second hard mask layer 40 is completely removed by etching a portion of the protection layer 30, so as to avoid the mask material residue of the second hard mask layer 40 at the connection position of the protrusion 201 and the substrate 10. And in the case that the mask material is completely removed, the damage of the convex portion 201 is reduced, and the work area and the shallow trench isolation structure 20 are protected. Specifically, as shown in fig. 8, the third etching amount is L 3 . The third etching amount is, for example, 1/10 to 1/4 of the thickness of the etching resist 30. In the present embodiment, after the etching process is completed, the thickness of the etching protection layer 30 is, for example, 110 angstroms to 190 angstroms. After the etching is completed, the plasma is used to dissociate the oxygen and react with the first pattern photoresist 50 to generate CO 2 And CO, thereby removing the first pattern photoresist 50. Due to the high etching selectivity of the second plasma gas to the etching between the protection layer 30 and the second hard mask layer 40, the second hard mask layer 40 can be etched in a large amount to ensure that the second hard mask layer 40 is completely removed while the surface of the protection layer 30 still has good flatness. The quality influence of the silicon nitride residue of the second hard mask layer 40 on the subsequent high-pressure oxidation can be avoided, and the surface flatness of the substrate 10 can be guaranteed and the working area can be protected from being damaged when the subsequent etching is carried out. In which, as shown in figure 11,after the etching is completed, the etching protective layer 30 has an active segment 301 and an isolation segment 302. Wherein, the working segment 301 and the isolation segment 302 are exposed, and the working segment 301 is located on the substrate 10, and the surface of the working segment 301 is a plane. The isolation segment 302 is located on the convex portion 201, and the surface of the isolation segment 302 includes a curved surface and a flat surface.
Referring to fig. 7 to 10, in an embodiment of the invention, the step of removing the second hard mask layer 40 by the second plasma gas may be divided into, for example, 2 times of etching, and specifically, a second etching amount is set to remove the flat section of the second hard mask layer 40, and a third etching amount is set to remove the recessed section of the second hard mask layer 40, so as to complete the removal of the second hard mask layer 40. The embodiment can not only better control the etching amount to avoid over-etching, but also improve the smoothness of the etched protection layer 30, and has high etching yield and good etching effect. In other embodiments of the present invention, the step of removing the second hard mask layer 40 by the second plasma gas may also include multiple etching. Specifically, the second etching amount and the third etching amount may be divided into a plurality of times to better control the etching amount. In other embodiments of the present invention, the step of removing the second hard mask layer 40 by the second plasma gas may include, for example, 1 etching, i.e., the second etching amount and the third etching amount are completed at one time, to complete the etching rapidly. In this embodiment, it is measured whether the second hard mask layer 40 has been completely removed after the etching is completed, and if not, the etching amount is supplemented by the second plasma gas until the second hard mask layer 40 is completely removed.
Referring to fig. 7 to 13, in an embodiment of the invention, the method for manufacturing the semiconductor structure includes removing the etching protection layer 30 and the substrate oxide layer 101, and etching the protrusion 201 to form a step structure 202. Specifically, the etching solution may be used to remove part of the etching protective layer 30 and the substrate oxide layer 101 until the surface of the substrate 10 is exposed, forming the deposition channel 60. Wherein the step structure 202 is formed at the same time as the deposition channel 60 is formed, wherein the step structure 202 is located within the deposition channel 60. In this embodiment, the etching solution is, for example, hydrofluoric acid (HF) or concentrated sulfuric acid (H) 2 SO 4 ) And hydrogen peroxide (H) 2 O 2 ) The mixed solution of (1). Wherein, under the action of the etching solution, a part of the convex portion 201 is removed, thereby forming a step structure 202 on the convex portion 201. In the embodiment, the height difference between the top surface of the step structure 202 and the surface of the substrate 10 is, for example, 2 to 3 times of the thickness of the substrate oxide layer 101, so as to ensure that the semiconductor structure of the invention still has a good isolation effect after the substrate oxide layer 101 is removed, and prevent the substrate 10 from having the surface unevenness and the like to influence the flatness of the formed gate oxide layer of the high-voltage device. Wherein the removal of the etching protection layer 30 and the substrate oxide layer 101 may be performed a plurality of times. The present invention does not limit the number of etching times, and in this embodiment, the etching protection layer 30 and the substrate oxide layer 101 are removed by 3 times, so as to ensure that the substrate oxide layer 101 does not remain on the surface of the substrate 10, and improve the etching accuracy. After the last etching is completed, the thickness of the oxide layer on the surface of the substrate 10 is tested to prevent the oxide layer 101 on the substrate from being left and affecting the forming quality of the gate oxide structure in the high-voltage device. If the substrate oxide layer 101 is not completely removed, the substrate oxide layer 101 is processed again by using the etching solution until the substrate oxide layer 101 is completely removed, so as to improve the gate oxide quality of the high-voltage device. Wherein the top surface of the step structure 202 is parallel to the surface of the substrate 10. In the deposition channel 60, the material of the second hard mask layer 40 is completely etched away, and particularly, no material such as silicon nitride remains on the surface of the substrate 10 and at the edge of the protrusion 201. The invention provides a semiconductor structure suitable for various circuit structure layouts. In the present embodiment, one sidewall of the deposition channel 60 is disposed on the protrusion 201, and the other sidewall of the deposition channel 60 is disposed on the bare substrate 10. In other embodiments of the present invention, two sidewalls of the deposition channel 60 may be disposed on different protrusions 201, respectively, wherein the deposition channel 60 spans at least 1 working region. In other embodiments of the present invention, both sidewalls of the deposition channel 60 may be disposed on the exposed substrate 10, and both sidewalls of the deposition channel 60 may be disposed on the same working area. Figure 13 is an electron micrograph of a substrate oxide and shallow trench isolation structure in accordance with one embodiment of the present invention. As shown in fig. 13, after the etching process is finished, the surface of the substrate oxide layer 101 has better flatness, which is beneficial to the protection worker in the subsequent etching processThe active region is not damaged by etching.
Referring to fig. 12 to 15, in an embodiment of the present invention, the method for manufacturing the semiconductor structure includes forming a gate oxide layer 70 on the substrate 10 in the second etching window 501 region, and forming a polysilicon layer 80 on the gate oxide layer 70. Specifically, under wet oxygen conditions and high temperature conditions, water vapor is brought into contact with the substrate 10 and reacts to oxidize the surface layer of the substrate 10, thereby forming the gate oxide layer 70 on the surface of the substrate 10. The thickness of the gate oxide layer 70 can be 1350-1500 angstroms, for example 1400 angstroms. The temperature condition for growing the gate oxide layer 70 may be, for example, 900 ℃ to 950 ℃, and may be, for example, 920 ℃. The reaction time is, for example, 50min to 55min, and specifically, 52min. When the gate oxide layer 70 is grown on the substrate 10, a part of the silicon substrate of the substrate 10 is consumed to form the gate oxide layer 70, so that in the present embodiment, a part of the gate oxide layer 70 is actually located above the bottom surface of the substrate oxide layer 101, and a part of the gate oxide layer 70 is located below the bottom surface of the substrate oxide layer 101, as shown in fig. 13. The thickness ratio of the gate oxide 70 located below the bottom surface of the substrate oxide layer 101 to the gate oxide 70 located above the bottom surface of the substrate oxide layer 101 may be, for example, 8 to 11, and specifically may be 9. A polysilicon layer 80 is grown overlying the surface of the gate oxide layer 70. Wherein, the thickness of the gate oxide layer 70 is greater than the sum of the thicknesses of the substrate oxide layer 101 and the etching protection layer 30, and the height of the gate oxide layer 70 is greater than the height of the step structure 202. Wherein a gap 701 is provided between the gate oxide layer 70 and the sidewall of the step structure 202. In this embodiment, the gap 701 is tapered, and in other embodiments, the cross section of the gap 701 may also be an arc-shaped groove structure. Wherein polysilicon layer 80 is formed by depositing polysilicon on gate oxide 70, gap 701 and step structure 202 by chemical vapor deposition. In the present embodiment, the polysilicon layer 80 includes a first deposition portion 801 disposed on the gate oxide layer 70, a second deposition portion 802 deposited in the gap 701, and a third deposition portion 803 disposed on the step structure 202. Wherein the thickness of the first deposition portion 801 is less than that of the third deposition portion 803, and the thickness of the third deposition portion 803 is less than that of the second deposition portion 802. In order to ensure the surface of the polysilicon layer 80 is flat, the surface of the polysilicon layer 80 may be polished after the high voltage device is formed.
Referring to fig. 7, 15 and 16, in an embodiment of the present invention, the method for manufacturing the semiconductor structure includes etching the polysilicon layer 80 and the gate oxide layer 70 to form the high voltage gate 90. Specifically, a photoresist layer may be formed on the polysilicon layer 80 by spin coating, and then the photoresist layer is exposed and developed to form the second patterned photoresist 502. The polysilicon layer 80 and the gate oxide layer 70 are etched by plasma gas or etching liquid using the second pattern photoresist 502 as a mask, and a high voltage gate 90 is formed on the high voltage device region 11. In the formed high-voltage grid 90, the surface flatness of the substrate 10 is good, the damage of a working area is small, the formed high-voltage grid 90 has better grid quality, and a semiconductor device formed by the semiconductor structure is not easy to generate electric leakage phenomenon and has good electrical performance.
Referring to fig. 14 to 17, in an embodiment of the invention, fig. 17 is an Electron Microscope (TEM) image obtained by observing a cross section of the semiconductor structure with a Transmission Electron Microscope (TEM). In the present embodiment, the surface height of the step structure 202 is 1290 angstroms, for example, and the gate oxide layer 70 is 1409 angstroms, for example. Wherein the actual shape of the gap 701 and the recessed structure may also refer to fig. 17. In fig. 15, it is evident that the contact between the gate oxide 70 and the substrate 10 is good and the growth of the gate oxide 70 is smooth. In conjunction with fig. 15 and 16, it is apparent that the substrate 10 is hardly damaged, and no abrasive material such as silicon nitride remains at the joint between the projection 201 and the substrate 10.
The invention provides a semiconductor structure and a manufacturing method thereof.A shallow trench isolation structure is formed on a substrate and comprises a convex part. And then forming a substrate oxidation layer on the substrate, forming a protective layer on the substrate oxidation layer, forming a second hard mask layer on the protective layer, and forming a pattern photoresist on the second hard mask layer. And taking the pattern photoresist as a mask, and etching for the first time by using first plasma gas to remove part of the second hard mask layer. And then carrying out second etching by using second plasma gas to remove part of the second hard mask layer and part of the protection layer. And then, carrying out third etching by using second plasma gas, removing all the second hard mask layer and etching part of the etching protection layer. And finally, taking the second hard mask layer as a mask, and removing the etching protection layer and the substrate oxide layer through multi-step wet etching to obtain the substrate surface which is smooth in surface and free of mask material residues. And forming a gate oxide layer on the surface of the substrate, and forming a polycrystalline silicon layer on the gate oxide layer so as to form the semiconductor structure. The semiconductor structure provided by the invention is beneficial to improving the electrical performance of a high-voltage device.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A semiconductor structure, comprising at least:
a substrate;
the shallow trench isolation structure is arranged in the substrate and comprises a convex part, and the convex part exceeds the surface of the substrate;
the stacking structure is arranged on the substrate and the shallow groove isolation structure, and comprises a substrate oxidation layer, a protection layer and a hard mask layer;
a deposition channel in contact with a surface of the substrate and/or the protrusion through the stacked structure, the deposition channel being disposed in a high voltage device region of the substrate, wherein the step of forming the deposition channel includes: thinning the hard mask layer by first plasma gas, etching the hard mask layer by second plasma gas until the hard mask layer corresponding to the surface of the substrate is removed, and etching the hard mask layer and the protective layer by the second plasma gas until the hard mask layer at the joint of the substrate and the convex part is removed;
the step structure is arranged on the convex part and is positioned in the deposition channel, the surface of the step structure is higher than the surface of the substrate, and the height of the step structure is smaller than that of the convex part;
the gate oxide layer is arranged on the substrate, the gate oxide layer is positioned in the deposition channel, and a gap is formed between the gate oxide layer and the step structure; and
and the polycrystalline silicon layer covers the gate oxide layer and the step structure.
2. The semiconductor structure of claim 1, wherein a sidewall of the deposition channel is disposed on the protrusion.
3. The semiconductor structure of claim 1, wherein the stacked structure comprises a substrate oxide layer disposed on the substrate, and the thickness of the substrate oxide layer is less than the height difference between the surface of the step structure and the surface of the substrate.
4. The semiconductor structure of claim 3, wherein said stacked structure comprises a protective layer disposed on said substrate oxide layer, and wherein the sum of the thicknesses of said substrate oxide layer and said protective layer is less than the thickness of said gate oxide layer.
5. The semiconductor structure of claim 4, wherein said stacked structure comprises a hard mask layer disposed on said protective layer.
6. The semiconductor structure according to claim 1, wherein the height of the protruding portion is 1/10 to 1/5 of the depth of the shallow trench isolation structure.
7. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a substrate oxide layer on the substrate;
forming a shallow trench isolation structure on the substrate, wherein the shallow trench isolation structure comprises a convex part, and the convex part exceeds the surface of the substrate;
forming a protective layer on the substrate oxide layer and the shallow trench isolation structure, and forming a hard mask layer on the protective layer;
etching the hard mask layer, the protective layer and the substrate oxide layer for multiple times to form a deposition channel, and forming a step structure on the convex part, wherein the deposition channel is in contact with the surface of the substrate and/or the convex part, and the surface of the step structure is higher than the surface of the substrate; and
forming a gate oxide layer on the substrate, and forming a polycrystalline silicon layer on the gate oxide layer and the step structure;
wherein the step of forming the deposition channel comprises:
thinning the hard mask layer by using first plasma gas;
etching the hard mask layer through second plasma gas until the hard mask layer corresponding to the surface of the substrate in position is removed; and
and etching the hard mask layer and the protective layer by the second plasma gas until the hard mask layer at the joint of the substrate and the convex part is removed.
8. The method of claim 7, wherein the step of forming the deposition channel comprises: and thinning the hard mask layer by using first plasma gas, wherein the etching amount of the thinned hard mask layer is 3/5-4/5 of the thickness of the hard mask layer.
9. The method as claimed in claim 7, wherein after removing the hard mask layer, the substrate oxide layer and the protective layer are etched, and the protrusion is etched simultaneously until the substrate oxide layer is removed.
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| CN1518089A (en) * | 2003-01-16 | 2004-08-04 | ���ǵ�����ʽ���� | Semiconductor device with multi-grid insulating barrier and its manufacturing method |
| CN102054778A (en) * | 2009-11-03 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of complementary metal oxide semiconductor structure |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN114038744A (en) * | 2021-10-26 | 2022-02-11 | 上海华力集成电路制造有限公司 | MOS transistor manufacturing method and MOS transistor |
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| CN1518089A (en) * | 2003-01-16 | 2004-08-04 | ���ǵ�����ʽ���� | Semiconductor device with multi-grid insulating barrier and its manufacturing method |
| CN102054778A (en) * | 2009-11-03 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of complementary metal oxide semiconductor structure |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN114038744A (en) * | 2021-10-26 | 2022-02-11 | 上海华力集成电路制造有限公司 | MOS transistor manufacturing method and MOS transistor |
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