KR20040061822A - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
- Publication number
- KR20040061822A KR20040061822A KR1020020088122A KR20020088122A KR20040061822A KR 20040061822 A KR20040061822 A KR 20040061822A KR 1020020088122 A KR1020020088122 A KR 1020020088122A KR 20020088122 A KR20020088122 A KR 20020088122A KR 20040061822 A KR20040061822 A KR 20040061822A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- pad
- nitride layer
- pad nitride
- semiconductor substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 21
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 4
- 229910019142 PO4 Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 2
- 239000010452 phosphate Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 고밀도 소자의 얕은 트랜치 소자분리(shallow trench isolation; 이하 STI라 칭함) 공정에서 기판의 모트(moat) 발생을 억제하여 셀의 문턱전압 감소와, 임계크기 손실을 방지하고, 게이트 잔류물에 의한 단락을 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a shallow trench isolation (STI) process of a high-density device, it is possible to reduce the threshold voltage of a cell by suppressing the generation of moat of a substrate, The present invention relates to a method for manufacturing a semiconductor device, which can prevent a size loss and prevent a short circuit caused by a gate residue, thereby improving process yield and device reliability.
일반적으로 반도체소자는 소자가 형성되는 활성영역과, 이들을 분리하는 소자분리 영역으로 구분할 수 있으며, 소자분리영역이 소자의 전체 면적에서 차지하는 비율이 크므로 소자의 고집적화를 위해서는 소자분리영역의 축소가 필요하다.In general, semiconductor devices can be divided into active regions in which devices are formed and device isolation regions separating them, and since the device isolation region occupies a large portion of the entire area of the device, it is necessary to reduce the device isolation region for high integration. Do.
고집적 소자에서는 기판에 얕은 트랜치를 형성하고 이를 절연막으로 메우는 STI 방법이 많이 사용되고 있다.In high-integration devices, STI methods that form shallow trenches in a substrate and fill them with insulating films are widely used.
더욱이 고집적-초미세화된 소자에서는 공정 능력이나 신뢰도의 향상이 요구되고 있으며, DRAM 소자의 경우 STI 및 게이트 형성 공정에서 트랜지스터 성능 및 안정성의 대부분이 결정된다.Furthermore, highly integrated and ultra-miniaturized devices require increased process capability and reliability, while DRAM devices typically determine most of transistor performance and stability in STI and gate formation processes.
도 1a 내지 도 1e은 종래 기술에 따른 반도체소자의 제조 공정도이다.1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.
먼저, 반도체기판(10)상에 패드산화막(12)과 패드질화막(14)을 순차적으로 형성하고, 소자분리 마스크(도시되지 않음)를 이용한 사진식각 공정으로 상기 패드질화막(14)과 패드산화막(12)을 식각하여 패드질화막(14) 패턴과 패드산화막(12) 패턴을 형성한 후, 상기 패드질화막(14) 패턴에 의해 노출되어있는 반도체기판(10)을 일정 깊이 식각하여 트랜치(16)를 형성한다. (도 1a 참조).First, the pad oxide layer 12 and the pad nitride layer 14 are sequentially formed on the semiconductor substrate 10, and the pad nitride layer 14 and the pad oxide layer 14 are formed by a photolithography process using an element isolation mask (not shown). 12 is etched to form the pad nitride film 14 pattern and the pad oxide film 12 pattern, and then the trench 16 is etched by etching the semiconductor substrate 10 exposed by the pad nitride film 14 pattern to a predetermined depth. Form. (See FIG. 1A).
그후, 상기 트랜치(16)의 내벽에 웰산화막(18)을 형성하고, 전면에 선형 질화막(20)을 도포한 후, 상기 구조의 전표면에 필드산화막(22)을 도포한다. (도 1b 참조).Thereafter, the well oxide film 18 is formed on the inner wall of the trench 16, the linear nitride film 20 is applied to the entire surface, and then the field oxide film 22 is applied to the entire surface of the structure. (See FIG. 1B).
그다음 상기 필드산화막(22)과 하부의 패드질화막(14)의 일부 두께를 화학기계적 연마(CMP)등의 방법으로 평탄화 식각하고, (도 1c 참조), 상기 패드질화막(14)을 제거하여 소자분리 공정을 완성한다. 이때 과식각에 의해 선형질화막(20)이 반도체기판(10) 표면 보다 낮아지게된다. (도 1d 참조).Then, the thickness of the field oxide film 22 and the lower part of the pad nitride film 14 is flattened and etched by a chemical mechanical polishing (CMP) method (see FIG. 1C), and the device is removed by removing the pad nitride film 14. Complete the process. At this time, the linear nitride film 20 is lower than the surface of the semiconductor substrate 10 due to overetching. (See FIG. 1D).
그후, 상기 패드산화막(12) 제거등의 공정을 거치며 선형질화막(20) 양측의 산화막 재질이 식각되어 모트가 발생된다. (도 1e 참조).Thereafter, the oxide material on both sides of the linear nitride film 20 is etched through a process such as removing the pad oxide film 12 to generate a mort. (See FIG. 1E).
상기와 같은 종래 기술에 따른 반도체 소자의 제조방법은 STI 공정에서 패드질화막 및 패트 산화막 제거 공정에서 과식각이 진행되어 선형 질화막의 양측으로 깊은 모트를 형성시키며, 이로 인하여 셀 문턱전압이 감소되고, 활성영역의 임계크기가 감소하며, 모트 영역에서의 게이트전극 물질의 식각 잔류물이 남게되는 등 여러 가지 문제점을 야기 시킨다.In the method of manufacturing a semiconductor device according to the prior art as described above, the over-etching is performed in the pad nitride film and the pad oxide film removing process in the STI process to form a deep mort on both sides of the linear nitride film, thereby reducing the cell threshold voltage and active The critical size of the region is reduced and causes a number of problems such as the etching residue of the gate electrode material in the mote region.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 STI 공정에서 페드질화막의 일부 두께를 인산용액으로 제거하여 선형질화막의 패스를 길게하여 소자분리 영역 에지부에 형성되는 모트를 방지하여 경계 지역에서의 불량 발생을 방지하고 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to remove a part of the thickness of the ped nitride film with a phosphate solution in the STI process to lengthen the path of the linear nitride film to prevent the mort formed on the edge of the device isolation region Accordingly, the present invention provides a method of manufacturing a semiconductor device that can prevent defects in the boundary area and improve process yield and device operation reliability.
도 1a 내지 도 1e은 종래 기술에 따른 반도체소자의 제조공정도.1a to 1e is a manufacturing process diagram of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 제조공정도.2a to 2e is a manufacturing process diagram of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 반도체기판 12 : 패드산화막10 semiconductor substrate 12 pad oxide film
14 : 패드질화막 16 : 트랜치14 pad nitride film 16 trench
18 : 웰 산화막 20 : 선형 질화막18 well oxide film 20 linear nitride film
22 : 필드산화막 24 : 모트22: field oxide film 24: mort
본발명은 상기와 같은 목적을 달성하기 위한 것으로서, 본발명에 따른 반도체소자 제조방법의 특징은,The present invention is to achieve the above object, the characteristics of the semiconductor device manufacturing method according to the present invention,
반도체소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device,
반도체기판상에 패드산화막과 패드질화막을 순차적으로 형성하는 공정과,Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate;
상기 패드질화막과 패드산화막을 소자분리마스크를 이용한 패턴닝 공정으로 선택 식각하여 반도체기판의 소자분리영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴을 형성하는 공정과,Selectively etching the pad nitride film and the pad oxide film by a patterning process using a device isolation mask to form a pad nitride film pattern exposing a predetermined portion of the semiconductor substrate as a device isolation region;
상기 패드질화막에 의해 노출되어있는 반도체기판을 일정 두께 식각하여 트랜치를 형성하는 공정과,Etching the semiconductor substrate exposed by the pad nitride layer to form a trench by a predetermined thickness;
상기 패드질화막 패턴을 인산용액을 이용하여 등방성 식각하여 트랜치 에지부의 반도체기판을 노출시키는 공정과,Isotropically etching the pad nitride layer pattern using a phosphoric acid solution to expose a semiconductor substrate at a trench edge;
상기 트랜치의 내벽이 웰 산화막을 형성하는 공정과,Forming a well oxide film on an inner wall of the trench;
상기 구조의 전표면에 선형 질화막을 형성하는 공정과,Forming a linear nitride film on the entire surface of the structure;
상기 트랜치를 메우는 필드산화막을 형성하는 공정을 구비함에 있다.And forming a field oxide film filling the trench.
또한 본 발명의 다른 특징은, 상기 인산용액의 식각공정은 140∼160℃에서, 50∼200Å 두께 실시하는 것을 특징으로 한다.Another feature of the present invention is characterized in that the etching step of the phosphoric acid solution is carried out at 140 to 160 ° C, with a thickness of 50 to 200 mm 3.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 제조공정도이다.2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 실리콘 웨이퍼등의 반도체기판(10)상에 소자분리 마스크(도시되지 않음)를 이용하여 패턴닝된 패드질화막(14) 패턴과 패드산화막(12) 패턴을 형성하고, 상기 패드질화막(14) 패턴에 의해 노출되어있는 반도체기판(10)을 일정 깊이 식각하여 트랜치(16)를 형성한다. (도 2a 참조).First, a patterned pad nitride film 14 pattern and a pad oxide film 12 pattern are formed on a semiconductor substrate 10 such as a silicon wafer using an isolation mask (not shown), and the pad nitride film 14 is formed. The trench 16 is formed by etching the semiconductor substrate 10 exposed by the pattern to a predetermined depth. (See FIG. 2A).
그다음 인산 용액을 이용한 습식 식각 방법으로 상기 패드질화막(14) 패턴을 등방성식각하여 그 크기를 감소시키면, 상기 트랜치(16) 에지부의 반도체기판(10) 모서리가 노출된다. 여기서 상기 식각 공정을 인산 용액을 이용하여 산화막과 질화막의 식각선택비를 고려한 최적의 온도, 예를 들어 140∼160℃ 범위 사이에서, 50∼200Å 정도 두께를 실시한다. (도 2b 참조).Then, when the pad nitride layer 14 is isotropically etched by a wet etching method using a phosphoric acid solution to reduce its size, the edge of the semiconductor substrate 10 of the edge portion of the trench 16 is exposed. In the etching process, a phosphoric acid solution is used to perform a thickness of about 50 to 200 kPa between an optimum temperature, for example, in the range of 140 to 160 ° C, in consideration of the etching selectivity of the oxide film and the nitride film. (See FIG. 2B).
그후, 상기 트랜치(16)의 내벽에 웰 산화막(18)을 형성하고, 상기 구조의 전표면에 선형 질화막(20)을 10∼500Å 두께로 형성한다. 이때 습식각에 의해 선형질화막(20)의 트랜치(16) 에지 상부 패스가 길어져 있다. (도 2c 참조).Thereafter, a well oxide film 18 is formed on the inner wall of the trench 16, and a linear nitride film 20 is formed on the entire surface of the structure to a thickness of 10 to 500 kHz. At this time, the upper path of the edge 16 of the trench 16 of the linear nitride film 20 is extended by wet etching. (See FIG. 2C).
그다음 상기 트랜치(16)를 메우는 필드산화막(22)을 도포하고, CMP 방법으로 상부를 연마하여 평탄화한 후, (도 2d 참조), 상기 패드질화막(14) 패턴을 제거한다. 이때 상기 선형 질화막(20)이 트랜치(16)의 에지 상부에 까지 형성되어 있어 모트 생성이 방지된다. (도 2e 참조).Then, the field oxide film 22 filling the trench 16 is applied, and the top is polished and planarized by a CMP method (see FIG. 2D), and then the pad nitride film 14 pattern is removed. At this time, the linear nitride film 20 is formed on the edge of the trench 16 to prevent the generation of motes. (See FIG. 2E).
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은, STI 공정에서 트랜치 형성후 패드질화막의 일부 두께를 인산용액을 이용하여 등방성식각하여 트랜치 에지부를 노출시킨 후 선형 질화막을 형성하여 에지 상부에서의 선형질화막 패스를 길게하여 모트 생성을 방지하였으므로, 모트에 의해 후속 식각 공정에서의 잔류물 발생이 방지되고 라인의 단락이 방지되며, 셀의 문턱전압 감소와 활성영역의 임계크기 감소를 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, after forming the trench in the STI process, a portion of the pad nitride film is isotropically etched using a phosphate solution to expose the trench edge portion, and then a linear nitride film is formed to form an upper portion of the edge. By preventing the generation of motes by lengthening the linear nitride film path at, the mott prevents residues from subsequent etching processes, prevents short circuits, and reduces the threshold voltage of the cell and the threshold size of the active area. There is an advantage that can improve the process yield and the reliability of the device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020088122A KR20040061822A (en) | 2002-12-31 | 2002-12-31 | Method for fabricating of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020088122A KR20040061822A (en) | 2002-12-31 | 2002-12-31 | Method for fabricating of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040061822A true KR20040061822A (en) | 2004-07-07 |
Family
ID=37353314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020088122A KR20040061822A (en) | 2002-12-31 | 2002-12-31 | Method for fabricating of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040061822A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100733558B1 (en) * | 2005-08-23 | 2007-06-29 | 후지쯔 가부시끼가이샤 | Method for fabricating semiconductor device |
| US7601576B2 (en) | 2005-08-23 | 2009-10-13 | Fujitsu Microelectronics Limited | Method for fabricating semiconductor device |
-
2002
- 2002-12-31 KR KR1020020088122A patent/KR20040061822A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100733558B1 (en) * | 2005-08-23 | 2007-06-29 | 후지쯔 가부시끼가이샤 | Method for fabricating semiconductor device |
| US7601576B2 (en) | 2005-08-23 | 2009-10-13 | Fujitsu Microelectronics Limited | Method for fabricating semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20040096365A (en) | Manufacturing method for semiconductor device | |
| KR100845103B1 (en) | Method of fabricating the semiconductor device | |
| KR100557541B1 (en) | Manufacturing method for semiconductor device | |
| JP2008004881A (en) | Method of manufacturing element isolation structure section | |
| US7323394B2 (en) | Method of producing element separation structure | |
| KR20040061822A (en) | Method for fabricating of semiconductor device | |
| KR100510772B1 (en) | Formation method of silicon on insulator substrate for semiconductor | |
| KR100831671B1 (en) | Method for forming isolation of semiconductor device | |
| KR100895388B1 (en) | Method for fabricating of semiconductor device | |
| KR100905163B1 (en) | Method for fabricating of semiconductor device | |
| KR20030049783A (en) | Method of forming an isolation film in semiconductor device | |
| KR100408863B1 (en) | Method of forming a gate oxide in a semiconductor device | |
| KR100557562B1 (en) | Method for fabricating of semiconductor device | |
| KR20050014166A (en) | Manufacturing method for semiconductor device | |
| KR100492695B1 (en) | Manufacturing method for semiconductor device | |
| KR100575616B1 (en) | Method for forming borderless contact hole in a semiconductor device | |
| KR20050014161A (en) | Manufacturing method for semiconductor device | |
| KR20040102717A (en) | Manufacturing method for semiconductor device | |
| KR20040061820A (en) | Method for fabricating of semiconductor device | |
| KR20050106879A (en) | Method for manufacturing gate spacer in semiconductor device | |
| KR20050002444A (en) | Manufacturing method for semiconductor device | |
| KR20000045448A (en) | Method for forming isolation region of semiconductor device | |
| KR20040001228A (en) | Method for manufacturing isolation layer in semiconductor device | |
| KR20050002442A (en) | Manufacturing method for semiconductor device | |
| KR20040055468A (en) | Method for forming isolation layer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |