KR20050106879A - Method for manufacturing gate spacer in semiconductor device - Google Patents
Method for manufacturing gate spacer in semiconductor device Download PDFInfo
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- KR20050106879A KR20050106879A KR1020040031939A KR20040031939A KR20050106879A KR 20050106879 A KR20050106879 A KR 20050106879A KR 1020040031939 A KR1020040031939 A KR 1020040031939A KR 20040031939 A KR20040031939 A KR 20040031939A KR 20050106879 A KR20050106879 A KR 20050106879A
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- gate spacer
- insulating layer
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 30
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 2
- SEOYNUHKXVGWFU-UHFFFAOYSA-N mu-oxidobis(oxidonitrogen) Chemical compound O=NON=O SEOYNUHKXVGWFU-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트스페이서 형성시 반도체 기판의 식각손실을 방지하는데 적합한 반도체 소자의 게이트스페이서 제조 방법을 제공하기 위한 것으로, 본 발명의 게이트스페이서 제조 방법은 반도체 기판 상부에 게이트패턴을 형성하는 단계, 상기 게이트패턴 상부에 제1절연막, 질화막계 제2절연막 및 제3절연막을 차례로 형성하는 단계, 상기 제2절연막에 대한 높은 식각선택비를 갖는 레시피로 상기 제3절연막을 건식식각하여 제1게이트스페이서를 형성하는 단계, 상기 제2절연막을 선택적으로 습식식각하여 제2게이트스페이서를 형성하는 단계, 및 상기 제1절연막을 선택적으로 습식식각하여 제3게이트스페이서를 형성하는 단계를 포함한다. The present invention provides a method for manufacturing a gate spacer of a semiconductor device suitable for preventing the etching loss of the semiconductor substrate when forming the gate spacer, the method of manufacturing a gate spacer of the present invention comprises the steps of forming a gate pattern on the semiconductor substrate, the gate Sequentially forming a first insulating layer, a nitride based second insulating layer, and a third insulating layer on the pattern, and dry etching the third insulating layer using a recipe having a high etching selectivity with respect to the second insulating layer to form a first gate spacer. And selectively wet etching the second insulating layer to form a second gate spacer, and selectively wet etching the first insulating layer to form a third gate spacer.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 게이트스페이서 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a gate spacer of a semiconductor device.
잘 알려진 바와 같이, 게이트스페이서(Gate spacer)는 반도체 소자의 고집적화가 진행되면서 채널길이의 감소에 따라 숏채널 효과(short channel effect)가 발생되는 것을 방지하기 위한 하나의 방법인 LDD(Lightly Doped Drain) 영역의 형성을 위해 도입하게 되었다. 그런데, 이러한 게이트 스페이서는 반도체 소자의 고집적화가 가속화되면서 다양한 반도체 제조 기술들이 개발됨에 따라, 최근에 들어서는 LDD 영역을 형성하기 위한 수단 이외에, 인접하는 게이트 전극들간의 전기적 차단 수단으로서의 기능을 행하게 되었다. As is well known, a gate spacer is a lightly doped drain (LDD), which is a method for preventing short channel effects from occurring as the channel length decreases as the integration of semiconductor devices increases. It was introduced for the formation of regions. However, as the high integration of semiconductor devices has accelerated the development of various semiconductor fabrication techniques, such gate spacers have recently functioned as electrical blocking means between adjacent gate electrodes, in addition to means for forming LDD regions.
상기한 게이트스페이서로는 주로 실리콘질화막(Si3N4)을 사용하는데, 실리콘질화막은 높은 밀도를 갖는 절연막이라는 점과 실리콘산화막에 대한 우수한 식각선택비를 갖는다는 점 때문에, 반도체 소자의 제조에서 다양한 용도로 사용된다.As the gate spacer, a silicon nitride film (Si 3 N 4 ) is mainly used. Since the silicon nitride film is an insulating film having a high density and has an excellent etch selectivity with respect to the silicon oxide film, the silicon nitride film has various characteristics in the manufacture of semiconductor devices. Used for the purpose.
상기와 같은 특성들 때문에, 실리콘질화막은 게이트스페이서를 형성하는데 주로 사용된다. 즉, 불순물이 소자 특성에 매우 중요한 역할을 하는 게이트산화막으로 침투하는 것을 방지하기 위해서, 게이트전극을 둘러싸는 게이트스페이서를 실리콘질화막으로 형성하는 것이 바람직하다. Because of these characteristics, silicon nitride films are mainly used to form gate spacers. In other words, in order to prevent impurities from penetrating into the gate oxide film, which plays a very important role in device characteristics, it is preferable to form a gate spacer surrounding the gate electrode with a silicon nitride film.
도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 게이트스페이서 제조 방법을 도시한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a gate spacer of a semiconductor device according to the prior art.
도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 게이트산화막(12), 폴리실리콘막(13), 텅스텐막(14) 및 게이트하드마스크질화막(15)의 순서로 적층된 게이트전극 패턴을 형성한다.As shown in FIG. 1A, a gate electrode pattern stacked on the semiconductor substrate 11 in the order of the gate oxide film 12, the polysilicon film 13, the tungsten film 14, and the gate hard mask nitride film 15 is formed. Form.
다음으로, 게이트전극 패턴을 포함한 전면에 제1실리콘산화막(16), 실리콘질화막(17), 제2실리콘산화막(18)을 차례로 증착한다.Next, the first silicon oxide film 16, the silicon nitride film 17, and the second silicon oxide film 18 are deposited in order on the entire surface including the gate electrode pattern.
도 1b에 도시된 바와 같이, 통상적인 건식식각(Dry etch)을 이용하여 제1실리콘산화막(16), 실리콘질화막(17), 제2실리콘산화막(18)을 동시에 건식식각하여 게이트전극 패턴의 양측벽에 접하는 게이트스페이서(100)를 형성한다. 따라서, 게이트스페이서는 제1실리콘산화막(16), 실리콘질화막(17) 및 제2실리콘산화막(18)의 삼중막으로 된다.As shown in FIG. 1B, the first silicon oxide layer 16, the silicon nitride layer 17, and the second silicon oxide layer 18 are simultaneously dry-etched by using a conventional dry etch, and thus, both sides of the gate electrode pattern. A gate spacer 100 in contact with the wall is formed. Therefore, the gate spacer serves as a triple layer of the first silicon oxide film 16, the silicon nitride film 17, and the second silicon oxide film 18.
그러나, 상술한 종래 기술은 게이트스페이서 형성을 위한 건식식각시 반도체 기판 표면 상에 실리콘질화막 및 실리콘산화막의 잔류물이 남지 않도록 과도식각(over etch)을 진행해야만 하고, 이러한 과도식각시 반도체 기판(11)의 식각손실(19)이 불가피하게 발생하는 문제가 있다.However, the above-described prior art has to overetch so that the residue of the silicon nitride film and the silicon oxide film does not remain on the surface of the semiconductor substrate during the dry etching for forming the gate spacer, and the semiconductor substrate 11 during such overetching ), There is a problem that inevitably occurs in the etching loss (19).
위와 같은 반도체 기판(11)의 식각손실(19)은 주변회로지역에 형성되는 트랜지스터의 특성을 열화시킬 수 있는 원인으로 작용할 수 있으며, 특히 소자의 집적화에 따른 PMOS 트랜지스터의 얕은 접합(Shallow junction)에 악영향을 미칠 수 있을 만큼인 200Å 이상의 두께로 발생되고 있다. The etch loss 19 of the semiconductor substrate 11 as described above may act as a cause of deterioration of the characteristics of the transistors formed in the peripheral circuit area, and particularly in the shallow junction of the PMOS transistors due to the integration of devices. It is generated to a thickness of 200Å or more, which may adversely affect.
또한, 종래기술은 식각장비에 의해 반도체기판의 손실정도가 불균일하게 발생한다.In addition, in the prior art, the loss degree of the semiconductor substrate is unevenly generated by the etching equipment.
도 2a는 종래 기술에 따른 NMOS 트랜지스터에서의 게이트스페이서형성후 반도체기판의 식각손실을 나타낸 사진이고, 도 2b는 종래 기술에 따른 PMOS 트랜지스터에서의 게이트스페이서형성후 반도체기판의 식각손실을 나타낸 사진이다.FIG. 2A is a photograph showing etching loss of a semiconductor substrate after gate spacer formation in an NMOS transistor according to the prior art, and FIG. 2B is a photograph showing etching loss of a semiconductor substrate after gate spacer formation in a PMOS transistor according to the prior art.
도 2a 및 도 2b에 도시된 바와 같이, NMOS 트랜지스터와 PMOS 트랜지스터 모두 게이트스페이서 형성후 반도체 기판의 식각손실이 0.0186㎛, 0.0232㎛ 정도로 발생하고 있다. As shown in FIGS. 2A and 2B, both the NMOS transistor and the PMOS transistor have an etching loss of about 0.0186 μm and 0.0232 μm after the gate spacer is formed.
상술한 것처럼, 종래 기술에서 게이트스페이서를 형성하기 위한 건식식각시 반도체 기판의 식각손실이 발생하는 이유는, 식각시 사용되는 식각가스가 실리콘산화막과 실리콘질화막에 대해 막 상호간에 식각선택비를 갖고 있지 않은 가스를 사용하기 때문이다. As described above, in the prior art, the reason why the etching loss of the semiconductor substrate occurs during the dry etching for forming the gate spacer is that the etching gas used during the etching has the etching selectivity between the films for the silicon oxide film and the silicon nitride film. This is because the gas is not used.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 게이트스페이서 형성시 반도체 기판의 식각손실을 방지하는데 적합한 반도체 소자의 게이트스페이서 제조 방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a gate spacer of a semiconductor device suitable for preventing the etching loss of the semiconductor substrate when forming the gate spacer.
상기 목적을 달성하기 위한 본 발명의 게이트스페이서 제조 방법은 반도체 기판 상부에 게이트패턴을 형성하는 단계, 상기 게이트패턴 상부에 제1절연막, 질화막계 제2절연막 및 제3절연막을 차례로 형성하는 단계, 상기 제2절연막에 대한 높은 식각선택비를 갖는 레시피로 상기 제3절연막을 건식식각하여 제1게이트스페이서를 형성하는 단계, 상기 제2절연막을 선택적으로 습식식각하여 제2게이트스페이서를 형성하는 단계, 및 상기 제1절연막을 선택적으로 습식식각하여 제3게이트스페이서를 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 제1 및 제3절연막은 실리콘산화막으로 형성하고, 상기 제2절연막은 실리콘질화막으로 형성하는 것을 특징으로 하며, 상기 제1게이트스페이서를 형성하는 단계는, 상기 높은 식각선택비를 갖도록 C4F8, C2H2F2 또는 C3F 6 중에서 선택된 하나의 가스를 플라즈마화하여 상기 제3절연막을 식각하는 것을 특징으로 하고, 상기 제2게이트스페이서 형성시 인산용액을 이용하여 상기 제2절연막을 식각하는 것을 특징으로 하며, 상기 제3게이트스페이서 형성시 불산을 이용하여 상기 제3절연막을 식각하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a gate spacer, which includes forming a gate pattern on an upper surface of a semiconductor substrate, sequentially forming a first insulating layer, a nitride-based second insulating layer, and a third insulating layer on the gate pattern; Dry etching the third insulating layer with a recipe having a high etching selectivity with respect to a second insulating layer to form a first gate spacer, selectively wet etching the second insulating layer to form a second gate spacer, and And selectively wet etching the first insulating layer to form a third gate spacer, wherein the first and third insulating layers are formed of a silicon oxide layer, and the second insulating layer is formed of a silicon nitride layer. Characterized in that, the step of forming the first gate spacer, C 4 F 8 , C 2 H to have the high etching selectivity And etching the third insulating layer by plasmalizing one gas selected from 2 F 2 or C 3 F 6 , and etching the second insulating layer using a phosphoric acid solution when forming the second gate spacer. The third insulating layer may be etched using hydrofluoric acid when forming the third gate spacer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체 소자의 게이트스페이서 제조 방법을 도시한 공정 단면도이다. 이하, 반도체소자는 DRAM에서 주변회로영역에 형성되는 트랜지스터이다. 3A to 3D are cross-sectional views illustrating a method of manufacturing a gate spacer of a semiconductor device in accordance with an embodiment of the present invention. Hereinafter, a semiconductor device is a transistor formed in a peripheral circuit region in a DRAM.
도 3a에 도시된 바와 같이, 반도체 기판(21) 상에 게이트산화막(22), 폴리실리콘막(23), 텅스텐막(24) 및 게이트하드마스크질화막(25)의 순서로 적층된 게이트전극 패턴을 형성한다.As shown in FIG. 3A, a gate electrode pattern stacked on the semiconductor substrate 21 in the order of the gate oxide film 22, the polysilicon film 23, the tungsten film 24, and the gate hard mask nitride film 25 is formed. Form.
이때, 게이트전극 패턴의 형성 방법은 먼저 반도체 기판(21) 상에 게이트산화막(22)을 형성한 후, 게이트산화막 상에 폴리실리콘막(23), 텅스텐막(24) 및 게이트하드마스크질화막(25)을 차례로 증착한다. 그리고 나서, 게이트하드마스크질화막(25) 상에 게이트전극을 패터닝하기 위한 감광막 마스크(도시 생략)를 형성하고, 감광막마스크를 식각마스크로 게이트하드마스크질화막(25)을 식각한 후에, 감광막마스크를 제거하며, 게이트하드마스크질화막(25)을 식각마스크로 하여 텅스텐막(24), 폴리실리콘막(23) 및 게이트산화막(22)을 동시에 패터닝한다.In this case, the gate electrode pattern is formed by first forming a gate oxide film 22 on the semiconductor substrate 21, and then, a polysilicon film 23, a tungsten film 24, and a gate hard mask nitride film 25 on the gate oxide film. ) In order. Then, a photoresist mask (not shown) is formed on the gate hard mask nitride film 25 for patterning the gate electrode, and the photoresist film mask is removed after etching the gate hard mask nitride film 25 using the photoresist mask as an etch mask. The tungsten film 24, the polysilicon film 23, and the gate oxide film 22 are simultaneously patterned using the gate hard mask nitride film 25 as an etching mask.
다음으로, 게이트전극 패턴을 포함한 전면에 제1실리콘산화막(26), 실리콘질화막(27), 제2실리콘산화막(28)을 차례로 증착한다.Next, the first silicon oxide film 26, the silicon nitride film 27, and the second silicon oxide film 28 are sequentially deposited on the entire surface including the gate electrode pattern.
여기서, 제1실리콘산화막(26)은 실리콘질화막(27)의 후속 습식식각시 게이트전극패턴 중의 게이트하드마스크질화막(25)이 식각되는 것을 방지하기위한 것이며, 실리콘질화막(27)은 제2실리콘산화막의 식각공정시 식각배리어 역할을 하고, 제2실리콘산화막(28)은 실질적으로 게이트스페이서 물질이다. Here, the first silicon oxide film 26 is to prevent the gate hard mask nitride film 25 from being etched in the gate electrode pattern during the subsequent wet etching of the silicon nitride film 27, and the silicon nitride film 27 is the second silicon oxide film. Serves as an etching barrier during the etching process, and the second silicon oxide film 28 is substantially a gate spacer material.
이때, 게이트스페이서 물질로는 제2실리콘산화막(28)외에 ON(Oxide/Nitride) 또는 ONONO(Oxide/Nitride/Oxide/Nitride/Oxide)로 형성할 수도 있다.In this case, the gate spacer material may be formed of ON (Oxide / Nitride) or ONONO (Oxide / Nitride / Oxide / Nitride / Oxide) in addition to the second silicon oxide layer 28.
위와 같이, 실리콘질화막(27)은 식각배리어 역할을 수행해야 하므로 그 두께는 50Å∼200Å이 바람직하고, 그리고, 제1실리콘산화막(26)은 게이트하드마스크질화막(25)을 충분히 보호하도록 50Å∼100Å 두께로 실링(sealing)하는 것이 바람직하다.As described above, since the silicon nitride film 27 should serve as an etching barrier, the thickness of the silicon nitride film 27 is preferably 50 kPa to 200 kPa, and the first silicon oxide film 26 is 50 kPa to 100 kPa to sufficiently protect the gate hard mask nitride film 25. It is desirable to seal to thickness.
도 3b에 도시된 바와 같이, 제2실리콘산화막(28)을 먼저 건식식각하여 제2실리콘산화막으로 된 제1게이트스페이서(28a)를 형성한다. 이때, 실리콘질화막(27)을 식각배리어로 이용하며, 제2실리콘산화막(28)의 건식식각시 실리콘질화막(27)에 대한 높은 식각선택비를 이용하므로써 실리콘질화막(27)에서 멈추도록 한다.As shown in FIG. 3B, the second silicon oxide film 28 is first dry etched to form a first gate spacer 28a made of the second silicon oxide film. At this time, the silicon nitride film 27 is used as an etching barrier and the silicon nitride film 27 is stopped by using a high etching selectivity with respect to the silicon nitride film 27 during dry etching of the second silicon oxide film 28.
즉, 실리콘질화막(27)에 대한 높은 식각선택비를 갖는 레시피(recipe)로 제2실리콘산화막(28)을 건식식각한다.That is, the second silicon oxide film 28 is dry etched with a recipe having a high etching selectivity with respect to the silicon nitride film 27.
위와 같은 제2실리콘산화막(28)에 대한 식각 공정시의 레시피는, 실리콘질화막(27)에 대해 높은 식각선택비를 갖는 식각가스로 C4F8, C2H2 F2 또는 C3F6 중에서 선택된 하나의 가스를 플라즈마화하여 이용하며, 식각챔버의 압력은 30mtorr∼100mtorr로 유지하고, 플라즈마를 유도하기 위한 RF 파워는 500W∼1500W로 한다.The above recipe in the etching process for the second silicon oxide film 28 is an etching gas having a high etching selectivity with respect to the silicon nitride film 27, C 4 F 8 , C 2 H 2 F 2 or C 3 F 6 One gas selected from among them is converted into a plasma, and the pressure of the etching chamber is maintained at 30 mtorr to 100 mtorr, and the RF power for inducing plasma is 500W to 1500W.
도 3c에 도시된 바와 같이, 습식 식각(wet etch)을 통해 실리콘질화막(27)을 제거하여 실리콘질화막으로 된 제2게이트스페이서(27a)를 형성한다. 이때, 제1게이트스페이서(28a)와 제1실리콘산화막(26)이 식각배리어 역할을 하므로 제1게이트스페이서(28a)가 덮는 부분은 식각되지 않고 게이트전극 패턴 상부 및 반도체 기판(21) 상부의 실리콘질화막(27)만 선택적으로 식각된다.As shown in FIG. 3C, the silicon nitride layer 27 is removed by wet etching to form a second gate spacer 27a formed of the silicon nitride layer. At this time, since the first gate spacer 28a and the first silicon oxide layer 26 serve as an etching barrier, the portion covered by the first gate spacer 28a is not etched and the silicon on the gate electrode pattern and the semiconductor substrate 21 is not etched. Only the nitride film 27 is selectively etched.
여기서, 실리콘산화막질인 제1게이트스페이서(28a)와 제1실리콘산화막(26)을 제거하지 않고 실리콘질화막(27)만을 선택적으로 제거할 수 있는 습식식각 용액은 인산(H3PO4) 용액이 있다. 한편, 실리콘질화막(27)을 습식식각할 때 하부에 제1실리콘산화막(26)이 존재하므로 반도체 기판(21) 표면으로 인산용액이 흘러들어가는 것을 방지할 수 있다.Here, the wet etching solution capable of selectively removing only the silicon nitride layer 27 without removing the first gate spacer 28a and the first silicon oxide layer 26, which is silicon oxide, is phosphoric acid (H 3 PO 4 ) solution. have. Meanwhile, when the silicon nitride layer 27 is wet etched, since the first silicon oxide layer 26 is present at the lower portion, it is possible to prevent the phosphoric acid solution from flowing into the surface of the semiconductor substrate 21.
위와 같이, 실리콘질화막(27)을 습식식각을 통해 제거하면 반도체 기판 표면이 식각되는 것을 감소 또는 방지할 수 있다. As described above, when the silicon nitride layer 27 is removed through wet etching, the surface of the semiconductor substrate may be reduced or prevented from being etched.
도 3d에 도시된 바와 같이, 제1실리콘산화막(26)을 선택적으로 제거하여 게이트전극 패턴에 직접 접하는 제3게이트스페이서(26a)를 형성한다.As shown in FIG. 3D, the first silicon oxide film 26 is selectively removed to form a third gate spacer 26a directly in contact with the gate electrode pattern.
이때, 제1실리콘산화막(26)은 불산(HF) 세정을 이용하여 제거하는데, 불산세정을 이용하여 제1실리콘산화막(26)을 식각하면 반도체기판(21)에 식각손실을 주지 않는다.In this case, the first silicon oxide film 26 is removed by using hydrofluoric acid (HF) cleaning. When the first silicon oxide film 26 is etched by using hydrofluoric acid (HF) cleaning, the semiconductor substrate 21 is not etched.
상기 제3게이트스페이서(26a) 형성시 제1게이트스페이서(28a)가 일부 식각될 수도 있으나, 얇게 형성된 제1실리콘산화막(26)을 식각하므로 그 식각손실량은 매우 적다. 그리고, 불산(HF)은 실리콘질화막을 식각하지 못하는 용액이므로 게이트전극패턴중의 게이트하드마스크질화막(25)이나 제2게이트스페이서(27a)는 식각하지 않는다.Although the first gate spacer 28a may be partially etched when the third gate spacer 26a is formed, the amount of etch loss is very small since the thin first silicon oxide layer 26 is etched. Since the hydrofluoric acid (HF) is a solution that cannot etch the silicon nitride film, the gate hard mask nitride film 25 or the second gate spacer 27a in the gate electrode pattern is not etched.
상술한 실시예에서는 실리콘질화막을 습식식각을 통해 식각하여 제2게이트스페이서를 형성하였으나, 다른 방법으로 소프트식각법을 이용할 수도 있으며, 이때, 실리콘기판의 손실을 최소화하기 위해 소프트식각은 이소트로픽(isotropic)하게 진행한다.In the above-described embodiment, the silicon nitride film is etched through wet etching to form the second gate spacer. Alternatively, the soft etching method may be used. In this case, the soft etching isotropic to minimize the loss of the silicon substrate. To proceed.
본 발명과 같이 게이트스페이서를 형성하면 반도체기판의 손실을 100Å 미만으로 할 수 있다.If the gate spacer is formed as in the present invention, the loss of the semiconductor substrate can be made less than 100 GPa.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 반도체기판의 식각손실을 방지 또는 감소시키므로써 반도체기판에 형성된 접합에 주는 영향을 최소화하여 소자의 특성을 향상시킬 수 있는 효과가 있다.The present invention has the effect of improving the characteristics of the device by minimizing the effect on the bonding formed on the semiconductor substrate by preventing or reducing the etching loss of the semiconductor substrate.
또한, 식각장비에 의해 발생하는 반도체기판 손실의 불균일또한 개선시킬 수 있어 수율을 향상시킬 수 있는 효과가 있다. In addition, the non-uniformity of the loss of the semiconductor substrate generated by the etching equipment can also be improved, thereby improving the yield.
도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 게이트스페이서 제조 방법을 도시한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a gate spacer of a semiconductor device according to the prior art.
도 2a는 종래 기술에 따른 NMOS 트랜지스터에서의 게이트스페이서형성후 반도체기판의 식각손실을 나타낸 사진, Figure 2a is a photo showing the etching loss of the semiconductor substrate after the formation of the gate spacer in the NMOS transistor according to the prior art,
도 2b는 종래 기술에 따른 PMOS 트랜지스터에서의 게이트스페이서형성후 반도체기판의 식각손실을 나타낸 사진,Figure 2b is a photo showing the etching loss of the semiconductor substrate after the formation of the gate spacer in the PMOS transistor according to the prior art,
도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체 소자의 게이트스페이서 제조 방법을 도시한 공정 단면도.3A to 3D are cross-sectional views illustrating a method of manufacturing a gate spacer of a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film
23 : 폴리실리콘막 24 : 텅스텐막23 polysilicon film 24 tungsten film
25 : 게이트하드마스크질화막 26 : 제1산화막25 gate hard mask nitride film 26 first oxide film
27 : 실리콘질화막 28 : 제2산화막 27 silicon nitride film 28 second oxide film
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| Country | Link |
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| KR (1) | KR20050106879A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100850139B1 (en) * | 2006-12-26 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Side wall spacer manufacturing method of semiconductor device |
| CN102420123A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
-
2004
- 2004-05-06 KR KR1020040031939A patent/KR20050106879A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100850139B1 (en) * | 2006-12-26 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Side wall spacer manufacturing method of semiconductor device |
| CN102420123A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
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