CN102420123A - Process for adjusting characteristic size of gate side wall layer by wet-method etching - Google Patents
Process for adjusting characteristic size of gate side wall layer by wet-method etching Download PDFInfo
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- CN102420123A CN102420123A CN2011101103340A CN201110110334A CN102420123A CN 102420123 A CN102420123 A CN 102420123A CN 2011101103340 A CN2011101103340 A CN 2011101103340A CN 201110110334 A CN201110110334 A CN 201110110334A CN 102420123 A CN102420123 A CN 102420123A
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- wall layer
- side wall
- lateral wall
- gate lateral
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Abstract
The invention discloses a process for adjusting the characteristic size of a gate side wall layer by wet-method etching. The process comprises the following steps of: growing a side wall layer on the surface of a semiconductor device through a furnace tube; carrying out dry-method etching, retaining the gate side wall layer of the gate side wall in the semiconductor device and removing excessive side wall layers; and carrying out wet-method etching so as to adjust the thickness of the side wall. According to the process disclosed by the invention, the problems of long process time and instable process caused by growing the side wall layer through the furnace tube and removing the excessive part of the side wall layer by using the dry-method etching in the prior art are solved by using the process of adjusting the characteristic size of the gate side wall layer by the wet-method etching; and the characteristic size of the gate side wall layer is adjusted by the wet-method etching and the technical effects of optimizing the processing procedure and simultaneously increasing the yield are achieved.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, relate in particular to a kind of technology of regulating the gate lateral wall characteristic size through wet etching.
Background technology
Fig. 1 is the structural representation before the gate lateral wall layer etching in the prior art, and Fig. 2 is the structural representation after the gate lateral wall layer etching in the prior art, sees also Fig. 1, Fig. 2:
The traditional handicraft of current gate lateral wall layer etching all is through boiler tube growth side wall layer, and then removes the side wall layer of redundance with dry etching.The shortcoming of this method is to have to regulate the side wall layer thickness after the etching through the side wall layer thickness of growth.And boiler tube growth is consuming time huge, and the process time is long, repeatedly plants experiment and must repeatedly grow if will do, and wastes very much.And the pattern that dry etching also is attended by after technology instability and the etching is the problem of up-narrow and down-wide (footing).
Summary of the invention
The invention discloses a kind of technology of regulating the gate lateral wall layer characteristic size through wet etching; Pass through boiler tube growth side wall layer in the prior art in order to solve, and then remove the long and technology problem of unstable of the process time that side wall layer caused of redundance with dry etching.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of technology through wet etching adjusting gate lateral wall layer characteristic size wherein, is passed through boiler tube growth one deck side wall layer with the surface of semiconductor device; Carry out dry etching,, remove unnecessary side wall layer the gate lateral wall layer reservation of gate lateral wall in the semiconductor device; Carry out wet etching, adjust with the thickness of oppose side wall.
Aforesaid technology through wet etching adjusting gate lateral wall layer characteristic size wherein, is adjusted etch period according to the wet etching rate, to control the thickness of said gate lateral wall layer.
Aforesaid technology through wet etching adjusting gate lateral wall layer characteristic size wherein, forms side wall layer through chemical vapour deposition (CVD) in said boiler tube.
Aforesaid technology through wet etching adjusting gate lateral wall layer characteristic size, wherein, said side wall layer forms through depositing undoped glass silicon.
Aforesaidly regulate the technology of gate lateral wall layer characteristic size, wherein, etch period is adjusted, with the characteristic size of control gate lateral wall layer and eliminate the up-narrow and down-wide situation of gate lateral wall layer according to the wet etching rate through wet etching.
In sum; Owing to adopted technique scheme; The technology that the present invention regulates the gate lateral wall layer characteristic size through wet etching has solved in the prior art through boiler tube growth side wall layer; And then remove the long and technology problem of unstable of the process time that side wall layer caused of redundance with dry etching, and regulate the gate lateral wall layer characteristic size through carrying out wet etching, reached and optimized the technique effect that processing procedure improves good productive rate simultaneously.
Description of drawings
Fig. 1 is the structural representation before the gate lateral wall layer etching in the prior art;
Fig. 2 is the structural representation after the gate lateral wall layer etching in the prior art;
Fig. 3 is that the present invention passes through the structural representation of completion side wall layer post precipitation that wet etching is regulated the technology of gate lateral wall layer characteristic size;
Fig. 4 is that the present invention passes through the structural representation after wet etching is regulated the unnecessary side wall layer of removal of technology of gate lateral wall layer characteristic size;
Fig. 5 is that the present invention passes through the structural representation after wet etching is regulated the technology wet etching of gate lateral wall layer characteristic size;
Fig. 6 is that the present invention passes through the flow chart that wet etching is regulated the gate lateral wall layer characteristic size.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
The invention discloses a kind of technology of regulating the gate lateral wall layer characteristic size through wet etching; Wherein, Fig. 3 is that the present invention passes through the structural representation of completion side wall layer post precipitation that wet etching is regulated the technology of gate lateral wall layer characteristic size, sees also Fig. 3; Boiler tube growth one deck side wall layer is passed through on the surface of semiconductor device; Both semiconductor device was placed boiler tube, deposition one deck side wall layer in boiler tube, this side wall layer covers entire semiconductor device; Fig. 4 is that the present invention passes through the structural representation after wet etching is regulated the unnecessary side wall layer of removal of technology of gate lateral wall layer characteristic size; See also Fig. 4; Carry out dry etching; Remove unnecessary side wall layer, remaining side wall layer that except the gate lateral wall of gate lateral wall part, covers on the semiconductor device through the dry etching semiconductor surfaces following is eliminated all; Fig. 5 is that the present invention passes through the structural representation after wet etching is regulated the technology wet etching of gate lateral wall layer characteristic size; See also Fig. 5; Carry out wet etching; Thickness with oppose side wall is adjusted, and the technology of available technology adopting dry etching is unstable, and the pattern that occurs easily after the etching is the problem of up-narrow and down-wide (footing); Through improving the uniformity of gate lateral wall layer characteristic size behind the wet etching, the problem that pattern is up-narrow and down-wide (footing) appears in gate lateral wall layer easily after increasing the stability of processing procedure and eliminating etching.
Carry out dry etching among the present invention, remove in the technology of unnecessary side wall layer, with the gate lateral wall layer reservation of gate lateral wall in the semiconductor device, remaining side wall layer is all removed through dry etching.
According to the wet etching rate etch period is adjusted among the present invention; Thickness with the control gate lateral wall layer; Realization need not can regulate through growth gate lateral wall layer thickness the technological effect of gate lateral wall layer thickness after the etching; Solved in the prior art dry etching defective of gate lateral wall layer of need growing with control gate lateral wall layer thickness; Especially in doing the process of repeatedly planting experiment, adopt technical scheme of the present invention effectively to reduce the waste that prior art is repeatedly grown and caused, and reduced the process time.
In said boiler tube, form side wall layer among the present invention through chemical vapour deposition (CVD) (Chemical Vapor Deposition is called for short CVD).
Said side wall layer among the present invention forms through depositing undoped glass silicon.
According to the wet etching rate etch period is adjusted among the present invention,, made the pattern of sidewall surfaces desirable more with the characteristic size (CD) of controlling gate lateral wall layer and the situation of eliminating gate lateral wall up-narrow and down-wide (footing).
Fig. 6 is that the present invention passes through the flow chart that wet etching is regulated the gate lateral wall layer characteristic size, sees also Fig. 6, and concrete processing step of the present invention is: step 101: boiler tube growth one deck side wall layer is passed through on the surface of semiconductor device; Step 102: carry out dry etching,, remove unnecessary side wall layer with the gate lateral wall layer reservation of gate lateral wall in the semiconductor device; Step 103: carry out wet etching, adjust with the thickness of oppose side wall.
In sum; Owing to adopted technique scheme; The technology that the present invention regulates the gate lateral wall layer characteristic size through wet etching has solved in the prior art through boiler tube growth side wall layer; And then remove the long and technology problem of unstable of the process time that side wall layer caused of redundance with dry etching, and regulate the gate lateral wall layer characteristic size through carrying out wet etching, reached and optimized the technique effect that processing procedure improves good productive rate simultaneously.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (5)
1. the technology through wet etching adjusting gate lateral wall layer characteristic size is characterized in that, boiler tube growth one deck side wall layer is passed through on the surface of semiconductor device; Carry out dry etching,, remove unnecessary side wall layer the gate lateral wall layer reservation of gate lateral wall in the semiconductor device; Carry out wet etching, adjust with the thickness of oppose side wall.
2. the technology through wet etching adjusting gate lateral wall layer characteristic size according to claim 1 is characterized in that, according to the wet etching rate etch period is adjusted, to control the thickness of said gate lateral wall layer.
3. the technology through wet etching adjusting gate lateral wall layer characteristic size according to claim 1 is characterized in that, in said boiler tube, forms side wall layer through chemical vapour deposition (CVD).
4. the technology through wet etching adjusting gate lateral wall layer characteristic size according to claim 1 is characterized in that said side wall layer forms through depositing undoped glass silicon.
5. technology of regulating the gate lateral wall layer characteristic size through wet etching according to claim 1; It is characterized in that; According to the wet etching rate etch period is adjusted, with control gate lateral wall layer characteristic size and eliminate the up-narrow and down-wide situation of gate lateral wall layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101103340A CN102420123A (en) | 2011-04-29 | 2011-04-29 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101103340A CN102420123A (en) | 2011-04-29 | 2011-04-29 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
Publications (1)
| Publication Number | Publication Date |
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| CN102420123A true CN102420123A (en) | 2012-04-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011101103340A Pending CN102420123A (en) | 2011-04-29 | 2011-04-29 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091556A (en) * | 2017-11-09 | 2018-05-29 | 上海华力微电子有限公司 | Etching process |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387238A (en) * | 2001-05-23 | 2002-12-25 | 松下电器产业株式会社 | Method for mfg. semiconductor device |
| KR20050106879A (en) * | 2004-05-06 | 2005-11-11 | 주식회사 하이닉스반도체 | Method for manufacturing gate spacer in semiconductor device |
| CN101211769A (en) * | 2006-12-28 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Grids structure and method of manufacture |
| CN101241852A (en) * | 2007-02-06 | 2008-08-13 | 中芯国际集成电路制造(上海)有限公司 | A making method for grid side wall for reducing N adulterated grid resistance |
| CN101872726A (en) * | 2010-05-28 | 2010-10-27 | 上海宏力半导体制造有限公司 | Manufacture method of semiconductor device |
-
2011
- 2011-04-29 CN CN2011101103340A patent/CN102420123A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387238A (en) * | 2001-05-23 | 2002-12-25 | 松下电器产业株式会社 | Method for mfg. semiconductor device |
| KR20050106879A (en) * | 2004-05-06 | 2005-11-11 | 주식회사 하이닉스반도체 | Method for manufacturing gate spacer in semiconductor device |
| CN101211769A (en) * | 2006-12-28 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Grids structure and method of manufacture |
| CN101241852A (en) * | 2007-02-06 | 2008-08-13 | 中芯国际集成电路制造(上海)有限公司 | A making method for grid side wall for reducing N adulterated grid resistance |
| CN101872726A (en) * | 2010-05-28 | 2010-10-27 | 上海宏力半导体制造有限公司 | Manufacture method of semiconductor device |
Non-Patent Citations (5)
| Title |
|---|
| 吴燕燕等: "改良离子色谱法测定咸鱼中亚硝酸盐的研究", 《南方水产科学》 * |
| 李宝文: "挖掘机液压系统的保养与维护", 《山东农机化》 * |
| 杨敏等: "离子色谱法测定白菜中的硝酸盐、亚硝酸盐、磷酸盐及总磷、总氮", 《食品科学》 * |
| 王宏军等: "大叶南五味子果实化学成分研究", 《中药材》 * |
| 钟跃宽: "红花注射液去除钾离子不同工艺对比研究", 《临床合理用药》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091556A (en) * | 2017-11-09 | 2018-05-29 | 上海华力微电子有限公司 | Etching process |
| CN108091556B (en) * | 2017-11-09 | 2019-11-19 | 上海华力微电子有限公司 | Etching process |
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Application publication date: 20120418 |