CN101872726A - Manufacture method of semiconductor device - Google Patents
Manufacture method of semiconductor device Download PDFInfo
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- CN101872726A CN101872726A CN201010187371A CN201010187371A CN101872726A CN 101872726 A CN101872726 A CN 101872726A CN 201010187371 A CN201010187371 A CN 201010187371A CN 201010187371 A CN201010187371 A CN 201010187371A CN 101872726 A CN101872726 A CN 101872726A
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Abstract
The invention discloses a manufacture method of a semiconductor device, comprising the following steps of: providing a semiconductor substrate on which a grid electrode is formed; forming a first oxidation layer, a silicon nitride layer and a second oxidation layer on the semiconductor substrate and the grid electrode in sequence; etching the second oxidation layer, the silicon nitride layer and the first oxidation layer until the top of the grid electrode is exposed to form a side wall layer; executing an argon ion implantation process; executing a wet etching process; forming a source electrode and a drain electrode in the semiconductor substrate at both sides of the side wall layer; forming self-aligned blocking layers on the surfaces of the semiconductor substrate, the side wall layer and the grid electrode, wherein the self-aligned blocking layers are provided with openings for exposing the grid electrode, the source electrode and the drain electrode; executing an argon ion sputtering process; and forming self-aligned metal silicides on the surfaces of the grid electrode, the source electrode and the drain electrode. According to the invention, the second oxidation layer remaining at the corners of the side wall layer can be removed effectively to ensure the quality of the self-aligned metal silicides and improve the electrical behavior of the semiconductor device.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of manufacture method of semiconductor device.
Background technology
Self-aligned metal silicate (Salicide) has lower resistivity, and has good adhesion property with silicon, be widely used in source, drain contact layer and grid contact layer to reduce contact resistance, described self-aligned metal silicate can form by the metal and the pasc reaction of infusibility.Along with reducing day by day of dimensions of semiconductor devices, performance demands to semiconductor device is more and more higher, particularly 90nm and following technology node thereof, in order to obtain lower contact resistance, industry adopts the metal material of metals such as cobalt, nickel or titanium as the self-aligned metal silicate that forms low-resistivity.
Specifically please refer to Figure 1A to Fig. 1 H, it is the generalized section of each step corresponding construction of the manufacture method of conventional semiconductor device.
Please refer to Figure 1A, at first, provide the Semiconductor substrate 100 that is formed with grid, described grid comprises grid oxic horizon 110 and is formed at gate electrode 120 on the grid oxic horizon 110.
Please refer to Figure 1B, then, on described Semiconductor substrate 100 and grid, form first oxide layer 130, silicon nitride layer 140 and second oxide layer 150 successively.
Please refer to Fig. 1 C, then, utilize the mode of dry etching, described second oxide layer 150 of etching, silicon nitride layer 140 and first oxide layer 130 successively, until the top that exposes described grid, to form side wall layer, described side wall layer comprises patterned first oxide layer 130a and patterned silicon nitride layer 140a.Yet, in actual production, find because the anisotropic characteristics of dry etching, the remaining second oxide layer 150a arranged in that the corner of described side wall layer is also residual.
Please refer to Fig. 1 D, afterwards, carry out wet-etching technology, to remove the remaining second oxide layer 150a.The corrosive liquid that described wet-etching technology adopted is a BOE solution, because wet-etching technology is isotropic, be not corroded in order to ensure the patterned first oxide layer 130a, the time of this wet-etching technology is shorter, therefore, through behind this wet-etching technology, in the corner (zone shown in the dotted line among Fig. 1 D) or residual second oxide layer that has to a certain degree of described side wall layer.
Please refer to Fig. 1 E, next, the mode of utilizing ion to inject forms source electrode 160 and drain electrode 170 in the Semiconductor substrate 100 of described side wall layer both sides.
Please refer to Fig. 1 F, form autoregistration barrier layer 180 in described Semiconductor substrate 100, side wall layer and gate surface, described autoregistration barrier layer 180 has the opening that exposes described grid, the opening that exposes described source electrode and the opening that exposes described drain electrode.
Please refer to Fig. 1 G, form after the described autoregistration barrier layer 180, carry out argon gas ion sputter (sputter) technology usually, to remove the natural oxidizing layer (native oxide) on the Semiconductor substrate 100.Because in still residual second oxide layer that has to a certain degree of the corner of described side wall layer, in this argon gas ion sputter step, these second residual oxide layers very likely deposit to the surface of Semiconductor substrate.
Please refer to Fig. 1 H, form self-aligned metal silicate 121, form self-aligned metal silicate 161, form self-aligned metal silicate 171 on drain electrode 170 surfaces on source electrode 160 surfaces on grid 120 surfaces.
But, owing to the remaining second oxide layer 150a arranged in that the corner of described side wall layer is also residual, and through behind the wet-etching technology, the remaining second oxide layer 150a still can't be got rid of fully.Therefore, in the argon gas ion sputter step, these second residual oxide layers may deposit to silicon face once more, hindered the formation of self-aligned metal silicate, thereby influence the quality of self-aligned metal silicate, thereby cause semiconductor device failure, reduced the yield of product.Industry was once attempted several different methods to address the above problem, and for example, prolong the time of wet etching step, but this will cause the patterned first oxide layer 130a also to be corroded.In addition, industry also once attempted reducing by second thickness of oxide layer, but this will influence the critical size (CD) of the side wall layer that forms, and then influenced the electric property of semiconductor device.
Summary of the invention
The invention provides a kind of manufacture method of semiconductor device,, guarantee the quality of self-aligned metal silicate, improve the electric property of semiconductor device with remaining second oxide layer of effective removal side wall layer corner.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of semiconductor device, comprising: the Semiconductor substrate that is formed with grid is provided; On described Semiconductor substrate and grid, form first oxide layer, silicon nitride layer and second oxide layer successively; Etching second oxide layer, silicon nitride layer and first oxide layer form side wall layer until exposing top portions of gates; Carry out the argon ion injection technology; Carry out wet-etching technology; In the Semiconductor substrate of described side wall layer both sides, form source electrode and drain electrode; Form the autoregistration barrier layer in described Semiconductor substrate, side wall layer and gate surface, described autoregistration barrier layer has the opening that exposes described grid, source electrode and drain electrode; Carry out argon ion sputtering technology; Form self-aligned metal silicate in grid, source electrode and drain surface.
Optionally, in the manufacture method of described semiconductor device, the injection energy of described argon ion injection technology is less than 5KeV, and the implantation dosage of described argon ion injection technology is 1 * 10
13～10 * 10
15/ cm
2
Optionally, in the manufacture method of described semiconductor device, the direction that described argon ion injects and the angle of Semiconductor substrate are 10～80 degree.
Optionally, in the manufacture method of described semiconductor device, the direction that described argon ion injects and the angle of Semiconductor substrate are 45 degree.
Optionally, in the manufacture method of described semiconductor device, the corrosive liquid that described wet-etching technology uses is BOE solution, and the time of described wet-etching technology is 20～400 seconds.
Optionally, in the manufacture method of described semiconductor device, the material on described autoregistration barrier layer is a silicon rich oxide, and the material of described self-aligned metal silicate is cobalt silicide, Titanium silicide or nickel silicide.
Optionally, in the manufacture method of described semiconductor device, form after the self-aligned metal silicate, also comprise: remove described autoregistration barrier layer.
Optionally, in the manufacture method of described semiconductor device, adopt the mode of wet etching to remove described autoregistration barrier layer.
Compared with prior art, the manufacture method of semiconductor device provided by the invention has the following advantages:
The present invention is after forming side wall layer, carry out before the wet-etching technology, increased the processing step that argon ion injects, this argon ion injection technology can make remaining second oxide layer of side wall layer corner decrystallized, thereby the etch rate of second oxide layer in the quickening wet-etching technology, guarantee that remaining second oxide layer of described side wall layer corner is removed fully, guarantee the quality of the final self-aligned metal silicate that forms, and then improve the electric property of semiconductor device.
Description of drawings
Figure 1A～1H is the generalized section of each step corresponding construction of the manufacture method of existing semiconductor device;
Fig. 2 is the flow chart of the manufacture method of the semiconductor device that the embodiment of the invention provided;
Fig. 3 A～3I is the generalized section of each step corresponding construction of the manufacture method of the semiconductor device that the embodiment of the invention provided.
Embodiment
Core concept of the present invention is, a kind of manufacture method of semiconductor device is provided, this method is after forming side wall layer, carry out before the wet-etching technology, increased the processing step that argon ion injects, this argon ion injection technology can make remaining second oxide layer of side wall layer corner decrystallized, thereby the etch rate of second oxide layer in the quickening wet-etching technology, guarantee that remaining second oxide layer of side wall layer corner is removed fully, guarantee the quality of the final self-aligned metal silicate that forms, and then improve the electric property of semiconductor device.
Please refer to Fig. 2, it is the flow chart of the manufacture method of the semiconductor device that the embodiment of the invention provided, and in conjunction with this figure, this method may further comprise the steps:
Step S201 provides the Semiconductor substrate that is formed with grid;
Step S202 forms first oxide layer, silicon nitride layer and second oxide layer successively on described Semiconductor substrate and grid;
Step S203, described second oxide layer of etching, silicon nitride layer and first oxide layer form side wall layer until exposing top portions of gates;
Step S204 carries out the argon ion injection technology;
Step S205 carries out wet-etching technology;
Step S206 forms source electrode and drain electrode in the Semiconductor substrate of described side wall layer both sides;
Step S207 forms the autoregistration barrier layer on described Semiconductor substrate, side wall layer and grid, described autoregistration barrier layer has the opening that exposes described grid, source electrode and drain electrode;
Step S208 carries out argon ion sputtering technology;
Step S209 forms self-aligned metal silicate in described grid, source electrode and drain surface.
Be described in more detail below in conjunction with the manufacture method of generalized section semiconductor device of the present invention, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Please refer to Fig. 3 A, at first, provide the Semiconductor substrate 300 that is formed with grid, described grid comprises grid oxic horizon 310 and is formed at gate electrode 320 on the grid oxic horizon 310.Be formed with shallow plough groove isolation area (STI) in the described Semiconductor substrate 300.
In another specific embodiment of the present invention, after forming described grid, form before the side wall layer, the ion that can also carry out low concentration injects, to form lightly-doped source/drain region (LDD) in the Semiconductor substrate 300 of described grid both sides.
Please refer to Fig. 3 B, then, on described Semiconductor substrate 300 and described grid, form first oxide layer 330, silicon nitride layer 340 and second oxide layer 350 successively.
Please refer to Fig. 3 C, then, utilize the mode of dry etching, described second oxide layer 350 of etching, silicon nitride layer 340 and first oxide layer 330 successively, until the top that exposes described grid, to form side wall layer, described side wall layer comprises patterned first oxide layer 330a and the patterned silicon nitride layer 340a that covers the described patterned first oxide layer 330a.Yet, in actual production, find because the anisotropic characteristics of dry etching, the remaining second oxide layer 350a arranged in that the corner of described side wall layer is also residual.
Please refer to Fig. 3 D, after forming side wall layer, carry out before the wet-etching technology, the present invention has increased the processing step that argon ion injects, this argon ion injection technology can make the remaining second oxide layer 350a of side wall layer corner decrystallized, thereby accelerates the etch rate of the remaining second oxide layer 350a in the wet-etching technology.
The injection energy of described argon ion injection technology is less, implantation dosage is higher, and can be by the direction of control argon ion injection and the angle between the Semiconductor substrate 300, make the remaining second oxide layer 350a of described side wall layer corner decrystallized, and guarantee can excessive damage grid and Semiconductor substrate.In a specific embodiment of the present invention, the injection energy of described argon ion injection technology is less than 5KeV, and implantation dosage is 1 * 10
13～10 * 10
15/ cm
2, the direction that described argon ion injects and the angle of Semiconductor substrate 300 are 10～80 degree.Preferably, the angle of the direction of described argon ion injection and Semiconductor substrate 300 is 45 degree.
Please refer to Fig. 3 E, after the execution argon ion injection technology, carry out wet-etching technology, to remove the remaining second oxide layer 350a.Because this argon ion injection technology has been accelerated the etch rate of the remaining second oxide layer 350a, can guarantee that the remaining second oxide layer 350a of described side wall layer corner is removed fully, thereby guarantee the quality of the final self-aligned metal silicate that forms, and then improve the electric property of semiconductor device.
In a specific embodiment of the present invention, the corrosive liquid that described wet-etching technology uses is BOE solution, and the time of described wet-etching technology is 20～400 seconds.
Please refer to Fig. 3 F, next, the mode of utilizing ion to inject forms source electrode 360 and drain electrode 370 in the Semiconductor substrate 300 of described side wall layer both sides.
Please refer to Fig. 3 G, form autoregistration barrier layer 380, the opening that described autoregistration barrier layer 380 has the opening that exposes described grid, the opening that exposes source electrode 360 and exposes drain electrode 370 in described Semiconductor substrate 300, side wall layer and gate surface.The material on described autoregistration barrier layer 380 can be silicon rich oxide.
Please refer to Fig. 3 H, after forming autoregistration barrier layer 380, carry out argon gas ion sputter (sputter) technology, to remove the natural oxidizing layer (native oxide) on the Semiconductor substrate 300.
Please refer to Fig. 3 I, form self-aligned metal silicate 321, form self-aligned metal silicate 361, form self-aligned metal silicate 371 on drain electrode 370 surfaces on source electrode 360 surfaces in described gate surface.The material of described self-aligned metal silicate 321,361,371 can be cobalt silicide, Titanium silicide or nickel silicide.
In another specific embodiment of the present invention, after forming described self-aligned metal silicate, can adopt the mode of wet etching to remove autoregistration barrier layer 380.
In sum, because the present invention is after forming side wall layer, carry out before the wet-etching technology, increased the processing step that argon ion injects, this argon ion injection technology can make remaining second oxide layer of side wall layer corner decrystallized, thereby accelerates the etch rate of second oxide layer in the wet-etching technology, guarantees that remaining second oxide layer of described side wall layer corner is removed fully, guarantee the quality of the final self-aligned metal silicate that forms, and then improve the electric property of semiconductor device.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. the manufacture method of a semiconductor device comprises:
The Semiconductor substrate that is formed with grid is provided;
On described Semiconductor substrate and grid, form first oxide layer, silicon nitride layer and second oxide layer successively;
Etching second oxide layer, silicon nitride layer and first oxide layer form side wall layer until exposing top portions of gates;
Carry out the argon ion injection technology;
Carry out wet-etching technology;
In the Semiconductor substrate of described side wall layer both sides, form source electrode and drain electrode;
Form the autoregistration barrier layer in described Semiconductor substrate, side wall layer and gate surface, described autoregistration barrier layer has the opening that exposes described grid, source electrode and drain electrode;
Carry out argon ion sputtering technology;
Form self-aligned metal silicate in described grid, source electrode and drain surface.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the injection energy of described argon ion injection technology is less than 5KeV.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the implantation dosage of described argon ion injection technology is 1 * 10
13～10 * 10
15/ cm
2
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the direction that described argon ion injects and the angle of described Semiconductor substrate are 10～80 degree.
5. the manufacture method of semiconductor device as claimed in claim 4 is characterized in that, the direction that described argon ion injects and the angle of described Semiconductor substrate are 45 degree.
6. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the corrosive liquid that described wet-etching technology uses is BOE solution.
7. the manufacture method of semiconductor device as claimed in claim 6 is characterized in that, the time of described wet-etching technology is 20～400 seconds.
8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the material on described autoregistration barrier layer is a silicon rich oxide.
9. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the material of described self-aligned metal silicate is cobalt silicide, Titanium silicide or nickel silicide.
10. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, forms after the described self-aligned metal silicate, also comprises: remove described autoregistration barrier layer.
11. the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, adopts the mode of wet etching to remove described autoregistration barrier layer.
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| CN201010187371.7A CN101872726B (en) | 2010-05-28 | 2010-05-28 | The manufacture method of semiconductor device |
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| CN201010187371.7A CN101872726B (en) | 2010-05-28 | 2010-05-28 | The manufacture method of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420123A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
| CN102623320A (en) * | 2012-03-22 | 2012-08-01 | 上海华力微电子有限公司 | Method for characterizing polycrystalline silicon resistor in multilayer grid electrode |
| CN112928153A (en) * | 2019-12-05 | 2021-06-08 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
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| CN101192577A (en) * | 2006-11-30 | 2008-06-04 | 东部高科股份有限公司 | Flash memory device and method of manufacturing the same |
| CN101253619A (en) * | 2005-08-31 | 2008-08-27 | 先进微装置公司 | Technique for forming recessed strained drain/source in NMOS and PMOS transistors |
| US20080242017A1 (en) * | 2007-03-26 | 2008-10-02 | Kun-Hsien Lee | Method of manufacturing semiconductor mos transistor devices |
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| US20050142777A1 (en) * | 2003-12-30 | 2005-06-30 | Dongbuanam Semiconductor, Inc. | Method of fabricating transistor in semiconductor device |
| CN101253619A (en) * | 2005-08-31 | 2008-08-27 | 先进微装置公司 | Technique for forming recessed strained drain/source in NMOS and PMOS transistors |
| CN101192577A (en) * | 2006-11-30 | 2008-06-04 | 东部高科股份有限公司 | Flash memory device and method of manufacturing the same |
| US20080242017A1 (en) * | 2007-03-26 | 2008-10-02 | Kun-Hsien Lee | Method of manufacturing semiconductor mos transistor devices |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420123A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Process for adjusting characteristic size of gate side wall layer by wet-method etching |
| CN102623320A (en) * | 2012-03-22 | 2012-08-01 | 上海华力微电子有限公司 | Method for characterizing polycrystalline silicon resistor in multilayer grid electrode |
| CN102623320B (en) * | 2012-03-22 | 2015-04-22 | 上海华力微电子有限公司 | Method for characterizing polycrystalline silicon resistor in multilayer grid electrode |
| CN112928153A (en) * | 2019-12-05 | 2021-06-08 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
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| CN101872726B (en) | 2016-03-23 |
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