CN101826465B - Method for preventing gap below side wall barrier layer during self-aligning silicide process - Google Patents
Method for preventing gap below side wall barrier layer during self-aligning silicide process Download PDFInfo
- Publication number
- CN101826465B CN101826465B CN2009100470063A CN200910047006A CN101826465B CN 101826465 B CN101826465 B CN 101826465B CN 2009100470063 A CN2009100470063 A CN 2009100470063A CN 200910047006 A CN200910047006 A CN 200910047006A CN 101826465 B CN101826465 B CN 101826465B
- Authority
- CN
- China
- Prior art keywords
- layer
- dusts
- device substrate
- thickness
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a method for a part to prevent a gap below a side wall barrier layer during a self-aligning silicide process. The part comprises a bedding oxidation film which covers a part underlayer and a grid which is formed on the bedding oxidation film. The method comprises the following steps that: after a sacrificial layer TEOS is deposited, the sacrificial layer and the bedding oxidation film covering the part underlayer are etched until the surface of the part underalyer and the grid top part; and during the manufacturing process of the side wall barrier layer of the grid, by utilizing the self-aligning silicide way, the thickness of the oxidation layer which is deposited on the part underlayer which is etched in a wet way is more than or equal to 100 angstroms and is less than 200 angstroms. The method can prevent the gap below the barrier layer during the self-aligning process of silicide.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly a kind of method that in the self-aligned silicide process, prevents slit below the barrier layer.
Background technology
In the manufacture process of integrated circuit, need metallize to device, metallization be in the device manufacturing processes on the dielectric film depositing metal films and subsequently the mint-mark figure so that form interconnect metallization lines and the hole filler plug process of device.Such as, go up the plated metal interconnection layer at the active area (AA, Active Region) of device.
Along with the performance optimization of integrated circuit, the characteristic size of device further reduces, and the cross section that between AA and metal interconnecting layer, electrically contacts is very little, and this little electric interface can cause the increase of contact resistance.For the AA that reduces device and the contact resistance between the metal interconnecting layer, can between AA and metal interconnecting layer, deposit one deck silicide as contact layer, react like the silicon of deposit cobalt and AA layer, form cobalt silicon.In order to obtain silicide, just need that AA is surface exposed to go out silicon.But in the device processing procedure of reality, some zones that have of AA do not need external metal wire, need not expose outside silicon, so just need not generate silicide yet.At this moment, the AA that just needs employing self-aligned silicide process generation barrier layer to make the surface have the barrier layer can't deposit and obtain silicide.
Adopt the self-aligned silicide mode to make the generalized section of the side wall barrier layer of grid in conjunction with the prior art device shown in Fig. 1 a～1e; Adopt prior art device shown in Figure 2 to adopt the self-aligned silicide mode to make the method flow diagram of the side wall barrier layer of grid, this process is elaborated.
Method concrete steps shown in Figure 2 are:
Step 201, the structure shown in Fig. 1 a are carried out the device processing procedure, comprise device substrate 10, grid 11 and pad oxide-film 20;
In this step, made the source electrode and the drain electrode of device in the device substrate 10, just AA;
In this step, the deposit thickness of pad oxide-film 20 is 155 dusts, and the gate oxide thickness in the grid 11 is 175 dusts;
In the structure shown in Fig. 1 a, only show the high-pressure MOS part in the device, also have low pressure MOS part in the device, the corresponding thickness that in the same plane of device, just exists is that the pad oxide-film 20 of 155 dusts is the pad oxide-film of 20 dusts with thickness;
Step 202, the method deposition that on the structure shown in Fig. 1 a, adopts the TEOS method to generate oxide layer 30 and low pressure chemical vapor phase deposition successively obtain nitration case 40; Obtain the structure shown in Fig. 1 b, just adopt oxide layer 30 and nitration case 40 to process the side wall barrier layer of grid 11;
In this step, oxide layer 30 and nitration case 40 are 580 dusts as the thickness of the side wall barrier layer of grid 11;
Step 203, the structure shown in Fig. 1 b is carried out etching, etch away the oxide layer 30 and nitration case 40 of grid 11 and substrate 10 upper surfaces deposition, obtain the structure shown in Fig. 1 c, promptly on the sidewall of grid 11, formed and stop sidewall;
In this step; The method that etching can adopt dry etching and wet etching to combine adopts first dry etching, the oxide layer 30 of residual 100 dusts of having an appointment; After to utilize wet method to carve again wet with its removal; Because this wet etching has certain etching of crossing,, promptly be reduced to 100 from 155 so the residual oxide layer of substrate 10 upper surfaces has certain minimizing;
Step 204, to adopting low pressure chemical vapor phase deposition silicon oxide layer 50 on the structure shown in Fig. 1 c, obtain the structure shown in Fig. 1 d;
In this step,,, and do not expose the silicon of substrate 10 on the device so the effect of silicon oxide layer deposited 50 is exactly as these regional barrier layers because other some zones of substrate 10 need not generate the metal silicide layer (not shown) on the device;
In this step, silicon oxide layer 50 thickness on the horizontal direction that deposition obtains are more than 100 dusts, such as being 350 dusts;
Step 205, employing dry etching silicon oxide layer 50;
Before etching, earlier silicon oxide layer 50 is carried out the patterning (not shown), be used to keep the silicon oxide layer 50 that need not generate the zone of silicide layer on the device substrate 10, make its at subsequent step as the barrier layer;
After adopting dry etching oxide layer 50, the silicon oxide layer 50 of the horizontal direction that obtains, oxide layer 30 and pad oxide-film 20 thickness are 200 dusts;
In this step; It is clean to adopt dry etching not allow silicon oxide layer 50, oxide layer 30 and pad oxide-film 20 etchings; This is because owing to existing high-pressure MOS part and low pressure MOS part to cause filling up the oxide thickness inequality on the device; If the oxide layer etching to the high-pressure MOS part is clean, then can the substrate 10 surperficial silicon ions of low pressure MOS part on the device be damaged (dry etching adopts ion bombardment to carry out, and can cause the damage of device substrate 10 to the silicon ion bombardment); So silicon oxide layer 50 in the horizontal direction, i.e. thickness behind the high-pressure MOS employing dry etching is less than 100 dusts;
Step 206, employing wet etching continue etching oxidation silicon layer 50, obtain the structure shown in Fig. 1 e;
Owing to do not remove clean silicon oxide layer 50, oxide layer 30 and pad oxide-film 20, so need to adopt wet etching, reach the purpose of the silicon oxide layer of complete removal devices substrate 10, expose device substrate, like this, just obtained final side wall barrier layer 13;
In this step; The silicon oxide layer 50 of horizontal direction, oxide layer 30 and pad oxide-film 20 thickness are 200 dusts; Adopt wet etching method etching oxidation silicon layer 50, oxide layer 30 and the pad oxide-film 20 of 110 dust thickness; Like this, pad oxide-film 20 and oxide layer 50 on just can removal devices substrate 10 expose device substrate; When adopting wet etching, etching speed is quite a few times of silicon oxide layer of dried oxygen method deposition, and the etch amount of 110 dusts refers to the thickness of the dry-oxygen oxidation silicon layer that etches away;
In this step, because oxide layer 30 is to adopt TEOS to form, its characteristic is more loose, can cause in the wet etching process of heavy dose, and side direction also is etched away, and causes the slit between side wall barrier layer 13 and the device substrate 10.
After the process of carrying out Fig. 2; Just can be on the structure shown in Fig. 1 e deposit cobalt, the silicon that structure shown in cobalt and Fig. 1 e exposes produces reaction, obtains the cobalt silicon layer; As and upper metal layers between contact layer, reduce the AA of device and the contact resistance between the metal interconnecting layer of upper strata.And, because the existence of the silicon oxide layer of not removing on the existence of side wall barrier layer 13 and the device substrate 10 50, can be at gate lateral wall yet with the device substrate 10 that does not need contact layer on generation cobalt silicon layer, can not cause the AA of device and the short circuit between the grid.
Can find out according to process shown in Figure 2; Because the final side wall barrier layer that forms grid behind the employing wet etching; And owing to need the silicon of device substrate 10 be exposed; So the wet etching amount is also bigger, this can cause the oxide layer 30 between this side wall barrier layer and the device substrate 10 also to be etched away with pad oxide-film 20, below this side wall barrier layer, has formed undesirable slit.
This slit below this side wall barrier layer can make the element leakage of finally processing; The sectional structure chart of the prior art as shown in Figure 3 gap below side wall barrier layer of grid between contact layer and upper strata metal interconnecting layer, and the profile of the gap below side wall barrier layer of grid between prior art contact layer shown in Figure 4 and the contact layer.Along with the characteristic size of device reduces, make contact layer have only 60 nanometers between the grid of upper strata metal interconnecting layer, metal can form short circuit through the slit; And the distance between contact layer and the contact layer is 80 nanometers, and this situation of finally processing element leakage that makes can be more serious.Therefore, how to prevent that the slit below this side wall barrier layer from becoming a problem demanding prompt solution.
Summary of the invention
In view of this, the present invention provides a kind of method that in the self-aligned silicide process, prevents slit below the barrier layer, and this method can prevent the slit to occur below the side wall barrier layer of grid in the self-aligned silicide process.
For achieving the above object, the technical scheme of the embodiment of the invention specifically is achieved in that
A kind of device prevents the method in slit below the barrier layer in the self-aligned silicide process, this device comprises pad oxide-film that covers device substrate and the grid that on the pad oxide-film, forms, and this method comprises:
Behind the deposition of sacrificial layer TEOS, the said sacrifice layer of etching and cover the pad oxide-film of device substrate is up to device substrate and top portions of gates surface;
Adopting the self-aligned silicide mode to make in the side wall barrier layer process of grid, the oxidated layer thickness that is deposited on the device substrate of wet etching is 100 dusts.
Said sacrifice layer of etching and the process that covers the pad oxide-film of device substrate are:
After adopting dry etching, adopt wet etching again.
On the pad oxide-film of the top portions of gates of device and device substrate, leave the TEOS of 100 dusts behind the said dry etching.
The thickness of said pad oxide-film is 155 dusts;
The thickness of said deposition of sacrificial layer is 800 dusts;
Wet etching amount during said employing wet etching is 90 dusts.
The oxide layer that adopts the oxide layer of TEOS deposition when the oxide layer of said deposition is included in the side wall barrier layer of making grid and be used for being deposited as making overlay area on the device substrate not generate metal silicide layer.
Before the oxide layer that is deposited on the wet etching device substrate, this method also comprises:
Adopt dry etching, it is 100 dusts that the oxide layer that is deposited on the device substrate is etched into thickness.
The oxidated layer thickness that is deposited on the device substrate that said dry etching obtains is 100 dusts;
The wet etching amount of said employing wet etching is 30 dusts.
Visible by technique scheme; The present invention is earlier at gate lateral wall structure sacrifice layer (TEOS); Be used for the pad oxide-film 20 on the removal devices substrate 10; Adopt the self-aligned silicide mode to make in the side wall barrier layer process of grid then, needing oxidated layer thickness on the device substrate 10 of wet etching for more than or equal to 100 dusts and less than 200 dusts, less than the oxidated layer thickness of wet etching device substrate 10 in the prior art; Etch amount gaps thereby can not carry out the side direction etching to the side wall barrier layer below of grid with regard to corresponding minimizing.Therefore, method provided by the invention prevents the slit to occur below the side wall barrier layer of grid in the self-aligned silicide process.
Description of drawings
Fig. 1 a～1e makes the generalized section of the side wall barrier layer of grid for the prior art device adopts the self-aligned silicide mode;
Fig. 2 makes the method flow diagram of the side wall barrier layer of grid for the prior art device adopts the self-aligned silicide mode;
Fig. 3 is the sectional structure chart of prior art gap below side wall barrier layer of grid between contact layer and upper strata metal interconnecting layer;
Fig. 4 is the profile of the gap below side wall barrier layer of grid between prior art contact layer and the contact layer;
Fig. 5 a～5f makes the generalized section of the side wall barrier layer of grid for device of the present invention adopts the self-aligned silicide mode;
Fig. 6 makes the method flow diagram of the side wall barrier layer of grid for device of the present invention adopts the self-aligned silicide mode;
Fig. 7 has the cross-sectional view of the grid of side wall barrier layer for the present invention on device substrate.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is done further explain.
As can beappreciated from fig. 2; When adopting the self-aligned silicide mode to make the barrier layer of gate lateral wall; Below this barrier layer; Promptly this barrier layer and device substrate the reason in slit occurs and are: during silica on the etched features substrate, adopt wet etching and owing to the thicker wet etching amount that adopts of the oxide layer on the device substrate (more than or equal to 200 dusts) is bigger, and caused the silicon oxide layer between this barrier layer and the device substrate also to be etched away by side direction.Therefore; In order to overcome this defective, method provided by the invention at gate lateral wall structure TEOS, is used for the pad oxide-film 20 on the removal devices substrate 10 earlier; Adopting the self-aligned silicide mode to make in the side wall barrier layer process of grid thereby make; Reduce the oxidated layer thickness on the device substrate 10, making the oxidated layer thickness on the device substrate 10 that needs wet etching is 100 dusts, less than the oxidated layer thickness of wet etching device substrate 10 in the prior art; The wet etching amount that adopts gaps thereby can not carry out the side direction etching to the side wall barrier layer below of grid with regard to corresponding minimizing.
Adopt the self-aligned silicide mode to make the generalized section of the side wall barrier layer of grid in conjunction with the device of the present invention shown in Fig. 5 a～5g; Adopt device of the present invention shown in Figure 6 to adopt the self-aligned silicide mode to make the method flow diagram of the side wall barrier layer of grid, this process is elaborated.
Method concrete steps shown in Figure 6 are:
In this step, processed the source electrode and the drain electrode of device in the device substrate 10, just AA;
In this step, the deposit thickness of pad oxide-film 20 is 155 dusts, and the gate oxide thickness in the grid 11 is 175 dusts;
In the structure shown in Fig. 5 a, only show the high-pressure MOS part in the device, also have low pressure MOS part in the device, the corresponding thickness that in the same plane of device, just exists is that the pad oxide-film 20 of 155 dusts is the pad oxide-film of 20 dusts with thickness;
In this step, the sacrifice layer 30 ' thickness of deposition can be 800 dusts, and this sacrifice layer 30 ' is for adopting the silica of TEOS method deposition, and its characteristic is that material is more loose, and the growing silicon oxide thickness that vertical direction and level side are washed is more approaching;
In this step, adopting the purpose of TEOS deposition of sacrificial layer is for the pad oxide-film 20 on the removal devices substrate 10;
In this step; Adopt dry etching sacrifice layer 30 ',, can guarantee the sacrifice layer 30 ' of many etchings level deposition because dry etching has anisotropic characteristics; Lose the sacrifice layer 30 ' on the vertical direction after a little while, the thickness of the sacrifice layer 30 ' on the vertical direction becomes 720 dusts;
In this step; Dry etching has fallen grid 11 and pad oxide-film 20 lip-deep most of sacrifice layers 30 '; Remaining oxide layer on device substrate 10; Comprising sacrifice layer 30 ' and pad oxide-film 20 near 100 dusts, promptly more than or equal to 100 dusts, is device substrate 10 surperficial silicon ions not to be caused damage in the dry etching process in order to guarantee greater than 100 dusts;
In this step; Adopt wet etching sacrifice layer 30 ', the wet etching amount is 90 dusts, so just can etch away behind pad oxide-film 20 and the dry etching of 155A remaining sacrifice layer 30 '; This be because; When adopting wet etching, the etching speed of TEOS is quite a few times of silicon oxide layer of high temperature dry oxidation growth, and the etch amount of 90 dusts refers to the thickness of the dry-oxygen oxidation silicon layer that etches away;
In this step, the method that etching can adopt dry etching and wet etching to combine adopts first dry etching, the oxide layer 30 of residual 100 dusts of having an appointment, after to utilize wet method to carve again wet with its removal;
In this step, the horizontal direction thickness of the silicon oxide layer 50 of deposition guarantees can not cause damage to the ion on device substrate 10 surfaces when follow-up dry etching greater than 100 dusts;
In this step,,, and do not expose the silicon of substrate 10 on the device so the effect of silicon oxide layer deposited 50 is exactly as these regional barrier layers because other some zones of substrate 10 need not generate the metal silicide layer (not shown) on the device;
After step 607, employing dry etching silicon oxide layer 50 and the oxide layer 30, obtain the structure shown in Fig. 5 e;
Before etching, earlier silicon oxide layer 50 is carried out the patterning (not shown), be used to keep the silicon oxide layer 50 that need not generate the zone of silicide layer on the device substrate 10, make its at subsequent step as the barrier layer;
After adopting dry etching oxide layer 50 and oxide layer 30, the silicon oxide layer 50 of the horizontal direction that obtains and the thickness of oxide layer 30 are altogether 100 dusts;
In this step; It is clean to adopt dry etching not allow silicon oxide layer 50 and oxide layer 30 etchings; This is because can the silicon ion on device substrate 10 surfaces be damaged (dry etching adopts ion bombardment to carry out, and can cause the damage of device substrate 10 to the silicon ion bombardment);
Adopt wet etching, etching oxidation silicon layer 50 and oxide layer 30 reach the purpose of the silicon oxide layer of complete removal devices substrate 10, expose device substrate, like this, have just obtained final barrier layer;
In this step; Owing to want silicon oxide layer 50 and the thickness of oxide layer 30 on the horizontal direction of etching to be merely 100 dusts; So accurately the wet etching amount is 30 dusts, this be because, when adopting wet etching; Etching speed is quite a few times of silicon oxide layer of the dried oxygen method of high temperature growth, and the etch amount of 30 dusts refers to the thickness of the dry-oxygen oxidation silicon layer that etches away;
Because the step of this step and prior art is compared, the oxidated layer thickness of wet etching reduces, and corresponding etch amount reduces, and gaps so can not carry out the side direction etching to the side wall barrier layer below of grid.
Certainly; In the described method of Fig. 6, the thickness that also can when device deposited oxide layer 50, deposit is big, such as getting final product less than 200 dusts; Behind dry etching; Etching oxidation silicon layer 50 is more than or equal to 100 dusts with oxide layer 30 remaining thickness, less than 200 dusts, just can below the side wall barrier layer of grid, not gap.But most preferred embodiment still to be Fig. 6 described oxide layer 50 and oxide layer 30 are when carrying out wet etching, and thickness is 100 dusts.
The cross-section structure of the side wall barrier layer of the grid that the said process of process Fig. 6 forms on device substrate is as shown in Figure 7, can find out, does not have the slit between the side wall barrier layer of device substrate and formation grid, thereby the device of finally processing can not be leaked electricity and short circuit.
More than lift preferred embodiment; The object of the invention, technical scheme and advantage have been carried out further explain, and institute it should be understood that the above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a device prevents the method in slit below the barrier layer in the self-aligned silicide process, and this device comprises pad oxide-film that covers device substrate and the grid that on the pad oxide-film, forms, and it is characterized in that this method comprises:
Behind the deposition of sacrificial layer TEOS, the said sacrifice layer of etching and cover the pad oxide-film of device substrate is up to device substrate and top portions of gates surface;
Adopting the self-aligned silicide mode to make in the side wall barrier layer process of grid, the oxidated layer thickness that is deposited on the device substrate of wet etching is more than or equal to 100 dusts and less than 200 dusts;
The oxide layer that adopts the oxide layer of TEOS deposition when the oxide layer of said deposition is included in the side wall barrier layer of making grid and be used for being deposited as making overlay area on the device substrate not generate metal silicide layer.
2. the method for claim 1 is characterized in that, the oxidated layer thickness that is deposited on the device substrate of said wet etching is 100 dusts.
3. the method for claim 1 is characterized in that, said sacrifice layer of etching and the process that covers the pad oxide-film of device substrate are:
After adopting dry etching, adopt wet etching again.
4. method as claimed in claim 3 is characterized in that, on the device substrate of device, leaves the TEOS and pad oxide-film of 100 dust thickness behind the said dry etching.
5. method as claimed in claim 3 is characterized in that, the thickness of said pad oxide-film is 155 dusts;
The thickness of said deposition of sacrificial layer is 800 dusts;
Said sacrifice layer of said employing wet etching and the wet etching amount when covering the pad oxide-film of device substrate are 90 dusts.
6. the method for claim 1 is characterized in that, before the oxide layer that is deposited on the wet etching device substrate, this method also comprises:
Adopt dry etching, it is 100 dusts that the oxide layer that is deposited on the device substrate is etched into thickness.
7. method as claimed in claim 6 is characterized in that the oxidated layer thickness that is deposited on the device substrate that said dry etching obtains is 100 dusts;
The wet etching amount of said employing wet etching is 30 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100470063A CN101826465B (en) | 2009-03-04 | 2009-03-04 | Method for preventing gap below side wall barrier layer during self-aligning silicide process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100470063A CN101826465B (en) | 2009-03-04 | 2009-03-04 | Method for preventing gap below side wall barrier layer during self-aligning silicide process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101826465A CN101826465A (en) | 2010-09-08 |
| CN101826465B true CN101826465B (en) | 2012-05-30 |
Family
ID=42690304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100470063A Expired - Fee Related CN101826465B (en) | 2009-03-04 | 2009-03-04 | Method for preventing gap below side wall barrier layer during self-aligning silicide process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101826465B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107851574B (en) * | 2015-07-15 | 2021-08-13 | 三菱电机株式会社 | Method for manufacturing semiconductor device |
| CN109037054B (en) * | 2018-07-13 | 2020-11-24 | 上海华力集成电路制造有限公司 | Manufacturing method of grid side wall |
| CN111366618B (en) * | 2020-04-01 | 2022-07-29 | 上海华虹宏力半导体制造有限公司 | Temperature and humidity sensor and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101150064A (en) * | 2006-09-21 | 2008-03-26 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
| CN101286476A (en) * | 2007-04-12 | 2008-10-15 | 上海宏力半导体制造有限公司 | Method of using silicon oxide layer as doped opaque layer and blocking layer of metal silicide |
-
2009
- 2009-03-04 CN CN2009100470063A patent/CN101826465B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101150064A (en) * | 2006-09-21 | 2008-03-26 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
| CN101286476A (en) * | 2007-04-12 | 2008-10-15 | 上海宏力半导体制造有限公司 | Method of using silicon oxide layer as doped opaque layer and blocking layer of metal silicide |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101826465A (en) | 2010-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8563426B2 (en) | Shrinkage of contact elements and vias in a semiconductor device by incorporating additional tapering material | |
| US8871638B2 (en) | Semiconductor device and method for fabricating the same | |
| US20070122952A1 (en) | Semiconductor device with a dummy gate and a method of manufacturing a semiconductor device with a dummy gate | |
| CN1770428A (en) | Method of fabricating flash memory device | |
| US9263321B2 (en) | Semiconductor device and manufacturing method thereof | |
| US8357577B2 (en) | Manufacturing method of semiconductor device having vertical type transistor | |
| CN101826465B (en) | Method for preventing gap below side wall barrier layer during self-aligning silicide process | |
| CN1266762C (en) | Transistor forming method | |
| US7524732B2 (en) | Semiconductor device with L-shaped spacer and method of manufacturing the same | |
| US6858494B2 (en) | Structure and fabricating method with self-aligned bit line contact to word line in split gate flash | |
| CN102130062B (en) | Manufacturing method of memory | |
| CN103137559B (en) | The removing method of dummy poly and the manufacture method of CMOS metal gates | |
| CN107731730B (en) | Method for forming semiconductor structure | |
| CN102468175A (en) | Method for manufacturing transistor | |
| CN102543878B (en) | Manufacturing method of storage | |
| TWI395290B (en) | Flash memory and method of fabricating the same | |
| CN104377160A (en) | Metal interconnector structure and process thereof | |
| CN211929495U (en) | Grid structure | |
| CN103377896A (en) | Method for manufacturing high-k metal-gate device | |
| JP2007035728A (en) | Semiconductor device and manufacturing method thereof | |
| CN100394552C (en) | Contact window opening formation and its production of semiconductor component | |
| CN111627993B (en) | Grid structure and manufacturing method thereof | |
| TWI512894B (en) | Metal interconnect structure and process thereof | |
| KR100973266B1 (en) | Method of manufacturing of semiconductor | |
| KR100882721B1 (en) | Semiconductor device and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20200304 |