KR20040001228A - Method for manufacturing isolation layer in semiconductor device - Google Patents
Method for manufacturing isolation layer in semiconductor device Download PDFInfo
- Publication number
- KR20040001228A KR20040001228A KR1020020036361A KR20020036361A KR20040001228A KR 20040001228 A KR20040001228 A KR 20040001228A KR 1020020036361 A KR1020020036361 A KR 1020020036361A KR 20020036361 A KR20020036361 A KR 20020036361A KR 20040001228 A KR20040001228 A KR 20040001228A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- film
- oxide film
- layer
- pad
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000002955 isolation Methods 0.000 title abstract description 26
- 239000004065 semiconductor Substances 0.000 title abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 40
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 보다 구체적으로는, 소자의 전기적 특성을 균일하게 유지할 수 있는 반도체 소자의 소자분리막제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and more particularly, to a method for manufacturing a device isolation film of a semiconductor device capable of maintaining the electrical characteristics of the device uniformly.
일반적으로 실리콘 웨이퍼에 형성되는 반도체 장치는 개개의 회로 패턴들을 전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 특히 반도체 장치가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 것뿐만 아니라 소자 분리 영역의 축소에 대한 연구가 활발히 진행되고 있다. 그 이유는 소자 분리 영역의 형성은 모든 제조 단계에 있어서 초기 단계의 공정으로서, 활성영역의 크기 및 후공정 단계의 공정마진을 좌우하게 되기 때문이다.In general, semiconductor devices formed on silicon wafers include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices have been highly integrated and miniaturized, research into not only the size of each individual device but also the device isolation region has been actively conducted. The reason for this is that the formation of the device isolation region is an initial step in all the manufacturing steps, and depends on the size of the active area and the process margin of the post-process step.
일반적으로 반도체 장치의 제조에 널리 이용되는 로코스 소자분리 방법은 공정이 간단하다는 이점이 있지만 256M DRAM급 이상의 고집적화되는 반도체 소자에 있어서는 소자 분리 영역의 폭이 감소함에 따라 버즈비크(Bird' Beak)에 의한 펀 치쓰루(Punch-Through)와 소자 분리막의 두께 감소로 인하여 그 한계점에 이르고 있다.In general, the Locos device isolation method widely used in the manufacture of semiconductor devices has the advantage of simple process, but in the case of highly integrated semiconductor devices of 256M DRAM level or more, the width of the device isolation region decreases in the bird's beak. Due to the punch-through and thickness reduction of the device isolation layer, the limit point is reached.
이에따라, 고집적화된 반도체 장치의 소자 분리에 적합한 기술로 트렌치를 이용한 소자 분리 방법, 예컨대 샬로우 트렌치 분리방법(Shallow Trench Isolation: 이하, STI)이 제안되었다.Accordingly, a device isolation method using a trench, such as a shallow trench isolation method (STI), has been proposed as a technique suitable for device isolation of highly integrated semiconductor devices.
도 1a 및 도 1f는 종래 기술에 따른 반도체 소자의 소자분리막 제조방법을 설명하기 위한 제조공정도이다.1A and 1F are manufacturing process diagrams illustrating a method of fabricating a device isolation film of a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 소자분리막 제조방법은, 도 1a에 도시된 바와 같이, 실리콘 기판(10) 상에 통상의 화학기상증착(Chemical Vapor Deposition) 공정에 의해 버퍼 역할을 하는 패드 산화막(12)과 산화를 억제하는 패드질화막(14)을 순차적으로 형성한다. 그 다음, 상기 패드 질화막 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(50)을 형성한다.In the method of manufacturing a device isolation film of a semiconductor device according to the related art, as illustrated in FIG. 1A, a pad oxide film 12 serving as a buffer by a conventional chemical vapor deposition process is formed on a silicon substrate 10. The pad nitride film 14 which suppresses excessive oxidation is sequentially formed. Next, a photoresist pattern 50 is formed on the pad nitride layer to form an element isolation region.
이 후, 도 1b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하여 패드 질화막, 패드 산화막 및 실리콘 기판을 소정 깊이만큼 식각하여, 샬로우 트렌치(16)를 형성한다.Subsequently, as illustrated in FIG. 1B, the shallow trench 16 is formed by etching the pad nitride film, the pad oxide film, and the silicon substrate by a predetermined depth, using the photoresist pattern as a mask.
이어, 상기 감광막 패턴을 제거하고, 도 1c에 도시된 바와 같이, 트렌치 식각 과정에서 실리콘 표면의 데미지를 제거하기 위하여 세정 공정(미도시)을 진행한 후, 고온에서 사이드 월 산화(side wall oxidation)공정을 수행하여 트렌치(16) 내에 산화막(18)을 형성한다.Subsequently, the photoresist pattern is removed, and as shown in FIG. 1C, a cleaning process (not shown) is performed to remove damage of the silicon surface during the trench etching process, and then side wall oxidation is performed at a high temperature. The process is performed to form an oxide film 18 in the trench 16.
그런 다음, 도 1d에 도시된 바와 같이, 상기 산화막(18)이 형성된 트렌치(16)에 고온의 산화막(18) 형성 후 리플래쉬(reflash)를 향상시키기 위해 실리콘 질화막(20) 및 실리콘 산화막(22)을 차례로 형성한다. 이 후, 상기 실리콘 산화막(22)을 포함한 기판 전면에 갭필옥사이드막(24)을 형성한다. 이때, 상기 필옥사드막(24)으로는 고밀도 플라즈마(High Density Plasma:이하, HDP) 산화막을 이용한다.Then, as shown in FIG. 1D, after forming the high temperature oxide film 18 in the trench 16 where the oxide film 18 is formed, the silicon nitride film 20 and the silicon oxide film 22 to improve reflash. ) In turn. Thereafter, a gap fill oxide layer 24 is formed on the entire substrate including the silicon oxide layer 22. In this case, a high density plasma (HDP) oxide film is used as the filoxad film 24.
이 후, 도 1e에 도시된 바와 같이, 상기 갭필옥사이드막 및 실리콘 산화막을 씨엠피(CMP:Chemical Mechnical Polishing) 공정을 진행하여 실리콘 질화막(20)을 노출시킨다.Subsequently, as shown in FIG. 1E, the gap fill oxide layer and the silicon oxide layer are subjected to a chemical mechanical polishing (CMP) process to expose the silicon nitride layer 20.
이어, 도 1f에 도시된 바와 같이, 상기 실리콘 질화막 및 패드 질화막을 H3PO4습식액을 이용하여 습식 식각하여 반도체소자의 소자분리막(L)을 형성한다.Subsequently, as shown in FIG. 1F, the silicon nitride film and the pad nitride film are wet-etched using a H 3 PO 4 wet liquid to form the device isolation layer L of the semiconductor device.
그러나, 종래 기술에서는 STI 식각 공정으로 인한 실리콘 기판 표면의 데미지를 제거하기 위해서 고온의 열산화막을 형성하게 되는데, 이 과정에서 후속의 씨엠피 공정의 베리어로 사용되는 패드 질화막의 표면이 산화되어 산화질화막이 형성된다. 따라서, H3PO4습식액을 이용하여 잔류된 실리콘 질화막 및 패드 질화막 식각 공정에서 패드 질화막 표면의 산화질화막을 제거하기 위해 실제 남아있는 실리콘 질화막 및 패드 질화막의 타겟보다 훨씬 많은 식각 시간이 소요되었다.However, in the prior art, a high temperature thermal oxide film is formed in order to remove damage on the surface of the silicon substrate due to the STI etching process. In this process, the surface of the pad nitride film used as a barrier of the subsequent CMP process is oxidized to oxidize the nitride film. Is formed. Therefore, in order to remove the oxynitride on the surface of the pad nitride layer in the silicon nitride film and the pad nitride film etching process using the H 3 PO 4 wet solution, much longer etching time was required than the target of the silicon nitride film and the pad nitride film.
또한, 상기 습식 식각 공정에서 과도한 식각으로 인해 실리콘 질화막이 손실됨으로서 트렌치 상측 모서리 부분에 움푹 패인 형상의 모우트(maot)가 관찰되었다. 따라서, 상기 모우트가 심한 경우 게이트 전극용 다결정 실리콘 식각 시 다결정 실리콘 잔류물이 남게 되어 소자의 문턱 전압 및 정상적인 동작 전류의 거동을 방해하여 디바이스의 품질을 저하시키는 문제점이 있었다.In addition, as the silicon nitride film is lost due to excessive etching in the wet etching process, a recessed shape moot was observed in the upper corner portion of the trench. Therefore, when the severity is severe, polycrystalline silicon residues remain when the polycrystalline silicon is etched for the gate electrode, which hinders the behavior of the threshold voltage and the normal operating current of the device, thereby degrading the quality of the device.
따라서, 상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, 실리콘 질화막의 손실에 따른 모우트 발생을 최소화하여 소자의 전기적 특성을 균일하게 유지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는 것이다.Accordingly, an object of the present invention for solving the above problems is to provide a method for forming a device isolation film of a semiconductor device that can maintain the electrical characteristics of the device uniformly by minimizing the generation of the moat caused by the loss of the silicon nitride film.
도 1a 및 도 1f는 종래 기술에 따른 반도체 소자의 소자분리막 제조방법을 설명하기 위한 제조공정도.1A and 1F are manufacturing process diagrams for explaining a device isolation film manufacturing method of a semiconductor device according to the prior art.
도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 소자분리막 제조방법을 설명하기 위한 제조공정도.Figure 2a to 2g is a manufacturing process diagram for explaining a device isolation film manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
100. 실리콘 기판 102,103. 패드 산화막100. Silicon substrate 102,103. Pad oxide
104,105. 패드 질화막 106. 트렌치104,105. Pad Nitride 106. Trench
108. 산화막 120,121. 실리콘 질화막108. Oxide films 120,121. Silicon nitride film
122,123. 실리콘 산화막 124, 125. 갭필옥사이드막122,123. Silicon oxide films 124 and 125. gap fill oxide films
M. 소자분리막 150 : 감광막 패턴M. Device Separator 150: Photoresist Pattern
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성 방법은, 실리콘 기판 상에 패드산화막과 패드 질화막을 차례로 증착하는 단계; 포토리쏘그라피 공정에 의해 패드 질화막과 패드 산화막의 소정부분을 식각하여 기판에 트렌치를 형성하는 단계; 트렌치 내부에 열산화막을 형성하는 단계; 열산화막을포함한 기판 전면에 실리콘 질화막 및 실리콘 산화막을 차례로 형성하는 단계; 실리콘 산화막을 포함한 기판 전면에 갭필옥사이드막을 형성하는 단계; 실리콘 질화막을 식각 베리어로 하고 갭필옥사이드막 및 실리콘 산화막을 씨엠피하는 단계; 실리콘 질화막을 건식 식각하는 단계; 및 패드 질화막을 습식 식각하는 단계를 포함한 것을 특징으로 한다.A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of depositing a pad oxide film and a pad nitride film on a silicon substrate in sequence; Etching a predetermined portion of the pad nitride film and the pad oxide film by a photolithography process to form a trench in the substrate; Forming a thermal oxide film inside the trench; Sequentially forming a silicon nitride film and a silicon oxide film on the entire surface of the substrate including the thermal oxide film; Forming a gap fill oxide film on the entire surface of the substrate including the silicon oxide film; CMP of the silicon nitride film as an etching barrier and the gapfill oxide film and the silicon oxide film; Dry etching the silicon nitride film; And wet etching the pad nitride layer.
상기 패드 질화막은 저압 화학기상증착 공정에 의해 500∼600Å 두께로 형성하며, 반응가스로 CHF3, CF4, O2및 Ar 혼합가스를 이용하는 것이 바람직하다. 또한, 상기 실리콘 질화막을 건식 식각하는 단계에서, 상기 산화막 형성 시에 패드 질화막 표면에 형성된 산화질화막도 함께 제거한다. 한편, 상기 패드 질화막을 습식 식각하는 단계는 H3PO4습식액을 이용하며, 패드 질화막 두께보다 20% 오버 식각하는 것이 바람직하다.The pad nitride film is formed to a thickness of 500 to 600 kPa by a low pressure chemical vapor deposition process, and it is preferable to use a mixed gas of CHF 3 , CF 4 , O 2 and Ar as a reaction gas. In the dry etching of the silicon nitride film, the oxynitride film formed on the surface of the pad nitride film is also removed at the time of forming the oxide film. Meanwhile, the wet etching of the pad nitride layer may be performed by using H 3 PO 4 wet liquid, and etching 20% over the thickness of the pad nitride layer.
이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 제조공정도이다.2A to 2G are manufacturing process diagrams for explaining a method of forming a device isolation film of a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 실리콘 기판(100) 상에 열산화 공정에 의해 버퍼 역할을 하는 패드 산화막(102)과 저압 화학기상증착(Low Pressure Chemical Vapor Deposition) 공정에 의해 산화를 억제하는 패드 질화막(104)을 순차적으로 형성한다. 이때, 상기 패드 질화막(104)은 500∼600Å 두께로 형성한다.First, as shown in FIG. 2A, oxidation is inhibited by a pad oxide layer 102 and a low pressure chemical vapor deposition process, which act as a buffer by a thermal oxidation process on the silicon substrate 100. The pad nitride film 104 is formed sequentially. At this time, the pad nitride film 104 is formed to a thickness of 500 ~ 600Å.
다음, 상기 패드 질화막 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(150)을 형성한다. 이때, 감광막 패턴(150)은 얇은 폭의 소자 분리막을 형성하기 위하여 해상도가 우수한 DUV(deep ultra violet)광원을 이용하여 형성한다.Next, a photoresist pattern 150 is formed on the pad nitride layer to form a device isolation region. In this case, the photoresist pattern 150 is formed using a deep ultra violet (DUV) light source having excellent resolution to form a thin device isolation layer.
이 후, 도 2b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하고 패드 질화막, 패드 산화막 및 실리콘 기판을 소정 깊이만큼 식각하여 샬로우 트렌치(106)를 형성한다.Thereafter, as illustrated in FIG. 2B, the shallow trench 106 is formed by etching the pad nitride film, the pad oxide film, and the silicon substrate by a predetermined depth, using the photoresist pattern as a mask.
이어, 상기 감광막 패턴을 제거하고, 도 2c에 도시된 바와 같이, 트렌치 식각 과정에서 실리콘 표면의 데미지를 제거하기 위하여 세정 공정(미도시)을 진행한 후, 고온에서 사이드 월 산화공정을 수행하여 트렌치(106) 내부에 산화막(108)을 형성한다. 이때, 상기 고온 산화 공정을 통해 패드 질화막 표면에는 산화질화막(미도시)이 형성된다.Subsequently, the photoresist layer pattern is removed, and as shown in FIG. 2C, a cleaning process (not shown) is performed to remove the damage of the silicon surface during the trench etching process, and then the sidewall oxidation process is performed at a high temperature to perform the trench. An oxide film 108 is formed inside 106. In this case, an oxynitride film (not shown) is formed on the surface of the pad nitride film through the high temperature oxidation process.
그런 다음, 도 2d에 도시된 바와 같이, 상기 산화막(108) 형성 후 리플래쉬를 향상시키기 위해 저압 화학기상증착 공정에 의해 실리콘 질화막(120)을 형성한다. 이때, 상기 실리콘 질화막(120)은 30∼60Å 두께로, 바람직하게는 50Å두께로 형성한다. 이 후, 후속의 갭필옥사이드막 형성 시 갭필력을 향상시키기 위해 실리콘 산화막(122)을 형성하고 나서 갭필옥사이드막(124)을 형성한다. 이때, 갭필옥사이드막(124) 형성은 HDP 산화막을 이용한다.Then, as illustrated in FIG. 2D, the silicon nitride film 120 is formed by a low pressure chemical vapor deposition process to improve refresh after the oxide film 108 is formed. In this case, the silicon nitride film 120 is formed to a thickness of 30 ~ 60Å, preferably 50ÅÅ. Thereafter, the silicon oxide film 122 is formed in order to improve the gap peeling force during the subsequent gap fill oxide film formation, and then the gap fill oxide film 124 is formed. In this case, the gap fill oxide film 124 is formed using an HDP oxide film.
이어서, 도 2e에 도시된 바와 같이, 상기 실리콘 질화막(120)을 식각 베리어로 하고 갭필옥사이드막, 실리콘 산화막에 씨엠피 공정을 진행한다. 이때, 상기 씨엠피 공정은 높은 선택비를 가진 슬러리를 적용함으로서, 패드 질화막 손실을 50Å 두께 이하로 줄일 수 있다. 따라서, 본 발명에서는 패드 질화막의 두께를 통상의 것보다 얇은 500∼600Å 두께로 형성한다. 도면부호 121은 씨엠피 공정 후에 잔류된 실리콘 질화막을 나타낸 것이고, 도면부호 125는 잔류된 갭필옥사이드막을 나타낸 것이다.Subsequently, as shown in FIG. 2E, the silicon nitride film 120 is used as an etching barrier, and a CMP process is performed on the gap fill oxide film and the silicon oxide film. In this case, in the CMP process, by applying a slurry having a high selectivity, the pad nitride film loss can be reduced to less than 50 Å thickness. Therefore, in the present invention, the thickness of the pad nitride film is formed to a thickness of 500 to 600 kPa, which is thinner than usual. Reference numeral 121 denotes a silicon nitride film remaining after the CMP process, and reference numeral 125 denotes a remaining gap fill oxide film.
그런 다음, 도 2f에 도시된 바와 같이, 씨엠피 공정이 완료된 후 씨엠피 베리어로 사용된 실리콘 질화막을 건식 식각한다. 이때, 상기 실리콘 질화막 건식 식각 공정에서 상기 고온 산화 공정 시 패드 질화막 표면에 형성된 산화질화막도 함께 제거된다.Then, as illustrated in FIG. 2F, the silicon nitride film used as the CMP barrier is dry-etched after the CMP process is completed. In this case, the oxynitride film formed on the surface of the pad nitride film during the high temperature oxidation process in the silicon nitride film dry etching process is also removed.
이 후, 도 2g에 도시된 바와 같이, 패드 질화막을 H3PO4습식액을 이용하여 습식 식각하여 반도체소자의 소자분리막(M)을 형성한다.Thereafter, as shown in FIG. 2G, the pad nitride layer is wet-etched using the H 3 PO 4 wet solution to form the device isolation layer M of the semiconductor device.
상기한 바와 같이. 본 발명에 따른 반도체 소자의 소자분리막 제조방법은 패드 질화막 및 패드 질화막 표면에 형성된 산화질화막을 건식 식각에 의해 제거한 후에, 실리콘 질화막을 습식 식각함으로써, 습식 식각에 소요되는 시간을 단축시킬 수 있으며, 실리콘 질화막의 손실에 따른 모우트 발생을 최소화하여 소자의 전기적 특성을 균일하게 유지할 수 있다.As mentioned above. In the method of manufacturing a device isolation film of a semiconductor device according to the present invention, after the etching of the silicon nitride film and the silicon nitride film is removed after dry etching the pad nitride film and the oxynitride film formed on the surface of the pad nitride film, the time required for wet etching can be shortened. By minimizing the occurrence of the moor due to the loss of the nitride film it is possible to maintain the electrical characteristics of the device uniformly.
또한, STI 형성 공정 중 높은 선택비를 가진 슬러리를 이용하여 씨엠피를 실시함으로서, 패드 질화막의 두께를 하향 조절할 수 있으며, 웨이퍼를 균일하게 평탄화할 수 있다.In addition, by performing CMP using a slurry having a high selectivity during the STI forming process, the thickness of the pad nitride film can be adjusted downward, and the wafer can be uniformly planarized.
한편, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시 할 수 있다.On the other hand, various changes can be made without departing from the spirit of the invention.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020036361A KR20040001228A (en) | 2002-06-27 | 2002-06-27 | Method for manufacturing isolation layer in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020036361A KR20040001228A (en) | 2002-06-27 | 2002-06-27 | Method for manufacturing isolation layer in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040001228A true KR20040001228A (en) | 2004-01-07 |
Family
ID=37312999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020036361A KR20040001228A (en) | 2002-06-27 | 2002-06-27 | Method for manufacturing isolation layer in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040001228A (en) |
-
2002
- 2002-06-27 KR KR1020020036361A patent/KR20040001228A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20010046153A (en) | Method of manufacturing trench type isolation layer in semiconductor device | |
| KR20010008579A (en) | Method for forming sti-type field oxide layer of a semiconductor device | |
| KR100460770B1 (en) | Method for forming trench type isolation layer in semiconductor device | |
| KR100510772B1 (en) | Formation method of silicon on insulator substrate for semiconductor | |
| KR20080084256A (en) | Method for forming shallow trench isolation of semiconductor device | |
| KR20070002945A (en) | Method for forming trench type isolation layer in semiconductor device | |
| KR20040001228A (en) | Method for manufacturing isolation layer in semiconductor device | |
| KR100419754B1 (en) | A method for forming a field oxide of a semiconductor device | |
| KR100429555B1 (en) | Method for forming trench type isolation layer in semiconductor device | |
| KR100486875B1 (en) | Isolation layer in a semiconductor device and a method of forming the same | |
| KR20030052663A (en) | method for isolating semiconductor device | |
| KR100548571B1 (en) | Method for fabricating isolation layer of semiconductor device | |
| KR100499409B1 (en) | Method for forming shallow trench isolation film in semiconductor device | |
| KR100561974B1 (en) | A Manufacturing Method of Semiconductor Element | |
| KR20020003031A (en) | Method for forming isolation in semiconductor device | |
| KR100800106B1 (en) | Method for forming trench isolation layer in semiconductor device | |
| KR20040105980A (en) | The method for forming shallow trench isolation in semiconductor device | |
| KR100520177B1 (en) | A method for forming a field oxide of semiconductor device | |
| KR100864845B1 (en) | Method for forming the Isolation Layer of Semiconductor Device | |
| KR20040001224A (en) | Method for manufacturing isolation layer in semiconductor device | |
| KR20050012652A (en) | Method for forming element isolation layer of semiconductor device | |
| KR20030000490A (en) | Manufacturing method for semiconductor device | |
| KR20050118489A (en) | Method for isolation in semiconductor device | |
| KR20060010241A (en) | Method for forming trench type isolation layer in semiconductor device | |
| KR20050010226A (en) | Method for forming trench type isolation layer in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |