KR20080084256A - Method for forming shallow trench isolation of semiconductor device - Google Patents

Method for forming shallow trench isolation of semiconductor device Download PDF

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Publication number
KR20080084256A
KR20080084256A KR1020070025689A KR20070025689A KR20080084256A KR 20080084256 A KR20080084256 A KR 20080084256A KR 1020070025689 A KR1020070025689 A KR 1020070025689A KR 20070025689 A KR20070025689 A KR 20070025689A KR 20080084256 A KR20080084256 A KR 20080084256A
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KR
South Korea
Prior art keywords
film
forming
device isolation
nitride film
semiconductor device
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KR1020070025689A
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Korean (ko)
Inventor
김영석
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주식회사 하이닉스반도체
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Priority to KR1020070025689A priority Critical patent/KR20080084256A/en
Publication of KR20080084256A publication Critical patent/KR20080084256A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Abstract

The present invention relates to a method of forming a device isolation film of a semiconductor device, and to forming a silicon nitride film and depositing polysilicon as a buffer on the upper portion of the device isolation film during the formation of the device isolation film to reduce the loss of the liner nitride film generated in the deposition process. The present invention relates to a method for preventing deterioration of a device resulting from device isolation film formation, which can be prevented and improved insulator properties.

Description

Method for forming Shallow Trench Isolation of semiconductor device

1A to 1F are process diagrams showing a conventional STI forming process.

2a to 2h is a process chart showing the STI forming process of the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 110: semiconductor substrate

12, 112: first oxide film

14, 114: pad nitride film

16, 116: second oxide film

18, 118: liner nitride film

22, 122: buried oxide film

120: polysilicon film

124: SiO 2

m1: moat site

The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, a liner that generates an oxide film for a subsequent device isolation film in a deposition process by depositing and oxidizing polysilicon as a buffer thereon after depositing a liner nitride film when forming a device isolation film. The present invention relates to a method for preventing loss of a nitride film and improving insulator properties, thereby ultimately preventing deterioration of a device resulting from device isolation film formation.

1 is a view for explaining a device isolation film forming method of a semiconductor device according to the prior art.

A pad nitride film 14 that is formed on the semiconductor substrate 10 by thermal oxidation and is used as a hard mask during STI (Shallow Trench Isolation) etching on the first oxide film 12. ) (See FIG. 1A).

Then, after the pad nitride film 14 is selectively etched, the semiconductor substrate 10 is etched using the nitride film pattern as a hard mask to form a trench in a region intended as an isolation region (see FIG. 1B).

Then, thermal oxidation is performed to remove etch damage of the etched semiconductor substrate 10 to form a second oxide film 16 as a sidewall oxide film on the trench surface (see FIG. 1C), and the pad nitride film 14 ), And then a liner nitride film 18 is formed on the surface of the semiconductor substrate including the trench (see FIG. 1D).

After the above process, the resultant front buried oxide film 22 is formed (see FIG. 1E) and planarized to form a device isolation film of the semiconductor device (see FIG. 1F).

As shown in FIG. 1F, in the device isolation film forming process according to the conventional method, when the buried oxide film 22, which is a device isolation oxide, is deposited by a high density plasma deposition process, deposition and etching are repeated, thereby causing loss of the liner nitride film 18. As a result, a mott (m1) phenomenon occurs in which the edge of the isolation layer is deeply recessed.

This mortise decreases the threshold voltage (V t ) to increase the leakage current, which adversely affects the reliability of the semiconductor device.

It is an object of the present invention to provide a device isolation film formation method which can prevent deterioration of devices resulting from the device isolation film formation as described above.

In order to achieve the above object, the present invention prevents the loss of the liner nitride film generated in the deposition process of the oxide film for subsequent device isolation film by depositing and oxidizing polysilicon as a buffer thereon after depositing the liner nitride film when forming the device isolation film, and insulator characteristics. The present invention provides a device isolation film formation method capable of improving the device isolation and ultimately preventing device deterioration resulting from device isolation film formation.

The present invention provides a method of forming a trench in a region defined as an isolation region on a semiconductor substrate,

Forming a sidewall oxide film on the trench surface;

Forming a liner nitride film on a surface of the semiconductor substrate including the trench;

Forming a polysilicon film on the entire surface of the resultant,

Forming an oxide film for device isolation on the entire surface of the resultant;

Flattening the resultant by performing a chemical mechanical polishing process using the liner nitride film as an etch stop film;

It provides a method for forming a device isolation film of a semiconductor device comprising the step of oxidizing the polysilicon film by performing an oxidation process on the result.

The process may further include removing the liner nitride layer remaining on the semiconductor substrate by performing a wet etching process after the planarization process and before the oxidation process.

The polysilicon film is preferably deposited to a thickness of 50 ~ 100Å.

In addition, the polysilicon film is preferably deposited to maintain a low concentration by depositing a concentration of 1E15 ~ 1E19. Deposition at a low concentration of the polysilicon film is intended to facilitate oxidation after deposition. In other words, if the concentration of polysilicon is too high, crystal defects may occur during the oxidation process, so that low doping polysilicon is used to reduce conductivity and to make the oxidation uniform.

On the other hand, the oxidation process is to convert the polysilicon film of the conductive material to SiO 2 to act as an insulator.

In addition, the present invention provides a semiconductor device manufactured by the device isolation film forming method of the semiconductor device.

2A to 2H are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device of the present invention.

A first oxide film 112 is formed on the semiconductor substrate 110 by thermal oxidation, and a pad nitride film 114 used as a hard mask during STI etching is formed on the first oxide film 112 (see FIG. 2A). .

Thereafter, the pad nitride layer 114 is selectively etched, and the semiconductor substrate 110 is etched using the nitride layer pattern as a hard mask to form a trench in a region designated as an isolation region (see FIG. 2B).

Then, thermal oxidation is performed to remove the etch damage of the etched semiconductor substrate 110 to form a second oxide film 116 as a sidewall oxide film on the trench surface (see FIG. 2C), and the pad nitride film 114 is removed. Next, a liner nitride film 118 is formed on the surface of the semiconductor substrate including the trench (see FIG. 2D).

Next, a polysilicon film 120 is formed over the liner nitride film 118 (see FIG. 2E).

After the above process, the buried oxide film 122 is formed on the entire surface of the resultant device, and the polysilicon film 120 is damaged instead of the liner nitride film 118 in the process of depositing the buried oxide film 122. (See FIG. 2F).

Next, the resultant is planarized to the liner nitride layer 118 with an etch stop layer, and the device isolation layer of the semiconductor device is formed by removing the liner nitride layer 118 remaining on the semiconductor substrate by a wet etching process. The loss of the nitride film, that is, the mott phenomenon, does not appear between the device isolation region and the device isolation region (see FIG. 2G).

When the oxidation process is performed after the above process, the upper portion of the polysilicon film 120, which is a conductive material, is oxidized to form SiO 2. 124, which can serve as an insulator (see FIG. 2H).

As can be seen in the figure, in the process of the present invention, the polysilicon film is further formed and oxidized on top of the liner nitride film when forming the device isolation film, so that the polysilicon film acts as a buffer during the subsequent deposition of the gapfill oxide film, resulting in loss of the liner nitride film. Can be reduced and the insulator characteristics can be improved.

Preferred embodiments of the present invention are for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

As described above, the present invention prevents the loss of the liner nitride film generated in the process of depositing the oxide film for subsequent device isolation film by depositing and oxidizing polysilicon as a buffer on the upper part of the liner nitride film deposition when forming the device isolation film and insulator characteristics Can be improved, and ultimately, deterioration of the element due to device isolation film formation can be prevented.

Claims (5)

Forming a trench in a predetermined region as an isolation region on the semiconductor substrate; Forming a sidewall oxide film on the trench surface; Forming a liner nitride film on a surface of the semiconductor substrate including the trench; Forming a polysilicon film on the entire surface of the resultant, Forming an oxide film for device isolation on the entire surface of the resultant; Flattening the resultant by performing a chemical mechanical polishing process using the liner nitride film as an etch stop film; And oxidizing the polysilicon film by performing an oxidation process on the resultant. The method of claim 1, And removing the liner nitride film remaining on the semiconductor substrate by performing a wet etching process after the planarization process and before the oxidation process. The method of claim 1, The polysilicon film is a device isolation film forming method of a semiconductor device which is deposited to a thickness of 50 ~ 100Å. The method of claim 1, Wherein the polysilicon film is deposited at a concentration of 1E15 to 1E19. The semiconductor device manufactured by the method of Claim 1.
KR1020070025689A 2007-03-15 2007-03-15 Method for forming shallow trench isolation of semiconductor device KR20080084256A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105826232A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor structure
US10062581B2 (en) 2015-07-09 2018-08-28 Samsung Electronics Co., Ltd. Methods of forming an isolation structure and methods of manufacturing a semiconductor device including the same
US11605714B2 (en) 2018-09-05 2023-03-14 Samsung Electronics Co., Ltd. Semiconductor device including insulating layers and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105826232A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor structure
US10062581B2 (en) 2015-07-09 2018-08-28 Samsung Electronics Co., Ltd. Methods of forming an isolation structure and methods of manufacturing a semiconductor device including the same
US11605714B2 (en) 2018-09-05 2023-03-14 Samsung Electronics Co., Ltd. Semiconductor device including insulating layers and method of manufacturing the same

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