CN114038744A - MOS transistor manufacturing method and MOS transistor - Google Patents
MOS transistor manufacturing method and MOS transistor Download PDFInfo
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- CN114038744A CN114038744A CN202111244747.8A CN202111244747A CN114038744A CN 114038744 A CN114038744 A CN 114038744A CN 202111244747 A CN202111244747 A CN 202111244747A CN 114038744 A CN114038744 A CN 114038744A
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- protective layer
- sti
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- gate oxide
- etching
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 43
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 9
- 238000002955 isolation Methods 0.000 abstract 1
- 101000658644 Homo sapiens Tetratricopeptide repeat protein 21A Proteins 0.000 description 9
- 102100034913 Tetratricopeptide repeat protein 21A Human genes 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 241000282326 Felis catus Species 0.000 description 5
- 241001391944 Commicarpus scandens Species 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a manufacturing method of an MOS transistor and the MOS transistor, wherein a substrate is provided, a plurality of protruding STI are formed on the substrate, groove regions among the STI are respectively defined as a low-voltage device region and a medium-voltage device region, a gate oxide layer is formed in the groove region by growth, and then a first protective layer is formed on the gate oxide layer; covering a first photoresist on the surface of the first protective layer, exposing the first protective layer of the gate oxide layer through photoetching, and simultaneously exposing partial STI (shallow trench isolation) on two sides of the gate oxide layer; simultaneously exposing partial STI on two sides of the gate oxide layer, and etching the exposed STI; removing the first photoresist and the first protective layer; growing a second protective layer; etching the exposed second protective layer, and continuously etching the substrate to form a polysilicon groove; growing a connecting layer at the polycrystalline silicon groove; the second protective layer and the second photoresist are removed through etching to obtain the MOS transistor, so that defects are avoided, and the reliability and yield of the medium-voltage device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of an MOS transistor and the MOS transistor.
Background
The existing gate oxide process is to directly grow an oxide layer on a silicon substrate, but because the gate oxide thickness of a medium-voltage MOS tube is thicker, the medium-voltage gate oxide grown according to the existing process is higher than that of a normal-voltage device, and after a dielectric layer zero chemical mechanical grinding process, the residual height of a pseudo gate in a medium-voltage device area is lower, which affects the formation of a metal gate and enables the metal gate in the medium-voltage device area to be thinner. Because the total area of the medium-voltage device is small, under the limit condition, after the zero chemical mechanical grinding process of the electric layer, the false gate of the medium-voltage device area is completely ground, a metal gate cannot be formed, and the yield and the reliability of a product are further damaged.
Introduction to the substrate prior to entering the IOX cycle as shown in fig. 9, the STI oxide covering the corners of the midgate oxide has a width of 118.9 angstroms and a height of 105.3 angstroms. This portion of the oxide will block the etching of the underlying silicon, resulting in silicon protrusions at the corners, as shown in fig. 10. During the growth of the medium voltage gate oxide, the silicon at the corners of the medium voltage gate oxide is difficult to be completely oxidized, and finally a cat-ear defect is formed (as shown in fig. 11), which causes the corners of the medium voltage gate oxide to be thinner and easy to break down after voltage is applied.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a manufacturing method of an MOS transistor and the MOS transistor, which solve the problems that the edge of a gate oxide in the manufacturing of a semiconductor integrated circuit is thinner and is easy to break down after voltage is applied.
In order to achieve the purpose, the invention is realized by the following technical scheme: a manufacturing method of a MOS transistor at least comprises the following steps:
providing a substrate, forming a plurality of protruding STI on the substrate, defining trench regions among the STI into a low-voltage device region and a medium-voltage device region respectively, growing a gate oxide layer in the trench regions, and then forming a first protective layer on the gate oxide layer; covering a first photoresist on the surface of the first protective layer, exposing the first protective layer of the gate oxide layer through photoetching, and simultaneously exposing partial STI on two sides of the gate oxide layer;
etching the exposed STI, wherein the etched width of the STI is a first width, and the depth of the STI is a first depth;
step three, removing the first photoresist and the first protective layer;
step four, growing a second protective layer;
covering the surface of the medium-voltage gate oxide region with a second photoresist through photoetching to expose part of the second protective layer, etching the exposed second protective layer, wherein the etched width of the second protective layer is a second width, the etched depth of the second protective layer is a second depth, and etching the substrate to form a polycrystalline silicon groove;
sixthly, growing a connecting layer at the polycrystalline silicon groove;
and seventhly, removing the second protective layer and the second photoresist through etching.
Optionally, the first width is 80 to 120 angstroms, and the first depth is 80 to 120 angstroms.
Optionally, the second protective layer is a silicon nitride layer with a thickness of 200 angstroms.
Optionally, in the second step, before etching, the first photoresist is hardened by using at least one of an Ash process and a baker process, and then is cleaned by a wet method.
Optionally, in the second step, the etching is formed by using at least one of a Certas process and an Etch process.
Optionally, in the fifth step, the second width is greater than the first width, and the second depth is etched to a position below the substrate.
Optionally, in the seventh step, after the second photoresist is removed by wet etching, the second protective layer is removed.
Optionally, the first protective layer and the second protective layer are made of silicon nitride.
Optionally, the ratio of the depth of the polysilicon trench to the thickness of the gate oxide layer in the medium-voltage gate oxide region is about 0.54: 1.
Optionally, the connection layer is generated by thermal oxidation of the polysilicon trench in a high-temperature furnace tube, the growth temperature is 800 to 900 ℃, and the growth thickness is 180 to 220 angstroms.
A MOS transistor, comprising:
a substrate;
the STI structure comprises a plurality of protruding STI positioned on the substrate, and trench regions among the STI are respectively defined as a low-voltage device region and a medium-voltage device region;
and the connecting layer is positioned in the groove region at the medium-voltage device region, wherein the edge thickness of the connecting layer is consistent with the whole thickness.
Alternatively, a MOS transistor can be manufactured by the manufacturing method of any one of the foregoing steps.
According to the invention, the STI of the IO boundary is added after the STI CMP to carry out the pre-etching process, so that the thickness of the STI oxide covered at the edge of the medium voltage gate oxide is reduced, silicon at the edge can be removed completely in the subsequent process, the cat ear defect is avoided, the problems that the thickness of the edge of the medium voltage gate oxide is thin and the medium voltage gate oxide is easy to break down after voltage is applied are avoided, and the reliability and the yield of a medium voltage device are improved.
Drawings
Fig. 1 is a schematic diagram illustrating a medium voltage gate oxide region defined by photolithography according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating the STI oxide covering the edges of the gate oxide during etching according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram illustrating the removal of the photoresist and the silicon nitride film according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating the growth of a hard mask silicon nitride film on a wafer by a high temperature furnace according to an embodiment of the present invention;
FIG. 5 is a schematic view of opening a silicon nitride film and etching a certain thickness according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating the growth of gate oxide in the medium-voltage gate oxide region by a high-temperature furnace oxidation method according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of the removal of a hard mask layer silicon nitride film according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a zero CMP process for a dielectric layer;
FIG. 9 is a schematic representation of a substrate before entering an IOX cycle;
FIG. 10 is a schematic view of an edge silicon bump;
FIG. 11 is a schematic diagram of medium voltage gate oxide growth to form a "cat ear" defect;
fig. 12 is a schematic flow diagram of a process modification.
The device comprises a substrate 1, a 2-STI, a 3-gate oxide layer, a 4-first photoresist, a 5-low-voltage device area, a 6-first protective layer, a 7-medium-voltage device area, an 8-connecting layer, a 9-second protective layer, a 10-second photoresist and a 11-polysilicon groove.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
The MOS transistor manufacturing method specifically comprises the following process steps:
step one, referring to fig. 1, providing a substrate 1, forming a plurality of protruding STIs 2 on the substrate 1, defining trench regions between the STIs 2 as a low-voltage device region 5 and a medium-voltage device region 7, respectively, growing a gate oxide layer 3 in the trench regions, and then forming a first protective layer 6 on the gate oxide layer 3, wherein the first protective layer 6 is flush with the top end surface of the STIs 2 after undergoing STI CMP; the first photoresist 4 is covered on the surface of the first protective layer 6 through a photoetching technology, and the first protective layer 6 in the area of the gate oxide layer 3 at the middle-voltage device area 7 is exposed through photoetching, and meanwhile, the STI2 on two sides of the area of the gate oxide layer 3 is partially exposed.
Step two, referring to fig. 2, the exposed STI2 is etched, the width of the etched STI2 is a first width, and the depth is a first depth; specifically, the STI2 is etched by at least one of the Certas process and the Etch process, the first width is greater than IO AA 80 angstroms and 120 angstroms, the width enables IO AA in IO device to be opened after etching, and here, if the areas of IO AA and IO STI2 are opened simultaneously, the cat ear defect shown in fig. 11 is formed after gate oxide is formed, the STI2 greater than IO AA is etched partially, so that formation of an STI2 covering layer above the edge of the circled position AA in fig. 9 can be avoided, if the covering layer is provided, polysilicon at the edge of AA protrudes due to blocking of the covering layer after etching, and the protruding polysilicon is difficult to be sufficiently oxidized in the oxidation process of the gate oxide 3, so that the cat ear defect shown in fig. 11 is formed. It should be understood that the value range here is the preferable scheme in this embodiment, and can be adjusted according to the actual requirement. The first depth is 80 angstroms to 120 angstroms, and then the first protective layer 6 and the first photoresist 4 are removed to obtain the structure shown in fig. 3, a dual-step structure is formed at the edge of the STI2 near the trench region, wherein the depth of the STI2 etching does not contact the gate oxide layer 3 at the trench region, the dual-step structure will be lost in subsequent operations such as washing, and the like, so as to form a single-step structure, the width of the formed new trench region is larger than the width of the original trench region, and after a second protective layer 9 is formed on the top surface of the substrate 1, the structure shown in fig. 4 is obtained;
further, the first protective layer 6 and the second protective layer 9 both use a silicon nitride material.
Removing the first photoresist 4 and the first protective layer 6 by wet etching;
step four, growing a second protective layer 9 with the thickness of 200 angstroms;
step five, referring to fig. 5, covering a second photoresist 10 on the surface of the medium voltage gate oxide region, exposing a part of the second protection layer 9 by photolithography, etching the exposed second protection layer 9, wherein the etched width of the second protection layer 9 is a second width, the second width is greater than the first width, a new double-step structure is formed after etching, the substrate 11 is also etched downwards to form a polysilicon trench 11, and the ratio of the thickness of the polysilicon trench 11 generated by etching to the thickness of the gate oxide layer 3 of the medium voltage device region 7 is about 0.54: 1;
step six, referring to fig. 6, a connecting layer 8 is grown and formed at the polysilicon trench 11, the connecting layer 8 is generated by thermal oxidation of the polysilicon trench 11 in a high-temperature furnace tube, the growth temperature is 800 ℃ to 900 ℃, and the growth thickness is 180 angstroms to 220 angstroms;
step seven, referring to fig. 7, the second protective layer 9 and the second photoresist 10 are removed by etching.
A MOS transistor, which can be manufactured by the manufacturing method described above, includes:
a substrate 1;
a plurality of raised STIs 2 on the substrate 1, trench regions between the STIs 2 being respectively defined as a low-voltage device region 5 and a medium-voltage device region 7;
and the connecting layer 8 is positioned in the groove region at the medium-voltage device region 7, and the edge thickness of the connecting layer is consistent with the whole thickness.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In conclusion, the STI pre-etching process for the IO boundary is added after the STI CMP, so that the thickness of the STI oxide covered at the edge of the medium voltage gate oxide is reduced, silicon at the edge can be removed completely in the subsequent process, the cat ear defect is avoided, the problems that the thickness of the edge of the medium voltage gate oxide is thin and the medium voltage gate oxide is easy to break down after voltage is applied are avoided, and the reliability and the yield of medium voltage devices are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. A manufacturing method of a MOS transistor is characterized by at least comprising the following steps:
providing a substrate, forming a plurality of protruding STI on the substrate, defining trench regions among the STI into a low-voltage device region and a medium-voltage device region respectively, growing a gate oxide layer in the trench regions, and then forming a first protective layer on the gate oxide layer; covering a first photoresist on the surface of the first protective layer, exposing the first protective layer of the gate oxide layer through photoetching, and simultaneously exposing partial STI on two sides of the gate oxide layer;
etching the exposed STI, wherein the etched width of the STI is a first width, and the depth of the STI is a first depth;
step three, removing the first photoresist and the first protective layer;
step four, growing a second protective layer;
covering a second photoresist on the surface of the medium-voltage gate oxide region, exposing a part of the second protective layer through photoetching, etching the exposed second protective layer, wherein the etched width of the second protective layer is a second width, and continuously etching the substrate to form a polysilicon groove;
sixthly, growing a connecting layer at the polycrystalline silicon groove;
and seventhly, removing the second protective layer and the second photoresist through etching.
2. The method of claim 2, wherein the method comprises: the first width is 80 to 120 angstroms and the first depth is 80 to 120 angstroms.
3. The method of claim 1, wherein the method comprises: the second protective layer is a silicon nitride layer with a thickness of 200 angstroms.
4. The method of claim 1, wherein the method comprises: in the second step, before etching, the first photoresist is hardened by adopting at least one of an Ash process and a Bake process, and then is cleaned by a wet method.
5. The method of claim 1, wherein the method comprises: in the second step, at least one of a Certas process and an Etch process is adopted for etching.
6. The method of claim 1, wherein the method comprises: in the fifth step, the second width is larger than the first width and smaller than the width of the STI.
7. The method of claim 1, wherein the method comprises: and seventhly, removing the second photoresist by wet etching, and then removing the second protective layer.
8. The method of claim 1, wherein the method comprises: the first protective layer and the second protective layer are made of silicon nitride.
9. The method of claim 1, wherein the method comprises: the ratio of the depth of the polysilicon groove to the thickness of the gate oxide layer is about 0.54: 1.
10. The method of claim 1, wherein the method comprises: the connecting layer is generated by thermal oxidation of the polycrystalline silicon groove in a high-temperature furnace tube, the growth temperature is 800-900 ℃, and the growth thickness is 180-220 angstroms.
11. A MOS transistor, comprising:
a substrate;
the STI structure comprises a plurality of protruding STI positioned on the substrate, and trench regions among the STI are respectively defined as a low-voltage device region and a medium-voltage device region;
and the connecting layer is positioned in the groove region at the medium-voltage device region.
12. The MOS transistor of claim 11, wherein: the edge thickness of the connecting layer is consistent with the whole thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111244747.8A CN114038744A (en) | 2021-10-26 | 2021-10-26 | MOS transistor manufacturing method and MOS transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111244747.8A CN114038744A (en) | 2021-10-26 | 2021-10-26 | MOS transistor manufacturing method and MOS transistor |
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| CN114038744A true CN114038744A (en) | 2022-02-11 |
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| CN202111244747.8A Pending CN114038744A (en) | 2021-10-26 | 2021-10-26 | MOS transistor manufacturing method and MOS transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360193A (en) * | 2022-10-21 | 2022-11-18 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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2021
- 2021-10-26 CN CN202111244747.8A patent/CN114038744A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360193A (en) * | 2022-10-21 | 2022-11-18 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115360193B (en) * | 2022-10-21 | 2023-01-31 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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