TW202029463A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

Description

Semiconductor memory element and manufacturing method thereof

The present invention relates to an integrated circuit and its manufacturing method, and more particularly to a semiconductor memory element and its manufacturing method.

With the rapid development of science and technology, in order to achieve the requirements of reducing costs and simplifying the process steps of semiconductor devices, it has gradually become a trend to integrate the components of the cell array region and the peripheral region on the same chip.

In the conventional manufacturing process, different gate structures in the cell array region and the peripheral region need to be defined using different masks. However, the isolation structure between the unit cell array area and the peripheral area will undergo multiple etching processes, resulting in excessive loss of the isolation structure. In this case, the conductor layer on the isolation structure near the peripheral area of the boundary area will also be lost, causing the generation of poly residue defects, thereby reducing the reliability and yield of the device. Therefore, how to provide a semiconductor memory device and a manufacturing method thereof to reduce polysilicon residue defects and thereby improve the reliability and yield of the semiconductor memory device will become an important issue.

The present invention provides a semiconductor memory element and a manufacturing method thereof, which can avoid the generation of polysilicon residue defects, thereby improving the reliability and yield of the semiconductor memory element.

The invention provides a semiconductor memory element, which includes a substrate, an isolation structure, a first gate dielectric layer, a first conductor layer, a second gate dielectric layer, a second conductor layer and a protective layer. The substrate has an array area and a peripheral area. The isolation structure is arranged in the substrate between the array area and the peripheral area. The first gate dielectric layer is disposed on the substrate in the array area. The first conductor layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the peripheral area. The second conductor layer is disposed on the second gate dielectric layer. The second conductor layer extends to cover part of the top surface of the isolation structure. The protective layer is disposed between the second conductor layer and the isolation structure.

The present invention provides a method for manufacturing a semiconductor memory element, the steps of which are as follows. Provide a substrate with an array area and a peripheral area. A first stack structure is formed on the substrate in the array area. A second stacked structure is formed on the substrate in the peripheral area. An isolation structure is formed in the substrate between the first stack structure and the second stack structure. A protective layer is comprehensively formed on the substrate. A first mask layer is formed on the protective layer, wherein the first mask layer extends from the array area to cover a part of the peripheral area. Taking the first mask layer as an etching mask, part of the protection layer and the second stack structure are removed. A gate dielectric layer is formed on the substrate in the peripheral area. The conductor material is formed comprehensively on the substrate. A second mask layer is formed on the conductor material in the peripheral area. The second mask layer is used as an etching mask, and part of the conductive material and the protective layer underneath are removed, so that the remaining protective layer is formed in the overlapping area of the first mask layer and the second mask layer.

Based on the above, the present invention partially overlaps the first mask layer and the second mask layer to form a protective layer between the second conductor layer and the isolation structure. The protective layer can prevent the underlying isolation structure from being excessively worn during the etching process, so as to reduce the generation of polysilicon residue defects, thereby improving the reliability and yield of the semiconductor memory device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The semiconductor memory devices in the following paragraphs are based on flash memory (Flash) as an example. However, the present invention is not limited to this.

1A, this embodiment provides a method for manufacturing a semiconductor memory device, the steps of which are as follows. First, a substrate 100 is provided. The substrate 100 may be, for example, a silicon substrate. Specifically, the substrate 100 includes an array area R1, a peripheral area R2, and a boundary area R3 between the array area R1 and the peripheral area R2. In one embodiment, the array region R1 may have a plurality of memory cells therein; the peripheral region R2 may have a plurality of logic circuits (for example, transistors) therein. In other embodiments, the peripheral area R2 may also have memory therein.

Next, a first stack structure 110 is formed on the substrate 100 in the array region R1 and a second stack structure 120a is formed on the substrate 100 in the peripheral region R2. The first stacked structure 110 includes a first gate dielectric layer 112 and a first conductive layer 114. The second stacked structure 120a includes a second gate dielectric layer 122a and a second conductive layer 124a.

In this embodiment, the first gate dielectric layer 112 may be, for example, a tunneling dielectric layer. The material of the first gate dielectric layer 112 includes silicon oxide, silicon oxynitride, silicon nitride or other suitable dielectric materials. Its formation method includes chemical vapor deposition or furnace tube oxidation, and its thickness can be 2 nm to 20 nm. In this embodiment, the first conductive layer 114 may be, for example, a floating gate. The material of the first conductive layer 114 includes doped polysilicon, undoped polysilicon, or a combination thereof. The formation method thereof may be a chemical vapor deposition method, and the thickness thereof may be 10 nm to 150 nm.

In one embodiment, the second gate dielectric layer 122a can be formed at the same time as the first gate dielectric layer 112, and the second conductive layer 124a can be formed at the same time as the first conductive layer 114, but the invention is not limited thereto. In an alternative embodiment, the material of the second gate dielectric layer 122a is the same as or different from the material of the first gate dielectric layer 112. The material of the second conductor layer 124a is also the same as or different from the material of the first conductor layer 114.

Then, a plurality of isolation structures 101 are formed in the substrate 100. Specifically, the isolation structure 101 extends from the top surface of the first stack structure 110 and the second stack structure 120 a in the direction of the substrate 100. As shown in FIG. 1A, the isolation structure 101 may be located in the substrate 100 in the boundary region R3 between the array region R1 and the peripheral region R2 to separate the first stack structure 110 and the second stack structure 120a. In addition, the isolation structure 101 may be located in the substrate 100 of the array region R1 to separate two adjacent first stack structures 110. In addition, the isolation structure 101 may be located in the substrate 100 in the peripheral region R2 to separate two adjacent second stacked structures 120a. In an embodiment, the isolation structure 101 includes an isolation material, which may be, for example, a high-density plasma oxide layer or spin-on glass (SOG). In an alternative embodiment, the isolation structure 101 may be a shallow trench isolation (STI) structure.

As shown in FIG. 1A, after the isolation structure 101 is formed, a buffer layer 103 is formed on the substrate 100 comprehensively, and a protective layer 102 is formed on the buffer layer 103 comprehensively. In one embodiment, the buffer layer 103 includes an oxide layer, such as silicon oxide, and its formation method includes a chemical vapor deposition method or a furnace tube oxidation method, and the thickness thereof may be 5 nm to 100 nm. The protective layer 102 includes a nitride layer, such as silicon nitride, silicon oxynitride, or a combination thereof. The formation method thereof includes a chemical vapor deposition method, and the thickness thereof may be 5 nm to 100 nm.

1A and 1B, a first mask layer 104 is formed on the protective layer 102. Specifically, as shown in FIG. 1B, the first mask layer 104 traverses the boundary region R3 from the array region R1 and extends to cover a part of the peripheral region R2. The first mask layer 104 is, for example, a photoresist material.

Next, using the first mask layer 104 as an etching mask, a first etching process is performed to remove part of the protective layer 102, part of the buffer layer 103, the second conductive layer 124a, and part of the isolation structure 101. During the first etching process, the second gate dielectric layer 122a can be used as an etch stop layer to prevent damage to the substrate 100. In one embodiment, the first etching process includes a dry etching process, such as a reactive ion etching (RIE) process. After the first etching process is performed, as shown in FIG. 1B, the second gate dielectric layer 122a is further removed to expose the substrate 100 in the peripheral region R2.

1B and 1C, after removing the first mask layer 104, a second gate dielectric layer 122 is formed on the substrate 100 in the peripheral region R2. In one embodiment, the material of the second gate dielectric layer 122 includes silicon oxide, silicon oxynitride, silicon nitride or other suitable dielectric materials, and its formation method includes chemical vapor deposition or furnace tube oxidation. And its thickness can be 2 nm to 50 nm. In addition, since the operating voltages of the semiconductor devices in the array region R1 and the peripheral region R2 are different, the thickness of the second gate dielectric layer 122 may be greater than the thickness of the first gate dielectric layer 112.

Next, a conductive material 124' is formed on the substrate 100 in an all-round way. As shown in FIG. 1C, the conductive material 124' covers the protective layer 102a, the buffer layer 103a, the isolation structure 101 and the second gate dielectric layer 122. In one embodiment, the conductive material 124' includes doped polysilicon, undoped polysilicon, or a combination thereof. The formation method may be a chemical vapor deposition method, and the thickness may be 50 nm to 300 nm. After that, a second mask layer 106 is formed on the conductive material 124' of the peripheral region R2. In an embodiment, the second mask layer 106 may be a photoresist material.

1C and 1D, using the second mask layer 106 as an etching mask, a second etching process is performed to remove part of the conductive material 124', thereby forming the second conductive layer 124. During the second etching process, the protective layer 102a can be used as an etching stop layer. In this case, as shown in FIG. 1D, the protective layer 102a is exposed to the second conductor layer 124. In one embodiment, the second etching process includes a dry etching process, such as RIE.

1D and 1E, after removing the second mask layer 106, using the second conductive layer 124 as an etching mask, a wet etching process is performed to remove part of the protective layer 102a and the buffer layer 103a below it , Part of the isolation structure 101 to expose the first stack structure 101. In this case, as shown in FIG. 1E, the first stack structure 110 protrudes from the top surface 101 t of the isolation structure 101 to form a recess 115 between the first stack structure 101. The recess 115 exposes part of the sidewalls of the first conductor layer 114, which can increase the contact area between the first conductor layer 114 and the third conductor layer 134 (as shown in FIG. 1F) formed subsequently, thereby increasing the gate coupling rate ( Gate-Coupling Ratio, GCR). In one embodiment, the wet etching process may include multiple etching steps. For example, a first etching step can be performed to remove the protective layer 102a made of nitride, and then a second etching step can be performed to remove the buffer layer 103a made of oxide and the isolation below it. Structure 101. In an alternative embodiment, the first etching step may use an etching solution containing phosphoric acid to remove nitrides; and the second etching step may use buffered hydrofluoric acid (BHF) to remove oxides, but the present invention does not Limit this.

It is worth noting that the first mask layer 104 (as shown in FIG. 1B) and the second mask layer 106 (as shown in FIG. 1C) partially overlap in the overlapping area OP (as shown in FIG. 1D). In an embodiment, the overlapping area OP may be between 0.3 micrometers (μm) and 1.0 micrometers. After the above-mentioned wet etching process, the protective layer 102b is formed in the overlapping area OP of the first mask layer 104 and the second mask layer 106, as shown in FIG. 1E. In addition, from the vertical direction, the protective layer 102b is formed between the second conductor layer 124 and the isolation structure 101 (or the buffer layer 103b). That is, the second conductive layer 124 is disposed on the second gate dielectric layer 122 and extends to cover the protective layer 102b on the isolation structure 101. The protective layer 102b can prevent the isolation structure 101 underneath from being excessively lost during the wet etching process, so as to further protect the bottom surface of the second conductive layer 124 above it, thereby reducing the occurrence of polysilicon residue defects. In some embodiments, the unetched isolation structure under the protective layer 102b can be regarded as another protective layer 101b. Hereinafter, the isolation structure above the top surface 101t of the isolation structure 101 is referred to as a protective layer 101b, and the rest are referred to as isolation structures 101a. As shown in FIG. 1E, the protective layer 101b, the protective layer 102b, and the buffer layer 103b between the two can constitute the protective structure 105. The protection structure 105 can protect the bottom surface of the second conductive layer 124 above it, thereby reducing the occurrence of polysilicon residue defects. In other words, the protection structure 105 of this embodiment can effectively improve the reliability and yield of the semiconductor memory device.

In addition, since the first mask layer 104 (as shown in FIG. 1B) crosses the border region R3 from the array region R1 and extends to cover a part of the peripheral region of R2, the isolation structure 101 of the border region R3 is basically protected by the protective layer 102a. Stay protected. In other words, the isolation structure 101 in the boundary region R3 has only undergone the second etching process, but not the first etching process. Therefore, the isolation structure 101 of the boundary region R3 will not be over-etched. In this case, as shown in FIG. 1E, the top surface 101t of the isolation structure 101 in the boundary region R3 is substantially flat, so as to facilitate the deposition of the subsequently formed layer. In addition, the top surface 101t of the isolation structure 101 in the boundary region R3 is higher than the top surface 100t of the substrate 100 in the peripheral region R2 (or the formation surface of the second gate dielectric layer 122), and is higher than the top surface of the substrate 100 in the array region R1. The surface 100t' (or the formation surface of the first gate dielectric layer 112).

1E and 1F, a dielectric layer 132 and a third conductive layer 134 are sequentially formed on the substrate 100. The dielectric layer 132 conformally covers the first stacked structure 110, the isolation structure 101 and the second stacked structure 120. In one embodiment, the dielectric layer 132 may be, for example, a composite layer structure composed of silicon oxide/silicon nitride/silicon oxide, but the invention is not limited thereto. In an embodiment, the material of the third conductive layer 134 includes doped polysilicon, undoped polysilicon, or a combination thereof. The third conductor layer 134 may be a control gate; and the dielectric layer 132 may be an interlayer dielectric between the first conductor layer 114 (that is, the floating gate) and the third conductor layer 134 (that is, the control gate) Floor.

In one embodiment, the formation of the third conductive layer 134 includes: comprehensively forming a third conductive material; sequentially forming a carbon material, a nitride material, and a photoresist pattern 140 on the third conductive material; and using the photoresist pattern 140 To etch the mask, part of the carbon material and part of the nitride material are removed to form a hard mask layer HM composed of the carbon layer 136 and the nitride layer 138; taking the hard mask layer HM as the etching mask, remove part The third conductive material to expose the dielectric layer 132. In this case, as shown in FIG. 1F, the third conductor layer 134 covers the array region R1 and part of the boundary region R3, but does not cover the peripheral region R2.

In summary, the present invention partially overlaps the first mask layer and the second mask layer to form a protective layer between the second conductor layer and the isolation structure. The protective layer can prevent the underlying isolation structure from being excessively worn during the etching process, so as to reduce the generation of polysilicon residue defects, thereby improving the reliability and yield of the semiconductor memory device. In addition, the top surface of the isolation structure in the boundary region is substantially flat, which can facilitate the deposition of subsequent layers, thereby increasing the process margin and yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: base 100t, 100t’: the top surface of the base 101, 101a: isolation structure 101t: the top surface of the isolation structure 101b, 102, 102a, 102b: protective layer 103, 103a, 103b: buffer layer 104: The first mask layer 105: Protective structure 106: The second mask layer 110: The first stack structure 112: First gate dielectric layer 114: first conductor layer 115: sunken 120, 120a: second stack structure 122, 122a: second gate dielectric layer 124, 124a: second conductor layer 124’: Conductor material 132: Dielectric layer 134: third conductor layer 136: Carbon layer 138: Nitride layer 140: photoresist pattern HM: Hard mask layer OP: overlapping area R1: Array area R2: Surrounding area R3: Border zone

1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor memory device according to an embodiment of the invention.

100: base

101, 101a: isolation structure

101b, 102b: protective layer

103b: buffer layer

105: Protective structure

110: The first stack structure

112: First gate dielectric layer

114: first conductor layer

120: second stack structure

122: second gate dielectric layer

124: second conductor layer

132: Dielectric layer

134: third conductor layer

136: Carbon layer

138: Nitride layer

140: photoresist pattern

HM: Hard mask layer

R1: Array area

R2: Surrounding area

R3: Border zone

Claims (10)

A semiconductor memory element, including: The substrate has an array area and a peripheral area; An isolation structure, disposed in the substrate between the array area and the peripheral area; A gate dielectric layer disposed on the substrate in the peripheral area; A conductor layer disposed on the gate dielectric layer, wherein the conductor layer extends to cover part of the top surface of the isolation structure; and The protection structure is arranged between the conductor layer and the isolation structure. The semiconductor memory device according to the first item of the patent application, wherein the protective structure includes a composite layer structure having different dielectric materials. The semiconductor memory element according to claim 1, wherein the top surface of the isolation structure is higher than the top surface of the substrate in the peripheral region. The semiconductor memory element according to claim 1, wherein the substrate further includes a boundary area arranged between the array area and the peripheral area, and the isolation structure located in the boundary area The top surface is substantially flat. The semiconductor memory device described in item 1 of the scope of patent application further includes: A tunneling dielectric layer is disposed on the substrate in the array area; and The floating gate is arranged on the tunneling dielectric layer, wherein the thickness of the tunneling dielectric layer is smaller than the thickness of the gate dielectric layer. A method for manufacturing a semiconductor memory element includes: Provide a substrate, which has an array area and a peripheral area; Forming an isolation structure in the substrate between the array area and the peripheral area; Comprehensively forming a protective layer on the substrate; Forming a first mask layer on the protective layer, wherein the first mask layer extends from the array area to cover a part of the peripheral area; Using the first mask layer as an etching mask, and removing the first part of the protective layer; Forming a second mask layer on the peripheral area; and Using the second mask layer as an etching mask, remove the second part of the protection layer so that the remaining protection layer is formed on the overlap of the first mask layer and the second mask layer Area. As described in item 6 of the scope of patent application, the method for manufacturing a semiconductor memory element, before the protective layer is comprehensively formed on the substrate, further includes: Forming a first stack structure on the substrate in the array area; and Forming a second stack structure on the substrate in the peripheral region, The step of removing the first part of the protective layer by using the first mask layer as an etching mask includes removing the second stack structure to expose the substrate in the peripheral region. As described in item 7 of the scope of patent application, the method for manufacturing a semiconductor memory device, after removing the second stack structure, further includes: Forming a gate dielectric layer on the substrate in the peripheral region; and Forming a conductive material on the substrate in an all-round way, The second mask layer is used as an etching mask, and the step of removing the second part of the protective layer includes removing part of the conductive material to form a conductive layer, which is dielectric from the gate The top surface of the layer extends to cover part of the top surface of the isolation structure, so that the remaining protective layer is disposed between the conductor layer and the isolation structure. According to the method for manufacturing a semiconductor memory device as described in item 8 of the scope of patent application, after the second mask layer is used as an etching mask, part of the conductive material and the protective layer underneath are removed, It further includes: removing part of the isolation structure to expose the first stack structure, wherein the remaining protective layer and the unetched isolation structure underneath form a protective structure to protect the bottom surface of the conductor layer. According to the method for manufacturing a semiconductor memory element according to the scope of patent application, after removing part of the isolation structure to expose the first stack structure, the top surface of the isolation structure is higher than the The top surface of the base in the peripheral zone.

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