TWI690059B - Semiconductor strucutre and method of fabricating the same - Google Patents

Abstract

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Description

Semiconductor structure and its manufacturing method

The embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof.

Non-Volatile Memory (NVM) cell array manufacturing has been integrated into advanced complementary metal oxide semiconductor (CMOS) manufacturing processes for smart card and automotive applications. The gate height of the embedded NVM cell array is usually higher than the gate height of peripheral circuits (such as logic elements). During the continuous chemical mechanical polishing (CMP) process, the gate height difference between the embedded NVM cell array and the logic device can cause a fishing issue.

According to some embodiments of the present disclosure, a semiconductor structure is provided, which includes a semiconductor substrate and at least one patterned dielectric layer. The semiconductor substrate includes a semiconductor portion, at least one first element, at least one second element, and at least one first dummy ring. At least one first element is disposed in the first region surrounded by the semiconductor portion. At least one second element and at least one first dummy ring are disposed on the second area, and the second area surrounds the first area. At least one patterned dielectric layer covers the semiconductor substrate.

According to some embodiments of the present disclosure, a semiconductor structure is provided, which includes a semiconductor substrate and at least one patterned dielectric layer. The semiconductor substrate includes an active region and a peripheral region surrounding the active region, at least one first component disposed on the active region, at least one second component disposed on the peripheral region, and at least one first dummy ring disposed on the peripheral region. At least one first element and at least one second element are spaced apart by the semiconductor portion of the active region. At least one patterned dielectric layer is disposed on the semiconductor substrate. At least one first element, at least one second element, and at least one first dummy ring are embedded in the patterned dielectric layer.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, which includes the following steps. A semiconductor substrate having a semiconductor portion is provided. At least one first element is formed on the first region surrounded by the semiconductor portion. At least one second element and at least one first dummy ring are formed on the second area, wherein the second area surrounds the first area, and at least one first dummy ring surrounds at least one first element. At least one dielectric layer is formed on the semiconductor substrate to cover at least one first element, at least one second element, and at least one first dummy ring. Grind at least one dielectric layer until at least one first element, at least one second element, and at least one first dummy ring are exposed.

100: semiconductor substrate

100A: District 1

100B: District 2

100B1: dummy area

100B2: Peripheral circuit area

102, 102b: cushion

102a: Wet oxide layer

104, 106a, 132a, 132c, 132d: patterned hard mask curtain layer

106, 132: hard cover curtain layer

110a: First trench isolation

110b: Second trench isolation

112: Semiconductor part

120: hard cover curtain top cover layer

120a: Patterned hard cover curtain top layer

122: oxide cap layer

122a: Patterned oxide cap layer

124, 124a, 130, 142: conductive layer

124b, 142a: conductive pattern

124c: floating gate electrode

126, 128, 136c, 150: dielectric layer

126a, 128b, 150a1, 150a2, 150b1, 150b2: dielectric pattern

128a, 128c: patterned dielectric layer

130a, 130c: patterned conductive layer

130b: control gate electrode

132b: Hard cover curtain pattern

134a, 134b, 136a, 136b, 144, 144a, 172, 176, 178: spacer

136d: oxide layer

138, 146, 168, PR: patterned photoresist layer

140, 170, 174: doped regions

142b: Select gate electrode

148: Patterned dummy layer

148a, 148a1, 148b: dummy layer

150a: part one

150b: Part Two

152: Gate electrode

154: Dielectric top cover

156, 158, 160, 162, 164, 166: dummy patterns

180: stop layer

180a: patterned stop layer

182: Interlayer dielectric layer

182a: Grinded interlayer dielectric layer

200, 200a: Integrated circuit components

B: border area

B1: Border

B2: Outer boundary

D: distance

DP: Dummy dot pattern

DR1: the first dummy ring

DR2: second dummy ring

H1: first height

H2: second height

IS1, IS2, IS3: inclined surface

M: memory cell array

MG: metal gate electrode

P: Peripheral circuit

R1, R2: groove

TH1: first thickness

TH2: second thickness

X: part

S1, S2: surface

Reading the following detailed description in conjunction with the accompanying drawings will best understand the various aspects of the present disclosure. It is worth noting that, according to industry standard practices, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily.

1 to 32 are diagrams schematically showing semiconductors according to some embodiments of the present disclosure Cross-sectional view of a method of manufacturing a structure.

33 is a top view schematically showing a wafer including a plurality of integrated circuit members arranged in an array according to some embodiments of the present disclosure.

FIG. 34 is an enlarged top view schematically showing part X shown in FIG. 33 according to some embodiments of the present disclosure.

FIG. 35 is an enlarged top view schematically showing part X shown in FIG. 33 according to some alternative embodiments of the present disclosure.

36A and 36B are cross-sectional views schematically showing a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

37A to 37C are cross-sectional views schematically showing a method of manufacturing a semiconductor structure according to some alternative embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and configurations to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, forming the first feature "on" or "on" the second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include An embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not directly contact each other. In addition, the disclosure content may reuse reference numbers and/or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of explanation, for example, "beneath", "below", "lower", "on" may be used in this article )", "above", "upper" and other spatially relative terms to illustrate the relationship between one element or feature and another (other) element or feature shown in the figure. The term spatial relativity is intended to include different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may have other orientations (rotation 90 degrees or other orientations), and the terms of spatial relativity used herein may be interpreted accordingly accordingly.

1 to 32 are cross-sectional views schematically showing a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

Referring to FIG. 1, a semiconductor substrate 100 is provided. For example, the semiconductor substrate 100 may be a silicon substrate or a substrate made of other semiconductor materials. In some embodiments, as shown in FIG. 33, the semiconductor substrate 100 may be a semiconductor wafer (for example, a silicon wafer or the like). A pad layer 102 is formed on the semiconductor substrate 100, and a patterned hard mask layer 104 is formed on the pad layer 102. For example, the pad layer 102 may be a silicon oxide (SiO _x , x>0) layer, and the patterned hard mask layer 104 may be a silicon nitride (SiN _y , y>0) layer. The material of the cushion layer 102 and the material of the patterned hard mask layer 104 are for illustration only, and the disclosure is not limited thereto. As shown in FIG. 1, the patterned hard mask layer 104 can be formed by a lithography and etching process, for example, and a portion of the pad layer 102 is exposed by the patterned hard mask layer 104. In the etching process of the patterned hard mask layer 104, the pad layer 102 can be used as an etch stop layer.

Referring to FIGS. 1 and 2, a wet oxidation process is performed so that a portion of the semiconductor substrate 100 covered by the pad layer 102 is oxidized, and a wet oxide layer 102 a is formed on the semiconductor substrate 100. After the wet oxidation process, A groove R1 of the semiconductor substrate 100 is formed, and a wet oxide layer 102a is formed on the groove R1. As shown in FIGS. 1 and 2, the wet oxide layer 102 a is not covered by the patterned hard mask layer 104, and the wet oxide layer 102 a is thicker than the cushion layer 102 covered by the patterned hard mask layer 104. For example, the thickness of the wet oxide layer 102a ranges from about 100 angstroms to about 2000 angstroms, and the depth of the groove R1 of the semiconductor substrate 100 is about half the thickness of the wet oxide layer 102a (eg, about 50 angstroms to about 1000 Angstroms). In some embodiments, the thickness of the wet oxide layer 102a may be about 600 angstroms, and the depth of the groove R1 of the semiconductor substrate 100 may be about half the thickness of the wet oxide layer 102a (eg, about 300 angstroms). The thickness of the wet oxide layer 102a and the depth of the groove R1 are for illustration only, and the disclosure is not limited thereto.

2 and 3, the wet oxide layer 102a is partially removed by an etching process to form another pad layer 102b in the groove R1. The pad layer 102b in the groove R1 is connected to the pad layer 102 covered by the patterned hard mask layer 104. In some embodiments, the thickness of the cushion layer 102b and the cushion layer 102 may be substantially the same (eg, about 10 angstroms to about 500 angstroms). During the etching process for forming the pad layer 102b, the patterned hard mask layer 104 may be slightly etched, and the thickness loss of the patterned hard mask layer 104 may be, for example, about 80 angstroms. The above thickness loss and the thickness of the pad layer 102b and the pad layer 102 are for illustration only, and the disclosure is not limited thereto.

As shown in FIGS. 2 and 3, the semiconductor substrate 100 may provide two surfaces S1 and S2, wherein the surfaces S1 and S2 are located at different horizontal heights, and the horizontal difference between the surfaces S1 and S2 is, for example, about 50 Angstrom to about 1000 Angstroms. The above-mentioned level difference between the surface S1 and the surface S2 is for illustration only, and the disclosure is not limited thereto.

Referring to FIG. 4, the patterned hard mask layer 104 is removed, and a hard mask layer 106 is formed on the pad layer 102 on the surface S1 of the semiconductor substrate 100 and the pad layer 102 b on the surface S2 of the semiconductor substrate 100. For example, the hard mask layer 106 may be a silicon nitride layer. The material of the hard mask layer 106 is for illustration only, and the disclosure is not limited thereto.

Referring to FIG. 5, a trench isolation manufacturing process may be performed on the semiconductor substrate 100 so that at least one first trench isolation 110 a (eg, at least one inner trench isolation) and at least one second trench isolation 110 b (eg, at least one) are formed in the semiconductor substrate 100 An outer trench is isolated). After forming at least one first trench isolation 110a and at least one second trench isolation 110b, the semiconductor portion 112 of the semiconductor substrate 100, the first region 100A, and the second region 100B are defined. In some embodiments, the first area 100A may be an active area surrounded by at least one first trench isolation 110a, and the second area 100B may be a peripheral area. For example, as shown in FIGS. 34 and 35, the first area 100A is connected to the second area 100B, the second area 100B is a ring-shaped peripheral area, and the first area 100A is surrounded by the ring-shaped second area 100B.

In some embodiments, the above trench isolation manufacturing process may include: patterning the hard mask layer 106 to form a patterned hard mask layer 106a; for example, forming a plurality of trenches in the semiconductor substrate 100 by an etching process; The electrical material fills the trench and covers the patterned hard mask layer 106a; and the dielectric material outside the trench is polished (eg, CMP process) until the patterned hard mask layer 106a is exposed, as shown in FIG. 5 . In some embodiments, the first trench isolation 110a and the second trench isolation 110b are, for example, shallow trench isolation (STI) structures. However, in this application, the manufacturing process of at least one first trench isolation 110a and at least one second trench isolation 110b is not limited.

As shown in FIG. 5, the semiconductor portion 112 of the semiconductor substrate 100 may be a ring structure, which is in contact with the first trench isolation 110 a and the second trench isolation 110 b. The first trench isolation 110a and the second trench isolation 110b may be located on opposite sides of the semiconductor portion 112. The semiconductor portion 112 and the first trench isolation 110a may be located in the boundary region B of the first region 100A. In other words, the boundary region B is the region where the semiconductor portion 112 and the first trench isolation 110a are located. For example, the semiconductor portion 112 is close to the interface between the first area 100A and the second area 100B, and the second trench isolation 110b is close to the interface between the first area 100A and the second area 100B (dashed line shown in FIG. 5 ). In addition, the top surface of the first trench isolation 110a, the top surface of the second trench isolation 110b, and the top surface of the patterned hard mask layer 106a are substantially at the same level.

6, a top cover layer is formed on the top surface of the first trench isolation 110a, the top surface of the second trench isolation 110b, and the top surface of the patterned hard mask layer 106a. In some embodiments, the cap layer may include a hard mask top layer 120 and an oxide cap layer 122 formed on the hard mask top layer 120. The hard mask top cover layer 120 is formed on the top surface of the first trench isolation 110a, the top surface of the second trench isolation 110b, and the top surface of the patterned hard mask layer 106a. In some embodiments, the material of the oxide cap layer 122 may be different from the material of the patterned hard mask layer 106a, and the material of the oxide cap layer 122 may be the same as the material of the pad layer 102. For example, the material of the hard mask cap layer 120 may include silicon nitride, and the material of the oxide cap layer 122 may include silicon oxide. The materials of the hard mask top cover layer 120 and the oxide top cover layer 122 are for illustration only, and the disclosure is not limited thereto.

Referring to FIG. 7, for example, the hard mask curtain cap layer 120 and the oxide cap layer 122 are patterned by a lithography and etching process to form a patterned hard mask curtain cap layer 120a and a patterned oxide cap The patterned cap layer of the cap layer 122a. Patterned The hard mask curtain cap layer 120a and the patterned oxide cap layer 122a cover the second trench isolation 110b, the patterned hard mask layer 106a between the first trench isolation 110a and the second trench isolation 110b, and the proximity semiconductor Part 112 of the first trench isolation 110a.

By using the patterned hard mask top cap layer 120a and the patterned oxide cap layer 122a as the mask, for example, by etching process to remove part of the patterned hard mask layer 106a on the pad layer 102b, Until the pad 102b is exposed. In some embodiments, during the etching process for partially removing the patterned hard mask curtain layer 106a, the material of the patterned oxide cap layer 122a (eg, silicon oxide) is different from the patterned hard mask The material of the curtain layer 106a and the material of the patterned hard mask curtain cap layer 120a (for example, silicon nitride), so the patterned hard mask curtain layer 106a can be selectively etched. In addition, during the etching process for partially removing the patterned hard mask layer 106a, since the material of the patterned oxide cap layer 122a (eg, silicon oxide) is the same as the material of the pad layer 102b, the pad layer 102b can be used as an etch stop layer. The materials of the pad layer 102b, the material of the patterned hard mask layer 106a, the material of the patterned hard mask layer 120a, and the material of the patterned oxide cap layer 122a are for illustration only, and this disclosure Not limited to this.

7 and 8, the pad layer 102 b is removed, and the dielectric layer 126 is formed on the surface S2 of the semiconductor substrate 100. In some embodiments, the dielectric layer 126 may be a silicon oxide layer. Next, a conductive layer 124 is formed on the patterned oxide cap layer 122a, the first trench isolation 110a, and the dielectric layer 126. In some embodiments, the conductive layer 124 may be a doped polysilicon layer. For example, the conductive layer 124 may be formed by depositing a polysilicon layer, implanting dopants into the polysilicon layer, and annealing the doped polysilicon layer. The material of the conductive layer 124 and the material of the dielectric layer 126 are for illustration only, and the disclosure is not limited thereto.

Referring to FIGS. 8 and 9, a polishing process (for example, a CMP process) is performed on the conductive layer 124 to form a conductive layer 124a having a planarized top surface. The conductive layer 124a covers the dielectric layer 126 and the first trench isolation 110a. During the polishing process of the conductive layer 124, the patterned oxide cap layer 122a is polished until the patterned hard mask cap layer 120a is exposed. The patterned hard mask curtain cap layer 120a can be used as a grinding stop layer during the grinding process of the conductive layer 124. As shown in FIG. 9, the top surface of the patterned hard mask top cover layer 120a and the top surface of the conductive layer 124a are substantially at the same level.

Referring to FIGS. 9 and 10, for example, the conductive layer 124 a is further patterned by an etching process, so that at least one conductive pattern 124 b is formed on the dielectric layer 126. In the etching process of the conductive layer 124a, a portion of the first trench isolation 110a that is not covered by the patterned hard mask curtain cap layer 120a may be partially removed. As shown in FIG. 10, for example, a groove R2 is formed in the first trench isolation 110a, and the groove R2 is close to the conductive pattern 124b.

10 and 11, a dielectric layer 128, a conductive layer 130, and a hard mask layer 132 are formed in order to cover the conductive pattern 124b, the first trench isolation 110a, and the patterned hard mask curtain cap layer 120a. The dielectric layer 128 covers the conductive pattern 124b, the first trench isolation 110a, and the patterned hard mask curtain cap layer 120a. The conductive layer 130 covers the dielectric layer 128. The hard mask layer 132 covers the conductive layer 130. In some embodiments, the dielectric layer 128 may be a silicon oxide layer. The conductive layer 130 may be a doped polysilicon layer. For example, the conductive layer 130 may be formed by depositing a polysilicon layer, implanting dopants into the polysilicon layer, and annealing the doped polysilicon layer. The hard mask curtain layer 132 may be a stacked layer of silicon oxide/silicon nitride/silicon oxide. However, the configuration of the hard mask curtain layer 132 is not limited. Above The material of the dielectric layer 128, the material of the conductive layer 130, and the material of the hard mask layer 132 are for illustration only, and the disclosure is not limited thereto.

Referring to FIGS. 11 and 12, for example, the dielectric layer 128, the conductive layer 130 and the hard mask layer 132 are patterned by a lithography and etching process, so that a patterned dielectric layer 128a, a dielectric pattern 128b, and a pattern are formed Conductive layer 130a, control gate electrode 130b, patterned hard mask layer 132a and hard mask pattern 132b. The patterned dielectric layer 128a, the patterned conductive layer 130a, and the patterned hard mask layer 132a are formed to cover the first trench isolation 110a and the patterned hard mask curtain cap layer 120a. The dielectric pattern 128b, the control gate electrode 130b, and the hard mask pattern 132b are formed to partially cover the conductive pattern 124b. During the patterning process of the dielectric layer 128, the conductive layer 130, and the hard mask layer 132, the conductive pattern 124b may be slightly over-etched.

12 and 13, a partition wall 134a and a partition wall 134b are formed. The spacer 134a is formed on the sidewall of the patterned dielectric layer 128a, the sidewall of the patterned conductive layer 130a, and the sidewall of the patterned hard mask layer 132a. The spacer 134b is formed on the side wall of the dielectric pattern 128b, the side wall of the control gate electrode 130b, and the side wall of the hard mask pattern 132b.

After forming the spacer 134a and the spacer 134b, a patterning process (for example, an etching process) is performed to remove a portion of the conductive pattern 124b and a portion of the dielectric layer 126 that are not covered by the spacer 134a and the spacer 134b, so that the semiconductor A plurality of floating gate electrodes 124c and a plurality of dielectric patterns 126a are formed on the surface S2 of the substrate 100. The floating gate electrode 124c and the dielectric pattern 126a are self-aligned with the dielectric pattern 128b, the control gate electrode 130b and the hard mask pattern 132b. Since the conductive pattern 124b is slightly over-etched, the bottom portion of each spacer 134b may be in the conductive pattern The upper portion of 124b extends laterally, and the bottom portion of the spacer 134b may be in contact with the floating gate electrode 124c.

Referring to FIGS. 13 and 14, after forming the floating gate electrode 124 c and the dielectric pattern 126 a, a plurality of spacers 136 a and 136 b are formed. The partition wall 136a is formed on the partition wall 134a, and the partition wall 136b is formed on the partition wall 134b. In addition, the spacer 136b covers the side wall of the floating gate electrode 124c and the side wall of the dielectric pattern 126a. Next, a patterned photoresist layer 138 is formed, and an ion implantation process is performed, so that a plurality of doped regions 140 (eg, common source regions) are formed in the semiconductor substrate 100. In some embodiments, an annealing process may be further performed to anneal the doped regions 140 in the semiconductor substrate 100 so that the implanted ions or dopants can diffuse.

14 and 15, after the doped region 140 is formed in the semiconductor substrate 100, the spacer 136b exposed by the opening of the patterned photoresist layer 138 is removed until the sidewall of the spacer 134b and the floating gate electrode 124c And the sidewall of the dielectric pattern 126a is exposed by the opening of the patterned photoresist layer 138. Next, a plurality of dielectric layers 136c are formed in the opening of the patterned photoresist layer 138 to cover the sidewalls of the spacer 134b, the floating gate electrode 124c, and the sidewalls of the dielectric pattern 126a, and a plurality of oxide layers 136d are formed (For example, a common source oxidation layer (CSOX)) to cover the doped region 140 formed in the semiconductor substrate 100.

In some embodiments, to prevent contamination caused by the patterned photoresist layer 138, the patterned photoresist layer 138 is removed before the dielectric layer 136c and the oxide layer 136d are formed. In some embodiments, the patterned photoresist layer 138 may be removed by, for example, an ashing process or other suitable manufacturing.

Referring to FIGS. 16 and 17, a gate dielectric layer (not shown) and a conductive layer 142 are sequentially formed on the semiconductor substrate 100. In some embodiments, the conductive layer 142 It can be a doped polysilicon layer. For example, the conductive layer 142 may be formed by depositing a polysilicon layer, implanting dopants into the polysilicon layer, and annealing the doped polysilicon layer. The material of the above conductive layer 142 is for illustration only, and the disclosure is not limited thereto. Next, the conductive layer 142 is sequentially subjected to a polishing process (for example, a CMP process) and an etch-back process, so that a plurality of conductive patterns 142a with planarized top surfaces are formed. In some embodiments, the conductive layer 142 may be polished until the patterned hard mask layer 132a is exposed, and the polished conductive layer 142 may be etched back to form the conductive pattern 142a.

Referring to FIGS. 17 and 18, after the conductive pattern 142a is formed, a plurality of spacers 144 are formed on the conductive pattern 142a to cover the spacer 136a, the spacer 136b, and the dielectric layer 136c. Next, for example, the conductive pattern 142a and the gate dielectric layer are patterned by an etch-back process to form a plurality of selective gate electrodes 142b (eg, erase gate electrodes above the doped regions 140 and/or word lines (erase gate electrode) and a plurality of select gate oxide layers (SGOX) under the select gate electrode 142b. In other words, the conductive pattern 142a and the gate dielectric layer not covered by the plurality of spacers 144 are partially etched to form a plurality of selective gate electrodes 142b.

Referring to FIGS. 18 and 19, a grinding process (for example, a CMP process) is performed on the spacer 144 and the patterned hard mask layer 132a, so that a plurality of spacers 144a and a patterned hard mask having a reduced height are formed Layer 132c. During the grinding process of the spacer 144 and the patterned hard mask layer 132a, part of the spacer 134a, part of the spacer 134b, part of the spacer 136a, part of the spacer 136b, and part of the dielectric layer 136c are grinded. In some embodiments, before the grinding process of the spacer 144 and the patterned hard mask layer 132a, a bottom layer (not shown) for the grinding process may be coated to cover the grinding spacer 144 and the patterning Of the hard cover curtain layer 132a The structure on the front semiconductor substrate 100. Also, the bottom layer (not shown) may be removed after the grinding of the spacer 144 and the patterned hard mask layer 132a. After the grinding process of the spacer 144 and the patterned hard mask layer 132a, a dummy layer 148a may be formed to cover the first region 100A and the second region 100B of the semiconductor substrate 100. In some embodiments, the dummy layer 148a may include a liner oxide layer and a dummy polysilicon layer stacked on the liner oxide layer. The dummy layer 148a can be formed by sequentially depositing a liner oxide layer and a polysilicon layer, and etching back the polysilicon layer to form a dummy polysilicon layer on the liner oxide layer. The material and configuration of the dummy layer 148a are for illustration only, and the disclosure is not limited thereto.

20 and 21, a patterned photoresist layer 146 is formed to cover part of the dummy layer 148a. Next, for example, the dummy layer 148a, the patterned dielectric layer 128a, the patterned conductive layer 130a, and the patterned hard mask layer 132c are patterned by a lithography and etching process so that the first region of the semiconductor substrate 100 A dummy layer 148a1, a patterned dielectric layer 128c, a patterned conductive layer 130c, and a patterned hard mask layer 132d are formed on 100A. In some embodiments, the patterned conductive layer 130c and the patterned hard mask layer 132d may have a ring structure. After the dummy layer 148a1, the patterned dielectric layer 128c, the patterned conductive layer 130c, and the patterned hard mask layer 132d are formed, the patterned light can be removed by, for example, an ashing process or other suitable processes Ohmic layer 146. After removing the patterned photoresist layer 146, a dummy layer 148b may be formed on the first region 100A and the second region 100B of the semiconductor substrate 100. In some embodiments, the dummy layer 148b may include a dummy polysilicon layer. The material and configuration of the dummy layer 148b are for illustration only, and the disclosure is not limited thereto.

21 and 22, after forming the dummy layer 148b, the dummy layer 148a1 and the dummy layer 148b are partially removed until the patterned hard mask curtain layer 106a, the first A trench isolation 110a and a second trench isolation 110b are exposed, so that a patterned dummy layer 148 is formed. As shown in FIG. 22, the patterned hard mask layer 106a and the pad layer 102 that are not covered by the patterned dummy layer 148 are removed until the semiconductor portion 112 of the semiconductor substrate 100 is exposed.

Referring to FIGS. 22 and 23, after removing the patterned hard mask layer 106 a and the pad layer 102, part of the first trench isolation 110 a and the second trench isolation 110 b are exposed by the patterned dummy layer 148. The portions of the first trench isolation 110a and the second trench isolation 110b are partially removed and planarized so that the top surface of the first trench isolation 110a, the top surface of the second trench isolation 110b, and the top surface of the semiconductor portion 112 are substantially Located on the same level. In some embodiments, partial removal of the first trench isolation 110a and the second trench isolation 110b may be performed by, for example, an etching process.

23 and 24, a dielectric layer 150 is formed to cover the patterned dummy layer 148, the first trench isolation 110a, the second trench isolation 110b embedded in the dummy region 100B1 of the second region 100B, the semiconductor portion 112, and the first The peripheral circuit area 100B2 of the second area 100B. The dummy area 100B1 is located between the peripheral circuit area 100B2 and the first area 100A. The dielectric layer 150 may include a first portion 150a and a second portion 150b. The first portion 150a not only covers the patterned dummy layer 148, the first trench isolation 110a and the semiconductor portion 112, but also partially covers the second trench isolation 110b. The second portion 150b not only partially covers the second trench isolation 110b, but also covers the dummy area 100B1. As shown in FIG. 24, a part (eg, the left part) of the second trench isolation 110b is covered by the first part 150a, and another part (eg, the right part) of the second trench isolation 110b is covered by the second part 150b. The first portion 150a is thicker than the second portion 150b, and the thickness difference ranges from about 10 angstroms to about 500 angstroms, for example. First The thickness difference between the part 150a and the second part 150b is for illustration only, and the disclosure is not limited thereto.

As shown in FIGS. 36A and 36B, in some embodiments, the dielectric layer 150 including the first portion 150a and the second portion 150b may be formed by the following process. First, for example, a dielectric material layer 150M (as shown in FIG. 36A) is formed by a deposition process (for example, chemical vapor deposition or the like) to cover the resulting structure shown in FIG. 23, and by a lithography process in A patterned photoresist layer PR is formed on the dielectric material layer 150M. For example, the material of the dielectric material layer 150M includes oxide, nitride, oxynitride, a combination thereof, or the like. By using the patterned photoresist layer PR as a mask, a portion of the dielectric material layer 150M not covered by the patterned photoresist layer PR can be removed by an etching process or other suitable patterning process. After the dielectric layer 150 is formed, the patterned photoresist layer PR is removed. As shown in FIG. 36B, the distance D between the boundary B1 of the first region 100A and the outer boundary B2 of the first portion 150a may range from about 0.1 microns to about 50 microns. When the distance D between the boundary B1 of the first region 100A and the outer boundary B2 of the first portion 150a is greater than about 0.1 microns, there is sufficient space for forming the first dummy ring DR1 (as shown in FIGS. 29 to 32), The first dummy ring DR1 (shown in FIGS. 29 to 32) is made strong enough to prevent the expansion of CMP fishing.

As shown in FIGS. 37A and 37B, in some alternative embodiments, the dielectric layer 150 including the first portion 150a and the second portion 150b may be formed as follows. First, for example, a dielectric material layer 150M (as shown in FIG. 36A) is formed by a deposition process (for example, chemical vapor deposition or the like) to cover the resulting structure shown in FIG. 23, and by a lithography process in A patterned photoresist layer PR is formed on the dielectric material layer 150M. By using the patterned photoresist layer PR as a mask, the etching process can be used Or another suitable patterning process to remove the dielectric material layer 150M not covered by the patterned photoresist layer PR, so that a portion (eg, the left portion) of the second trench isolation 110b is covered by the first portion 150a, and the second Another part (for example, the right part) of the trench isolation 110b is exposed. After the first portion 150a is formed, the second portion 150b can be formed only on the peripheral circuit area 100B2 by the selective growth process (ie, the second portion 150b does not cover the second trench isolation 110b). After forming the first portion 150a or after forming the second portion 150b, the patterned photoresist layer PR is removed. As shown in FIGS. 37B and 37C, the distance D between the boundary B1 of the first region 100A and the outer boundary B2 of the first portion 150a may range from about 0.1 microns to about 50 microns. When the distance D between the boundary B1 of the first region 100A and the outer boundary B2 of the first portion 150a is greater than about 0.1 microns, there is enough space for forming the first dummy ring DR1 (as shown in FIGS. 29 to 32), The first dummy ring DR1 (as shown in FIGS. 29 to 32) can have sufficient strength to prevent the expansion of the CMP recess.

In some embodiments, the process shown in FIG. 37C is not used. In other words, in some embodiments, the formation of the second portion 150b on the peripheral circuit area 100B2 is not used.

24 and 25, after the dielectric layer 150 is formed, a plurality of gate electrodes 152 (eg, polysilicon gate electrodes) and a plurality of dielectrics provided on the plurality of gate electrodes 152 are formed on the peripheral circuit area 100B2电顶盖154. The material of the gate electrode 152 is for illustration only, and the disclosure is not limited thereto. In some embodiments, when forming the gate electrode 152 and the dielectric cap 154, a plurality of dummy patterns 156, dummy patterns 158, dummy patterns 160, dummy patterns 162, dummy patterns 164, and dummy patterns 166 may be formed. The material of the dummy pattern 156, the dummy pattern 160, and the dummy pattern 164 may be the same as the material of the gate electrode 152, and the dummy pattern 158, the dummy pattern 162 The material of the dummy pattern 166 may be the same as the material of the dielectric cap 154. The dummy pattern 156 and the dummy pattern 158 disposed on the dummy pattern 156 are formed on the second portion 150b and are located above the dummy area 100B1. The dummy pattern 160 and the dummy pattern 162 provided on the dummy pattern 160 are formed on the first portion 150a and are located above the dummy area 100B1. The dummy pattern 164 and the dummy pattern 166 provided on the dummy pattern 164 are formed on the first portion 150a and above the first area 100A. Due to the thickness difference between the first portion 150a and the second portion 150b, the top surfaces of the dummy pattern 162 and the dummy pattern 166 are higher than the top surfaces of the dummy pattern 158 and the top surface of the dielectric cap 154. For example, the dummy pattern 156 and the dummy pattern 158 are dot-shaped dummy patterns, and the dummy pattern 160, the dummy pattern 162, the dummy pattern 164, and the dummy pattern 166 are ring-shaped dummy patterns. The dot-shaped dummy patterns 156 and the dot-shaped dummy patterns 158 may be randomly (as shown in FIGS. 34 and 35) or regularly distributed above the second trench isolation 110b.

In some embodiments, the manufacture of the dummy pattern 164 and the dummy pattern 166 may be omitted according to design requirements. In some alternative embodiments, the manufacture of the dummy pattern 156 and the dummy pattern 158 may be omitted according to design requirements. In some alternative embodiments, the manufacture of the dummy pattern 156, the dummy pattern 158, the dummy pattern 164, and the dummy pattern 166 may be omitted according to design requirements.

25 and 26, after forming the gate electrode 152, the dielectric cap 154 and the dummy pattern 156, the dummy pattern 158, the dummy pattern 160, the dummy pattern 162, the dummy pattern 164 and the dummy pattern 166, the dielectric layer A patterned photoresist layer 168 is formed on 150 so that the gate electrode 152, the dielectric cap 154, and the dummy pattern 156, the dummy pattern 158, the dummy pattern 160, the dummy pattern 162, the dummy pattern 164, and the dummy pattern 166 are patterned The photoresist layer 168 covers. For example, conduct micro In the shadow and etching process, the dielectric layer 150 is patterned and the patterned dummy layer 148 is removed. Then, an ion implantation process is performed, so that a plurality of doped regions 170 (eg, lightly doped drain regions) are formed in the semiconductor substrate 100. In some embodiments, an annealing process may be further performed to anneal the doped region 170 in the semiconductor substrate 100 so that the implanted ions or dopants may diffuse.

In some embodiments, before or after the doped region 170 is formed, a plurality of lightly doped regions (for example, lightly doped drain regions) not shown in FIG. 26 may be formed in the peripheral circuit region 100B2.

Referring to FIG. 27, after the doped regions 170 are formed, a plurality of spacers 172 are formed on the sidewalls of the selection gate electrode 142b, and an ion implantation process is performed to form a plurality of doped regions 174 in the semiconductor substrate 100 (e.g. , Jiji District). In some embodiments, an annealing process may be further performed to anneal the doped regions 174 in the semiconductor substrate 100 so that the implanted ions or dopants can diffuse. After the doped region 174 is formed, the memory cell array M (ie, the first element) is formed. In some embodiments, the memory cell array M may include a plurality of memory cells arranged in an array. For example, the memory cell array M may be a non-volatile memory cell array, such as a flash memory cell array or the like. The type of the memory cell array M is for illustration only, and the disclosure is not limited thereto.

As shown in FIG. 27, the dielectric layer 150 is patterned to form a plurality of dielectric patterns 150a1, dielectric patterns 150a2, dielectric patterns 150b1, and dielectric patterns 150b2. The dielectric pattern 150a1 is disposed between the first trench isolation 110a and the dummy pattern 164, the dielectric pattern 150a2 is disposed between the second trench isolation 110b and the dummy pattern 160, and the dielectric pattern 150b1 is disposed between the semiconductor substrate 100 and the gate electrode 152 The dielectric pattern 150b2 is disposed between the second trench isolation 110b and the dummy pattern 156. For example, the materials of the dielectric pattern 150a1, the dielectric pattern 150a2, the dielectric pattern 150b1, and the dielectric pattern 150b2 may include oxide, nitride, oxynitride, and combinations thereof.

In some embodiments, a plurality of spacers 176 are formed on the sidewall of the gate electrode 152, the sidewall of the dielectric cap 154, and the sidewall of the dielectric pattern 150b1, and the dummy pattern 156, the dummy pattern 158, the dummy pattern 160, A plurality of spacers 178 are formed on the sidewalls of the dummy pattern 162, the dummy pattern 164, and the dummy pattern 166 and the sidewalls of the dielectric pattern 150a1, the dielectric pattern 150a2, and the dielectric pattern 150b2. In addition, a plurality of doped regions (for example, drain regions) not shown in FIG. 27 may be formed in the peripheral circuit region 100B2 before or after the doped region 174 is formed, so that the periphery may be formed on the peripheral circuit region 100B2 Circuit P (ie, the second element). The peripheral circuit P may include a plurality of logic elements (for example, MOS elements, each of which includes a dielectric pattern 150b1, a gate electrode 152, and a doped area in the peripheral circuit area 100B2). In some embodiments, the peripheral circuit P may include a core device, a static random access memory (SRAM), and input/output devices. The type of peripheral circuit P is for illustration only, and the disclosure is not limited thereto.

Referring to FIGS. 27 and 28, for example, an etch-back process is performed to remove the dielectric cap 154, the dummy pattern 158, the dummy pattern 162 and the dummy pattern 166, the spacer 144a, the hard mask pattern 132b, and the patterned hard mask Layer 132d. During the above etch-back process, the dielectric layer 136c and the spacer 134a, the spacer 134b, the spacer 136a, the spacer 136b, the spacer 172, the spacer 176, and the spacer 178 are partially removed and their heights are reduced. After the etch-back process, the patterned conductive layer 130c, the memory cell array M, the first dummy ring DR1, the second dummy ring DR2, a plurality of dummy dot patterns DP and the peripheral circuit P are exposed. First The top surface of one dummy ring DR1 and the top surface of the second dummy ring DR2 are, for example, substantially flat surfaces. The first dummy ring DR1 and the second dummy ring DR2 are disposed between the memory cell array M and the dummy dot pattern DP. The second dummy ring DR2 is disposed between the memory cell array M and the first dummy ring DR1. Since the second dummy ring DR2 is disposed between the memory cell array M and the first dummy ring DR1, the second dummy ring DR2 is an inner dummy ring, and the first dummy ring DR1 is an outer dummy ring.

In some embodiments, the first dummy ring DR1, the second dummy ring DR2, and the dummy dot pattern DP are electrically floating, because the first dummy ring DR1 and the dummy dot pattern DP are formed on the second trench isolation 110b And the second dummy ring DR2 is formed on the first trench isolation 110a. In other words, the first dummy ring DR1, the second dummy ring DR2, and the dummy dot pattern DP are electrically insulated from each other. In addition, the first dummy ring DR1, the second dummy ring DR2, and the dummy dot pattern DP are electrically insulated from other semiconductor elements (for example, the memory cell array M and the peripheral circuit P).

As shown in FIG. 28, in some embodiments, the patterned conductive layer 130c may be a ring structure, and the memory cell array M is surrounded by the patterned conductive layer 130c. The first dummy ring DR1 is disposed on the dummy area 100B1, and the first dummy ring DR1 is located between the second dummy ring DR2 and the dummy dot pattern DP. The first dummy ring DR1 may be a film stack including a dielectric pattern 150a2, a dummy pattern 160 (such as a polysilicon pattern), and a spacer 178, wherein the dummy pattern 160 is stacked on the dielectric pattern 150a2, and the spacer 178 covers the dielectric pattern 150a2 And the side wall of the dummy pattern 160. The second dummy ring DR2 may be a film stack including a dielectric pattern 150a1, a dummy pattern 164 (such as a polysilicon pattern), and a spacer 178, wherein the dummy pattern 164 is stacked on the dielectric pattern 150a1, and the spacer 178 covers the dielectric pattern 150a1 And the side wall of the dummy pattern 164. Each dummy dot pattern DP may include a dielectric A film stack of the pattern 150b2, the dummy pattern 156 (for example, polysilicon pattern), and the spacer 178, wherein the dummy pattern 156 is stacked on the dielectric pattern 150b2, and the spacer 178 covers the sidewall of the dielectric pattern 150b2 and the sidewall of the dummy pattern 156. For example, the materials of the dielectric pattern 150a1, the dielectric pattern 150a2, and the dielectric pattern 150b2 may include oxide, nitride, oxynitride, and combinations thereof. The material of the spacer 178 may include oxide, nitride, oxynitride, and combinations thereof. The materials of the dielectric pattern 150a1, the dielectric pattern 150a2 and the dielectric pattern 150b2, the material of the dummy pattern 156, the dummy pattern 160 and the dummy pattern 164, and the material of the spacer 178 are for illustration only, and the disclosure is not limited thereto.

As shown in FIGS. 28, 34, and 35, the memory cell array M is surrounded by the patterned conductive layer 130c. The memory cell array M and the peripheral circuit P are separated by a first trench isolation 110a and a second trench isolation 110b. The first dummy ring DR1 surrounds the memory cell array M. The first height H1 (for example, the first gate height) of the memory cell array M is greater than the second height H2 (for example, the second gate height) of the peripheral circuit P, the first thickness TH1 and the first thickness of the first dummy ring DR1 The second thickness TH2 of the two dummy rings DR2. The first thickness TH1 and the second thickness TH2 are substantially equal to each other and greater than the second height H2. In other words, the top surface of the memory cell array M is higher than the top surface of the peripheral circuit P, and the top surface of the memory cell array M may be slightly higher or substantially equal to the top surface of the first dummy ring DR1 and the second dummy The top surface of the ring DR2. In addition, since the dielectric patterns 150a1 and 150a2 are thicker than the dielectric patterns 150b1 and 150b2, the top surfaces of the first dummy ring DR1 and the second dummy ring DR2 are higher than the top surface of the peripheral circuit P Top surface with dummy dot pattern DP. In some embodiments, the first dummy ring DR1 is thicker than the dummy dot pattern DP, and the thickness difference ranges from about 10 angstroms to about 500 angstroms.

The level difference between the surface S1 and the surface S2 of the semiconductor substrate 100 can reduce the gate height difference between the memory cell array M formed on the first area 100A and the peripheral circuit P formed on the peripheral circuit area 100B2 .

28 and 29, a stop layer (or etch stop layer) 180 is formed on the semiconductor substrate 100 to cover the memory cell array M, the patterned conductive layer 130c, the first dummy ring DR1, and the second dummy ring DR2, dummy dot pattern DP and peripheral circuit P. Next, an inter-layered dielectric layer (ILD) 182 is formed on the etch stop layer 180. In some embodiments, the material of the etch stop layer 180 may include silicon oxide, silicon nitride (SiN), or silicon oxynitride (SiON), and the material of the interlayer dielectric layer 182 may include phosphorosilicate glass (PSG) , Borophosphosilicate glass (BPSG) or the like. The materials of the etch stop layer 180 and the interlayer dielectric layer 182 are for illustration only, and the disclosure is not limited thereto.

Referring to FIGS. 29 and 30, an ILD polishing process (for example, a CMP process) is performed on the interlayer dielectric layer 182 until a part of the stop layer 180 is exposed. In some embodiments, after performing the ILD polishing process, the top surface of the first dummy ring DR1, the top surface of the second dummy ring DR2, the top surface of the patterned conductive layer 130c, and the memory cell array M are partially stopped Layer 180 may be exposed. After the polishing process of the interlayer dielectric layer 182, the polished interlayer dielectric layer 182a is formed, and CMP recession may occur in the area above the dummy dot pattern DP and the peripheral circuit P. As shown in FIG. 30, the inclined surface IS1 caused by the CMP depression is generated. The first dummy ring DR1 distributed on the second region 100B helps control the expansion of the CMP recess. For example, the inclined surface IS1 caused by the ILD grinding process can be controlled in the second region 100B. In other words, the expansion of the CMP recess can be controlled by the first dummy ring DR1, so that After performing the ILD polishing process, the CMP recess may not be extended into the first region 100A. In the case where the first dummy ring DR1 distributed on the second region 100B is omitted, the CMP recess may expand into the first region 100A after performing the ILD polishing process.

Referring to FIG. 31, a stop layer polishing process (eg, a CMP process) is performed on the stop layer 180 until the top surface of the memory cell array M, the top surface of the patterned conductive layer 130c, the top surface of the first dummy ring DR1, the first The top surface of the second dummy ring DR2, the top surface of the dummy dot pattern DP and the top surface of the peripheral circuit P are exposed. After the polishing process of the stop layer 180 is performed, a polished and patterned stop layer 180a is formed, and CMP recession may occur in the area above the semiconductor portion 112, the first dummy ring DR1, the dummy dot pattern DP, and the peripheral circuit P. As shown in FIG. 31, another inclined surface IS2 caused by the CMP recess is generated. In other words, compared with FIG. 30, the CMP recess is expanded.

As shown in FIG. 31, during the polishing of the stop layer 180, since the first dummy ring DR1 is thicker than the dummy dot pattern DP and the peripheral circuit P, the first dummy ring DR1 can prevent the expansion of the CMP depression caused by the stop layer polishing , And the expansion of the depression can be controlled. After performing ILD polishing and stop layer polishing, the memory cell array M is not affected by the CMP recess phenomenon. In the case where the first dummy ring DR1 distributed on the second region 100B is omitted, the CMP recess may further expand into the first region 100A after the stop layer 180 is polished.

Referring to FIGS. 31 and 32, in some embodiments, a gate replacement process may be performed to replace the gate electrode 152 with a metal gate electrode MG. In some alternative embodiments, a gate replacement process may be performed to replace the gate electrode 152 and the dummy pattern 156 with the metal gate electrode MG and the metal pattern, respectively. During the gate replacement process, metal gate polishing (eg, CMP process) is performed, and the polished interlayer The electric layer 182a is further ground. After the polishing process of the metal gate electrode MG, CMP recession may occur in the area above the patterned conductive layer 130c, the semiconductor portion 112, the first dummy ring DR1, the dummy dot pattern DP, and the peripheral circuit P. As shown in FIG. 32, the inclined surface IS3 caused by the CMP recess is generated. In other words, the CMP recess further expands.

After performing ILD polishing, stop layer polishing, and metal gate electrode MG polishing, a patterned dielectric layer (ie, the polished and patterned stop layer 180a and the polished interlayer dielectric layer 182a) may be formed to Cover the semiconductor substrate 100. The memory cell array M, the peripheral circuit P, the first dummy ring DR1 and the second dummy ring DR2 are embedded in the patterned dielectric layer (ie, the polished and patterned stop layer 180a and the polished interlayer dielectric layer 182a )in. As shown in FIG. 31, the top surface of the first dummy ring DR1 is inclined. In addition, a portion of the polished interlayer dielectric layer 182a between the first dummy ring DR1 and the second dummy ring DR2 has an inclined top surface.

As shown in FIG. 32, during the polishing of the metal gate electrode MG, since the first dummy ring DR1 and the second dummy ring DR2 are thicker than the dummy dot pattern DP and the peripheral circuit P, the first dummy ring DR1 and the second dummy ring DR2 can prevent further expansion of the CMP depression caused by the grinding of the metal gate electrode MG, and the expansion of the CMP depression can be controlled. In other words, after the polishing of the stop layer 180 and the polishing of the metal gate electrode MG, a CMP recess occurs in the area above the second region 100B and the first trench isolation 110a, and the recess does not expand to affect memory Body cell array M. Therefore, the memory cell array M is not affected by ILD polishing, stop layer polishing, and gate replacement processes. The yield of the memory cell array M therefore increases. In the case where the first dummy ring DR1 distributed on the second area 100B is omitted, remember The memory cell array M may be affected by ILD polishing, stop layer polishing, and gate replacement processes.

After the grinding of the stop layer 180 and the grinding of the metal gate electrode MG, the thickness of the second dummy ring DR2 may be greater than the thickness of the first dummy ring DR1. The thickness of at least one first dummy ring DR1 may be greater than the thickness of the dummy dot pattern DP. The height of the peripheral circuit P may be substantially equal to the thickness of the dummy dot pattern DP. In some embodiments, the top surface of the first dummy ring DR1 and the top surface of the second dummy ring DR2 may be inclined surfaces.

After the polishing of the stop layer 180 and the polishing of the metal gate electrode MG, the height of the memory cell array M is greater than the height of the peripheral circuit P, the thickness of the first dummy ring DR1, and the thickness of the second dummy ring DR2. The top surface of the memory cell array M is higher than the top surface of the peripheral circuit P, and the top surface of the memory cell array M may be higher than the top surface of the first dummy ring DR1 and the second dummy ring DR2. In addition, the top surface of the first dummy ring DR1 and the top surface of the second dummy ring DR2 are higher than the top surface of the peripheral circuit P and the top surface of the dummy dot pattern DP.

As shown in FIGS. 26 to 32, the thickness difference between the first portion 150a and the second portion 150b (shown in FIG. 26) causes a thickness difference between the first dummy ring DR1 and the dummy dot pattern DP. As shown in FIGS. 30 to 32, in the polishing process of the ILD 182, the stop layer 180, and the metal gate electrode MG, due to the thickness difference between the first dummy ring DR1 and the dummy dot pattern DP, the first dummy ring DR1 may be It acts as a retarder to prevent the CMP recess from uncontrolled expansion to the memory cell array M. Therefore, the first dummy ring DR1 can protect the memory cell array M from the CMP recess.

33 is a top view schematically showing a wafer including a plurality of integrated circuit members arranged in an array according to some embodiments of the present disclosure; FIG. 34 is a schematic view showing FIG. 33 according to some embodiments of the present disclosure Enlarged top view of part X shown in.

Referring to FIGS. 32, 33, and 34, the above semiconductor structure (shown in FIG. 32) may be the wafer shown in FIG. 33, and the wafer may include a plurality of integrated circuit members 200 arranged in an array. Each integrated circuit component 200 may include a memory cell array M, a patterned conductive layer 130c, a first dummy ring DR1 (ie, outer dummy ring), a second dummy ring DR2 (ie, inner dummy ring), and a dummy point Pattern DP and peripheral circuit P. From the top view shown in FIG. 33, the patterned conductive layer 130c, the first dummy ring DR1, the semiconductor portion 112, and the second dummy ring DR2 have a ring structure. The memory cell array M is surrounded by the patterned conductive layer 130c, the first dummy ring DR1, the semiconductor portion 112, and the second dummy ring DR2. The patterned conductive layer 130c and the second dummy ring DR2 are disposed on the first trench isolation 110a, and the first dummy ring DR1 and the dummy dot pattern DP are disposed on the second trench isolation 110b. The dummy dot pattern DP is distributed between the first dummy ring DR1 and the peripheral circuit P.

FIG. 35 is an enlarged top view schematically showing part X shown in FIG. 33 according to some alternative embodiments of the present disclosure.

Referring to FIGS. 33, 34, and 35, the integrated circuit member 200a shown in FIG. 35 is similar to the integrated circuit member 200 shown in FIG. 34, except that two first Dummy ring DR1. The number of the first dummy ring DR1 is not limited in this application. In addition, the line width of each first dummy ring DR1 is not limited in this application.

In the above embodiment, at least one dummy ring between the first element (for example, the memory cell array M) and the second element (for example, the peripheral circuit P) is used to minimize the side effects caused by the polishing process. Therefore, the first element (for example, the memory cell array M) can be well protected, and the manufacturing yield can be improved.

According to some embodiments of the present disclosure, a semiconductor structure is provided, which includes a semiconductor substrate and at least one patterned dielectric layer. The semiconductor substrate includes a semiconductor portion, at least one first element, at least one second element, and at least one first dummy ring. At least one first element is disposed in the first region surrounded by the semiconductor portion. At least one second element and at least one first dummy ring are disposed on the second area, and the second area surrounds the first area. At least one patterned dielectric layer covers the semiconductor substrate.

In the above semiconductor structure, the first height of at least one first element is greater than the second height of at least one second element and the first thickness of at least one first dummy ring, and the first thickness is greater than the second height.

In the above semiconductor structure, at least one first dummy ring is electrically floating.

In the above semiconductor structure, at least one first dummy ring has an inclined top surface.

The above semiconductor structure further includes at least one second dummy ring disposed on the first region, wherein at least one first dummy ring and at least one second dummy ring surround at least one first element, and at least one second dummy ring is At least one first dummy ring thickness.

According to some embodiments of the present disclosure, a semiconductor structure is provided, which includes a semiconductor substrate and at least one patterned dielectric layer. The semiconductor substrate includes an active area and a peripheral area surrounding the active area, and at least one first element disposed on the active area Pieces, at least one second element disposed on the peripheral area, and at least one first dummy ring disposed on the peripheral area. At least one first element and at least one second element are spaced apart by the semiconductor portion of the active region. At least one patterned dielectric layer is disposed on the semiconductor substrate. At least one first element, at least one second element, and at least one first dummy ring are embedded in the patterned dielectric layer.

In the above semiconductor structure, the first height of at least one first element is greater than the second height of at least one second element and the first thickness of at least one first dummy ring, and the first thickness is greater than the second height.

In the above semiconductor structure, at least one first dummy ring is electrically floating.

In the above semiconductor structure, at least one first dummy ring has an inclined top surface.

The above semiconductor structure further includes at least one second dummy ring disposed on the active region, wherein at least one first dummy ring and at least one second dummy ring surround at least one first element, and at least one second dummy ring is more than A first dummy ring is thick.

In the above semiconductor structure, the semiconductor substrate further includes a first trench isolation embedded in the active area and a second trench isolation embedded in the peripheral area, the semiconductor portion is located between the first trench isolation and the second trench isolation, and at least one The first dummy ring is disposed on the second trench isolation.

The above semiconductor structure further includes at least one second dummy ring disposed on the first trench isolation, wherein at least one first dummy ring and at least one second dummy ring surround at least one first element, and at least one second dummy The ring is thicker than at least one first dummy ring.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, which includes the following steps. A semiconductor substrate having a semiconductor portion is provided. At least one first element is formed on the first region surrounded by the semiconductor portion. At least one second element and at least one first dummy ring are formed on the second area, wherein the second area surrounds the first area, and at least one first dummy ring surrounds at least one first element. At least one dielectric layer is formed on the semiconductor substrate to cover at least one first element, at least one second element, and at least one first dummy ring. Grind at least one dielectric layer until at least one first element, at least one second element, and at least one first dummy ring are exposed.

In the above method of manufacturing a semiconductor structure, wherein after grinding at least one dielectric layer, at least one first dummy ring is partially ground so that the first height of at least one first element is greater than the second height of at least one second element and The first thickness of the at least one first dummy ring is greater than the second height.

In the above method of manufacturing a semiconductor structure, wherein before grinding at least one dielectric layer, at least one first dummy ring includes a substantially flat top surface, and after grinding at least one dielectric layer, at least one first dummy ring includes Inclined top surface.

In the above method for manufacturing a semiconductor structure, the method further includes forming a plurality of dummy dot patterns on the second trench isolation in the second region, wherein at least one first dummy ring is located between the at least one first element and the plurality of dummy dot patterns, And at least one first dummy ring is thicker than a plurality of dummy dot patterns.

In the above method for manufacturing a semiconductor structure, it further includes forming at least one second dummy ring on the first trench isolation in the first region, wherein at least one second dummy ring surrounds at least one first element, and at least one second dummy ring The second thickness is greater than the first thickness of the at least one first dummy ring.

In the above method for manufacturing a semiconductor structure, wherein forming at least one second element and at least one first dummy ring on the second region includes: forming a dielectric layer on the second region, the dielectric layer includes a first portion and a second portion, And the first part is thicker than the second part; a plurality of stacked dummy patterns are formed on the first part of the dielectric layer; a gate electrode provided on the second part of the dielectric layer and a dielectric top stacked on the gate electrode are formed A cover; and using a stacked dummy pattern, a gate electrode, and a dielectric cap as a mask to pattern the dielectric layer to form a first dielectric pattern under the stacked dummy pattern, and a second dielectric under the gate electrode In the pattern, at least one first dummy ring including the first dielectric pattern and the stacked dummy pattern is formed, and at least one second element including the second dielectric pattern, the gate electrode, and the dielectric cap.

In the above method of manufacturing a semiconductor structure, the thickness difference between the first portion and the second portion ranges from about 10 angstroms to about 500 angstroms.

In the above method of manufacturing a semiconductor structure, the distance between the boundary of the first region and the outer boundary of the first portion ranges from about 0.1 micrometer to about 50 micrometers.

The above outlines the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and/or achieve the same goals and/or implementations as the embodiments described herein. The same advantages as the embodiment. Those skilled in the art should also realize that these equivalent structures do not deviate from the spirit and scope of this disclosure, and they can make various changes, substitutions, and substitutions without departing from the spirit and scope of this disclosure. change.

100‧‧‧Semiconductor substrate

100A‧‧‧District 1

100B‧‧‧District 2

110a‧‧‧The first trench isolation

110b‧‧‧Second trench isolation

112‧‧‧Semiconductor

130c‧‧‧patterned conductive layer

180a‧‧‧patterned stop layer

182a‧‧‧polished interlayer dielectric layer

DP‧‧‧Dummy dot pattern

DR1‧‧‧The first dummy ring

DR2‧‧‧The second dummy ring

IS3‧‧‧inclined surface

M‧‧‧Memory cell array

MG‧‧‧Metal gate electrode

P‧‧‧Peripheral circuit

Claims (11)

A semiconductor structure includes: a semiconductor substrate, including a semiconductor portion, at least one first element, at least one second element, and at least one first dummy ring, the at least one first element is disposed at a first surrounding by the semiconductor portion On the area, the at least one second element and the at least one first dummy ring are disposed on the second area, and the second area surrounds the first area; and at least one patterned dielectric layer is provided On the semiconductor substrate, the at least one first element, the at least one second element, and the at least one first dummy ring are embedded in the at least one patterned dielectric layer. A semiconductor structure includes: a semiconductor substrate, including: an active area and a peripheral area surrounding the active area; at least one first element disposed on the active area; at least one second element disposed on the peripheral area ; And at least one first dummy ring disposed on the peripheral region, wherein the at least one first element and the at least one second element are separated by the semiconductor portion of the active region; and at least one patterned A dielectric layer is disposed on the semiconductor substrate, wherein the at least one first element, the at least one second element, and the at least one first dummy ring are embedded in the patterned dielectric layer. The semiconductor structure according to item 1 or 2 of the patent application scope, wherein the first height of the at least one first element is greater than the second height of the at least one second element and the first height of the at least one first dummy ring A thickness, and the first thickness is greater than the second height. The semiconductor structure according to item 1 or 2 of the patent application scope, wherein the at least one first dummy ring is electrically floating. The semiconductor structure according to item 1 or 2 of the patent application range, wherein the at least one first dummy ring has an inclined top surface. The semiconductor structure as described in item 2 of the patent application scope, wherein the semiconductor substrate further includes a first trench isolation embedded in the active area and a second trench isolation embedded in the peripheral area, the semiconductor portion It is located between the first trench isolation and the second trench isolation, and the at least one first dummy ring is disposed on the second trench isolation. A method of manufacturing a semiconductor structure, comprising: providing a semiconductor substrate including a semiconductor portion; forming at least one first element on a first area surrounded by the semiconductor portion; forming at least one second element on a second area An element and at least one first dummy ring, wherein the second region surrounds the first region, and the at least one first dummy ring surrounds the at least one first element; at least one dielectric layer is formed on the semiconductor substrate An electrical layer to cover the at least one first element, the at least one second element, and the at least one first dummy ring; and grinding the at least one dielectric layer until the at least one first element, The at least one second element and the at least one first dummy ring are exposed. The method for manufacturing a semiconductor structure as described in item 7 of the patent application scope, in which After grinding the at least one dielectric layer, the at least one first dummy ring is partially ground so that the first height of the at least one first element is greater than the second height of the at least one second element and the A first thickness of at least one first dummy ring, and the first thickness is greater than the second height. The method for manufacturing a semiconductor structure according to item 7 of the patent application range, wherein before grinding the at least one dielectric layer, the at least one first dummy ring includes a substantially flat top surface, and grinding the at least one After one dielectric layer, the at least one first dummy ring includes an inclined top surface. The method for manufacturing a semiconductor structure as described in item 7 of the patent application scope further includes: forming a plurality of dummy dot patterns on the second trench isolation of the second region, wherein the at least one first dummy ring is located on the Between at least one first element and the plurality of dummy dot patterns, and the at least one first dummy ring is thicker than the plurality of dummy dot patterns. The method for manufacturing a semiconductor structure according to item 7 of the patent application range, wherein forming the at least one second element and the at least one first dummy ring on the second region includes: forming in the second region A dielectric layer including a first portion and a second portion, and the first portion is thicker than the second portion; forming a plurality of stacked dummy patterns on the first portion of the dielectric layer; forming A gate electrode provided on the second portion of the dielectric layer and a dielectric cap stacked on the gate electrode; and using the stacked dummy pattern, the gate electrode and the dielectric The electric cap serves as a mask to pattern the dielectric layer to form a first under the stacked dummy pattern A dielectric pattern, and a second dielectric pattern is formed under the gate electrode, wherein the at least one first dummy ring including the first dielectric pattern and the stacked dummy pattern is formed, and includes the The at least one second element of a second dielectric pattern, the gate electrode, and the dielectric cap.

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