JP2016072537A - Semiconductor storage device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which reduce leakage current to achieve low power consumption.SOLUTION: A semiconductor device comprises: a semiconductor substrate 100 having a recessed region 105 formed on a surface in a recessed shape lower than the circumference; a plurality of series-connected cell transistors MC formed above the semiconductor substrate 100; a source line contact SLC with a bottom contacting the semiconductor substrate 100 in the recessed region; a bit line contact CB with a bottom contacting the semiconductor substrate 100 at a position higher than the bottom of the source line contact SLC; a source line side selection transistor SS connected to between the source line contact SLC and the cell transistor MC; and a bit line side selection transistor SB formed between the bit line contact and the cell transistor MC.SELECTED DRAWING: Figure 5

Description

  Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

  Increasing capacity and accompanying miniaturization of semiconductor memory devices are progressing. With this miniaturization, it is necessary to miniaturize wiring and contacts. Among the contacts, in particular, the bit line contact and the source line contact greatly contribute to the area of the memory device, and the demand for further miniaturization is increasing.

  It is known that as the contact becomes finer, it becomes more difficult to control pattern formation and processing. In particular, it has been known that the opening areas of the bit line contact and the source line contact are different, resulting in a difference in etching rate, and simultaneous processing is difficult.

US Patent Application Publication No. 2014/0070297 JP 2010-50357 A JP 2010-87162 A

  An object of the present embodiment is to provide a semiconductor memory device with low power consumption and a method for manufacturing the same.

  A semiconductor memory device according to an embodiment includes a semiconductor substrate having a recessed region formed to be recessed on the surface lower than the periphery, a plurality of cell transistors formed in series above the semiconductor substrate and connected in series, and the recessed portion A source line contact provided in contact with the bottom of the semiconductor substrate, a bit line contact provided in contact with the bottom of the semiconductor substrate at a position higher than the bottom of the source line contact, and the source line A source line side select transistor connected between the contact and the cell transistor; and a bit line side select transistor formed between the bit line contact and the cell transistor.

1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment. 1 is a schematic plan view of a semiconductor device according to a first embodiment. FIG. 3 is a circuit diagram schematically showing a memory cell array of the semiconductor device according to the first embodiment. FIG. 2 is a schematic plan layout diagram of a memory cell array of the semiconductor device according to the first embodiment. Schematic cross-sectional view of the semiconductor device according to the first embodiment Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 1) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 2) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 3) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 4) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 5) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 6) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 7) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 8) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 9) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 10) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 11) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 12) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 13) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 14) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 15) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 16) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 17) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 18) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 14) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 15) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 16) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 17) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 18) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 18) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 19) Typical sectional drawing which shows the manufacturing process of 1st Embodiment (the 20) Schematic sectional view showing a modification of the first embodiment Schematic sectional view showing a modification of the first embodiment Schematic sectional view showing a modification of the first embodiment

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In the following description, for convenience, the side closer to the semiconductor substrate side is expressed as the lower side.

(First embodiment)
As the first embodiment, a NAND flash memory will be described as an example. FIG. 1 is a block diagram showing a configuration of the semiconductor memory device 5 according to the first embodiment.

  The semiconductor memory device 5 includes a memory cell array 10 and a peripheral circuit 7 that is the other part. The memory cell array 10 mainly stores data. Further, various operations such as reading and writing of data are performed in accordance with the input from the peripheral circuit 7. The peripheral circuit 7 supplies necessary voltages to the memory cell array 10 in response to external inputs, and performs various operations for the semiconductor memory device 5 to function.

  In the memory cell array 10, a plurality of memory cells are arranged in a matrix. The memory cell has an electrically rewritable EEPROM cell. The memory cell array 10 includes a plurality of bit lines, a plurality of word lines, and source lines in order to control the voltage of the memory cells.

  As shown in FIG. 1 as an example, the peripheral circuit 7 includes a word line driver 15, a sense amplifier 20, a column decoder 25, an input / output control unit 30, an input / output buffer 35, an address decoder 40, a controller 45, and an internal voltage generation unit 50. , And a register 55.

  The word line driver 15 is connected to a plurality of word lines related to the memory cell array 10. The word line driver 15 selects and drives a word line based on the output signal of the address decoder 40 when reading, writing, and erasing data.

  The sense amplifier 20 detects bit line data when reading data. In addition, a voltage corresponding to the write data is applied to the bit line when writing data.

  The column decoder 25 generates a column selection signal for selecting a bit line based on the output signal of the address decoder 40 and sends this column selection signal to the sense amplifier 20.

  The input / output control unit 30 receives various commands CMD, an address signal ADD, and data DT (including write data) supplied from the outside.

  Specifically, at the time of data writing, the write data is sent to the sense amplifier 20 via the input / output control unit 30 and the input / output buffer 35. At the time of data reading, the read data read by the sense amplifier 20 is sent to the input / output control unit 30 via the input / output buffer 35. Then, the read data is output to an external HM (for example, a memory controller or a host) via the input / output control unit 30.

  The address signal ADD sent from the input / output control unit 30 to the input / output buffer 35 is sent to the address decoder 40. The address decoder 40 decodes the address signal ADD, sends the row address to the word line driver 15, and sends the column address to the column decoder 25.

  The command CMD sent from the input / output control unit 30 to the input / output buffer 35 is sent to the controller 45.

  The controller 45 is supplied with external control signals such as a chip enable signal / CE, a write enable signal / WE, a read enable signal / RE, an address latch enable signal ALE, and a command latch enable signal CLE from the external HM.

  The controller 45 generates a control signal for controlling a data writing and erasing sequence and a control signal for controlling reading of data based on an external control signal and a command CMD supplied according to the operation mode. This control signal is sent to the word line driver 15, the sense amplifier 20, the internal voltage generation unit 50, and the like. 45 comprehensively controls various operations of the semiconductor memory device 5 using this control signal.

  The controller 45 does not necessarily have to be arranged in the semiconductor memory device 5. That is, the semiconductor memory device 5 may be disposed in a different semiconductor device, or may be disposed in the external HM.

  The internal voltage generator 50 performs various operations of the memory cell array 10, the word line driver 15, and the sense amplifier 20, such as a read voltage, a write voltage, a verify voltage, and an erase voltage, according to various control signals sent from the controller 45. Generate the necessary voltage.

  The register 55 is connected to the input / output control unit 30 and the controller 45 and stores parameters suitable for the quality of the chip determined in the test process.

  FIG. 2 is a schematic plan view of the semiconductor memory device 5 according to the first embodiment shown in FIG.

  Two memory cell arrays 10 are provided inside the semiconductor memory device 5. A peripheral circuit 7 is formed outside the area of the memory cell array 10.

  As the peripheral circuit 7, a word line driver 15, a sense amplifier 20, and a column decoder 25 are provided so as to be in contact with the memory cell array 10. In other regions, the input / output control unit 30, the input / output buffer 35, the address decoder 40, the controller 45, the internal voltage generation unit 50, the register 55, and the like described in FIG. 1 are formed.

  These peripheral circuits include two or more types of transistors having different operating voltages. For convenience, a transistor with a low operating voltage is called a low voltage transistor, and a transistor with a high operating voltage is called a high voltage transistor. The film thickness of the gate insulating film differs between the low voltage transistor and the high voltage transistor due to the difference in operating voltage.

  FIG. 3 shows an example of the configuration of the NAND flash memory. FIG. 3 is a circuit diagram schematically showing a part of the memory cell array 10 of the NAND flash memory.

  In FIG. 3, BL1 to BL5 are bit lines, WL (1) to WL (n) are word lines (control gates), DWL (1) and DWL (2) are dummy word lines, SGB (1) and SGB (2 ) Denotes a selection gate line of the selection transistor on the bit line side, SGS (1) and SGS (2) denote selection gate lines of the selection transistor on the source line side, and SL denotes a source line. MC (1) to MC (n) are memory cells (also referred to as memory cell transistors), DMC (1) and DMC (2) are dummy memory cells (also referred to as dummy memory cell transistors), SB (1) and SB (2 ) Indicates a bit line side select transistor, SS (1) and SS (2) indicate source line side select transistors, CB indicates a bit line contact, and SLC indicates a source line contact.

  In the case where distinction is not necessary, the memory cell MC, the dummy memory cell DMC, the bit line side selection transistor SB, the source line side selection transistor SS, the bit line BL, the word line WL, the selection gate line SGB, and the selection gate line SGS. Call it. The dummy memory cell transistor DMC and the memory cell transistor MC are collectively referred to as cell transistors. Further, the bit line side select transistor SB and the source line side select transistor SS are collectively referred to as a select transistor.

  As shown in FIG. 3, the memory cell array 10 includes a plurality of NAND strings NS.

  Each NAND string NS includes, for example, m memory cells MC (1) to MC (n) connected in series, and two dummy memory cells DMC (1) and DMC (2) respectively connected to both ends thereof. And a bit line side select transistor SB (1) and a source line side select transistor SS (1) respectively connected to both ends thereof.

  The other end of the bit line side select transistor SB (1) is connected to one end of the bit line side select transistor SB (2) related to another NAND string NS and also connected to the bit line BL via the bit line contact CB. . The other end of the source line side select transistor SS (1) is connected to one end of the source line side select transistor SS (2) related to another NAND string NS and also connected to the source line SL via the source line contact SLC. .

  The memory cell MC may be a charge storage film (for example, a floating gate electrode or an insulating film having a trap) formed on a semiconductor substrate (well) with a gate insulating film interposed therebetween, or a film in which these are stacked. And a control gate electrode formed on the charge storage film with an inter-gate insulating film interposed therebetween. The memory cell MC can store, for example, 1.5 bits (three or more values) of data in one memory cell MC in accordance with a change in threshold voltage due to the amount of electrons injected into the charge storage film. .

  The dummy memory cell DMC includes the same film as the memory cell MC. However, the data from the user of the semiconductor memory device 5 need not necessarily be saved.

  The bit line side selection transistor SB and the source line side selection transistor SS control selection / non-selection of the NAND string NS.

  FIG. 4 schematically shows a plan view of the memory cell array of the NAND flash memory shown in FIG. In the following description, the extending direction of the bit line is referred to as the column direction, and the extending direction of the word line is referred to as the row direction.

  As shown in FIG. 4, a plurality of active areas AA extending in the column direction are formed. The active areas AA are provided separated from each other by the element isolation region STI.

  Word lines WL (1) to WL (n), dummy word lines DWL (1) and DWL (2), select gate lines SGB (1), SGB (2), SGS (1), and SGS (2) are It is formed by extending in the row direction so as to be substantially orthogonal to the active area AA. Memory cells MC (1) to MC (n) are formed at the intersections of the active area AA and the word lines WL (1) to WL (n). Similarly, dummy memory cells DMC (1) and DMC (2) are formed at the intersections with the dummy word lines DWL (1) and DWL (2). Bit line side select transistors SB (1) and SB (2) are formed at the intersections with the select gate lines SGB (1) and SGB (2). Source line side select transistors SS (1) and SS (2) are formed at the intersections with the select gate lines SGS (1) and SGS (2).

  The source line SL is formed by extending in the row direction so as to be substantially orthogonal to the active area AA. Source line SL is connected to active area AA via source line contact SLC. The source line contact SLC is formed in a line shape across the active area in the row direction as shown in FIG.

  The bit line contact CB connects each bit line (not shown) and each active area AA. Therefore, unlike the source line contact SLC, each active area is formed in a plug shape.

  That is, as apparent from FIG. 4, the source line contact SLC has a larger area in plan view than the bit line contact CB.

  FIG. 5 schematically shows a cross-sectional view of the semiconductor memory device of this embodiment. FIG. 5A schematically shows a cross-sectional view taken along the line A-A ′ of FIG. 4. 5A is omitted from FIG. 4 for convenience of explanation.

  FIG. 5B schematically shows a cross-sectional view of the low-voltage transistor. FIG. 5C schematically shows a cross-sectional view of the high-voltage transistor. The low voltage transistor and the high voltage transistor are arbitrary transistors formed in the peripheral circuit 7 illustrated in FIG.

  First, the memory cell array region will be described with reference to FIG. The recess 105 provided between the source line side select transistor SS (1) and the source line side select transistor SS (2) will be described later.

  As shown in FIG. 5A, on the semiconductor substrate 100, memory cells MC (1) (not shown) to MC (n) are formed side by side. Dummy memory cells DMC (1) and DMC (2) are formed on both sides of the memory cells MC (1) to MC (n), respectively. Further, a bit line side select transistor SB (1) and a source line side select transistor SS (1) are formed on both sides thereof.

  In other words, the memory cells MC (1) to MC (n) are provided between the dummy memory cells DMC (1) and DMC (2). The dummy memory cell DMC (1) is provided between the memory cell MC (1) and the bit line side select transistor SB (1). The dummy memory cell DMC (2) is provided between the memory cell MC (n) and the source line side select transistor SS (1).

  Between these memory cells MC (1) to MC (n), dummy memory cells DMC (1) and DMC (2), and bit line side select transistor SB (1) and source line side select transistor SS (1) A first impurity diffusion layer 230 is formed in the source / drain regions. Each source / drain region is connected via the first impurity diffusion layer 230.

  The source region of the bit line side select transistor SB (1) is connected to the source region of the dummy memory cell DMC (1). The drain region of the bit line side select transistor SB (1) is connected to the drain region of the bit line side select transistor SB (2) and to the bit line contact CB.

  The bit line contact CB is connected to a bit line (not shown) via the first wiring contact 333 in the upper layer.

  One of the drain regions of the source line side select transistor SS (1) is connected to the source region of the dummy memory cell DMC (2) as described above. The source region of the source line side select transistor SS (1) is connected to the source region of the source line side select transistor SS (2) and to the source line contact SLC.

  The source line contact SLC is connected to the first wiring (source line) 335.

  Next, a more detailed structure of each element will be described.

  Memory cells MC (1) to MC (n), dummy memory cells DMC (1) and DMC (2), source line side select transistors SS (1) and SS (2), bit line side select transistors SB (1) and The gate insulating film and the gate electrode of SB (2) have a structure including the same film.

  These transistors include a second gate insulating film 130, a first memory gate insulating film 160, a charge storage film 170, a second memory gate insulating film 180, and a conductive film 210. A cover film 220, an insulating film 240, and a stopper film 280 are provided on the gate electrodes of these transistors.

  As an example, for example, the second gate insulating film 130 is a silicon oxide film, the first memory gate insulating film 160 is a silicon oxide film, the charge storage film 170 is a silicon film, and the second memory gate insulating film 180 is a hafnium oxide film and a silicon oxide film. The conductive film 210 is made of tungsten, the cover film 220 is made of a silicon nitride film, the insulating film 240 is made of a silicon oxide film, and the stopper film 280 is made of a silicon nitride film.

  A spacer 270 and a stopper film 280 are formed on the side wall on the bit line contact CB side of the bit line side select transistor SB and the side wall on the source line contact SLC side of the source line side select transistor SS.

  Gaps 245 are formed between the bit line side select transistor SB and the source line side select transistor SS and the dummy memory cell DMC, between the dummy memory cell DMC and the memory cell MC, and between the memory cells MC, respectively. .

  The bit line contact CB and the source line contact SLC have, for example, a metal film and a barrier metal film. As the metal film, a conductive metal such as tungsten, aluminum, or copper is used. As the barrier metal film, titanium, tantalum, titanium nitride, tantalum nitride, or a laminated film thereof is used. In addition to the metal film and the barrier metal film, a silicon film may be used.

  Next, the low voltage transistor and the high voltage transistor will be described with reference to FIGS. 5B and 5C.

  An element isolation region STI is provided on the semiconductor substrate 100.

  In the low voltage transistor, the second gate insulating film 130 is provided on the semiconductor substrate 100, and the gate electrode GC is provided thereon. On the other hand, in the high voltage transistor, the first gate insulating film 120 and the second gate insulating film 130 are provided on the semiconductor substrate 100, and the gate electrode GC is provided thereon. That is, the configuration of the gate insulating film is different between the low voltage transistor and the high voltage transistor. The first gate insulating film 120 and the second gate insulating film are, for example, silicon oxide films.

  A second impurity diffusion layer 260 is formed on the semiconductor substrate 100 so as to sandwich a region directly under the gate electrode GC.

  Each of the gate electrodes GC of the low voltage transistor and the high voltage transistor includes, for example, a peripheral gate electrode film 140 and a conductive film 210. A cover film 220, an insulating film 240, and a stopper film 280 are provided on the gate electrode. A spacer 270 and a stopper film 280 are provided on the side walls of the gate electrodes of these transistors.

  Subsequently, the height of the upper surface of the semiconductor substrate 100 in the recess 105 and each region will be described with reference to FIGS. In the following description, for the sake of convenience, the height of the surface of the semiconductor substrate 100 in the region where the memory cells MC are formed will be described as a reference. That is, for example, when the surface of the semiconductor substrate 100 is at a higher position than the height of the surface of the semiconductor substrate 100 in the region where the memory cell MC (1) is formed, it is called “high” and at a lower position. When the surface of the semiconductor substrate 100 is present, it is called “low” or “deep”.

  As shown in FIG. 5A, part of the region where the source line side select transistors SS (1) and SS (2) are formed, and the source line side select transistor SS (1) and the source line side select transistor In the region between SS (2), the semiconductor substrate 100 has a recess 105 formed in a recess on the surface lower than the periphery. The depth of the concave portion 105 is b1.

  Since the semiconductor substrate 100 has the recess 105, the source line side selection transistors SS (1) and SS (2) are formed in a bent shape as shown in FIG. That is, the gate electrode, the gate insulating film, and the channel region related to the source line side select transistors SS (1) and SS (2) are formed in a bent shape.

  Due to the bending, the length of the channel region of the source line side select transistor SS becomes longer than that when the source line side select transistor SS is formed flat like the bit line side select transistor SB. That is, the controllability of the source line side select transistor SS is improved.

  Note that the semiconductor substrate 100 is further lowered between the spacers 270 related to the source line side select transistors SS (1) and SS (2). This depth is defined as b1 + b2.

  Next, a region where the low voltage transistor of FIG. 5B is formed will be described.

  The semiconductor substrate 100 under the gate electrode GC of the low voltage transistor is also formed low, and this depth is b3.

  Here, as described later in the manufacturing method, b3 and b1 are substantially the same because they are generated by the same RIE etching process. However, in each region, a film formed on the semiconductor substrate 100 is different, and thus a difference in diffusion of elements constituting the semiconductor substrate 100 from the semiconductor substrate 100 is different, so that a difference of about several nm may occur. .

  Subsequently, a region where the high voltage transistor of FIG. 5C is formed will be described. The semiconductor substrate 100 under the gate electrode GC of the high voltage transistor is also formed low, and this depth is b4.

  Hereinafter, a method for manufacturing the semiconductor memory device according to the present embodiment will be described with reference to FIGS. 6A to 29B, FIG. 6A is a cross section taken along the line AA ′ in FIG. 4 (column direction), FIG. 5B is a cross section of the low-voltage transistor in the peripheral circuit portion, and FIG. ) Shows a cross section of the high voltage transistor in the peripheral circuit section. For convenience, they are hereinafter referred to as a memory cell region, a low voltage transistor region, and a high voltage transistor region, respectively. 6 to 29 are different from FIG. 5 in aspect ratio for convenience of explanation.

  First, FIG. 6 shows the state of the semiconductor substrate 100. The semiconductor substrate 100 has the same height in all of the memory cell region, the low voltage transistor region, and the high voltage transistor region.

  Then, as shown in FIG. 7, a mask pattern (not shown) is formed on the semiconductor substrate 100, and the high voltage transistor region is etched by RIE. This etching depth is defined as d1.

  Then, as shown in FIG. 8, a mask pattern (not shown) is formed on the semiconductor substrate 100 and etched by RIE. By this etching process, the high voltage transistor region and the low voltage transistor region are processed, and the recess 105 is formed in the memory cell region. This etching depth is defined as d2.

  Thereafter, a sacrificial oxide film (not shown) is formed, and impurities are implanted by an implantation method, thereby forming P-type and N-type wells (not shown).

  Then, as shown in FIG. 9, after the sacrificial oxide film 110 is removed, a first gate insulating film 120 is formed. As the first gate insulating film 120, for example, a silicon oxide film, a silicon oxynitride film, or the like is used.

  Then, as shown in FIG. 10, after forming a mask pattern (not shown), the first gate insulating film 120 other than the high-voltage transistor region is etched using a chemical solution such as hydrofluoric acid.

  Then, as shown in FIG. 11, a second gate insulating film 130 is formed on the semiconductor substrate 100 and the first gate insulating film 120. As the second gate insulating film 130, for example, a silicon oxide film, a silicon oxynitride film, or the like is used.

  Thereby, the first gate insulating film 120 and the second gate insulating film 130 are formed in the high voltage transistor region. On the other hand, a second gate insulating film 130 is formed in the low voltage transistor region and the memory cell region.

  Note that it is desirable that the height of the upper end of the second gate insulating film 130 in the low voltage transistor region and the high voltage transistor region be substantially the same. The alignment of the heights is realized, for example, by adjusting the etching depth d1 and the thickness of the first gate insulating film 120.

  Then, as shown in FIG. 12, the peripheral gate electrode film 140 and the peripheral cover film 150 are formed on the second gate insulating film 130. For example, polycrystalline silicon is used for the peripheral gate electrode film 140. For the peripheral cover film 150, for example, a silicon nitride film is used.

  Then, as shown in FIG. 13, a mask pattern (not shown) is formed, and the peripheral cover film 150 and the peripheral gate electrode film 140 in the low-voltage and high-voltage transistor regions are etched by RIE. By this processing, as shown in FIG. 13A, the peripheral cover film 150 and the peripheral gate electrode film 140 in the memory cell region are removed. Note that the second gate insulating film 130 in a region where the memory cell MC is formed may be removed by etching.

  Then, as shown in FIG. 14, a first memory gate insulating film 160 is formed. The first memory gate insulating film 160 is, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a hafnium oxide film, a hafnium nitride film, a hafnium oxynitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or these Are used.

  Then, as shown in FIG. 15, a charge storage film 170, a second memory gate insulating film 180, and a cell array cover film 190 are formed on the first memory gate insulating film 160. As the charge storage film 170, for example, a silicon film, a silicon nitride film, or the like is used.

  The second memory gate insulating film 180 is, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a hafnium oxide film, a hafnium nitride film, a hafnium oxynitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or these Are used. The second memory gate insulating film 180 may contain other metal elements. As the cell array cover film 190, for example, a silicon nitride film is used.

  Here, it is preferable that the upper end of the second memory gate insulating film 180 in the memory cell region and the upper end of the peripheral gate electrode film 140 in the low-voltage and high-voltage transistor regions are formed at substantially the same height. This height can be made uniform by adjusting, for example, d2 which is the depth of etching and the thickness of the peripheral gate electrode film 140.

  Then, as shown in FIG. 16, a desired mask pattern is formed, and the cell array cover film 190 other than the memory cell region, the second memory gate insulating film 180, the charge storage film 170, and the first memory gate insulating film 160 are formed by RIE. Is etched. By this processing, the cell array cover film 190, the second memory gate insulating film 180, the charge storage film 170, and the first memory gate insulating film 160 in the low voltage and high voltage transistor regions are removed.

  Here, it is desirable that the heights of the upper ends of the peripheral cover film 150 in the low-voltage and high-voltage transistor regions and the cell array cover film 190 in the memory cell region are substantially the same. This is realized, for example, by adjusting the etching process described above, the film thickness of the peripheral cover film 150, and the film thickness of the cell array cover film 190.

  Then, as shown in FIG. 17, an element isolation region STI is formed.

  A mask pattern is formed on the peripheral cover film 150 and the cell array cover film 190 by lithography. Using the mask pattern as a mask material, the semiconductor substrate 100 is etched to a predetermined depth by RIE. Thereafter, an element isolation film 200 is formed. By planarization by CMP (Chemical Mechanical Polishing) using the peripheral cover film 150 and the cell array cover film 190 as stoppers, the excess element isolation film 200 is removed and planarization is performed. Thereby, an element isolation region STI is formed.

  The element isolation region STI is formed in a stripe shape parallel to the column direction described above with reference to FIG. 4 in the memory cell region. Further, as shown in FIG. 17, an element isolation region STI is formed in the low voltage and high voltage transistor regions.

  Then, as shown in FIG. 18, the element isolation film 200 is etched to a predetermined depth by selective etching using RIE. As shown in FIG. 18, it is desirable to remove the element isolation film 200 in the recess 105 formed in the memory cell region.

  Then, as shown in FIG. 19, the peripheral cover film 150 and the cell array cover film 190 are removed using, for example, hot phosphoric acid. Thereafter, a conductive film 210 is formed. If necessary, planarization by CMP may be performed.

  For the conductive film 210, for example, silicon, titanium, titanium nitride, tungsten, tungsten nitride, or a stacked film thereof is used.

  Then, as shown in FIG. 20, a cover film 220 is formed on the conductive film 210. The cover film 220 is, for example, a silicon nitride film.

  Then, the gate electrode of the transistor is processed. Here, as an example, a method of separately processing the memory cell MC, the selection transistor, and the peripheral circuit transistor will be described.

  First, as shown in FIG. 21, the memory cell MC is processed.

  A mask pattern is formed on the cover film 220 by a lithography method or the like. Etching is performed by RIE using this mask pattern as a mask. By this processing, the cover film 220, the conductive film 210, the second memory gate insulating film 180, the charge storage film 170, and the first memory gate insulating film 160 are etched. Thereafter, an impurity element is implanted by an implantation method to form the first impurity diffusion layer 230.

  Note that the second gate insulating film 130 may be etched during the etching process. Further, if necessary, a mask material may be formed on the cover film 220 and a mask pattern may be formed on the mask material. In this case, the mask material may be lost during the etching process, or may remain.

  Note that when the impurity element is implanted, a mask may be formed in advance by a lithography method or the like, and the impurity element may be divided into regions. In FIG. 21, the first impurity diffusion layer 230 is illustrated without distinction.

  Then, as shown in FIG. 22, an insulating film 240 with poor coverage is formed on the cover film 220, and a gap 245 is formed. As the insulating film 240, a silicon oxide film or a silicon nitride film is formed by a sputtering method or a PECVD (Plasma-Enhanced Chemical Vapor Deposition) method under film forming conditions with poor coverage. Note that a mask material may be formed over the insulating film 240 as a mask material when processing a transistor and a selection transistor in a peripheral circuit portion to be described later.

  Then, as shown in FIG. 23, low voltage and high voltage transistors are processed. A mask pattern is formed on the insulating film 240 by lithography. Using this mask pattern as a mask, the insulating film 240, the cover film 220, the conductive film 210, and the peripheral gate electrode film 140 are etched by RIE. Note that the second gate insulating film 130 and the first gate insulating film 120 may be processed. Further, an impurity element may be implanted by an implantation method.

  Then, as shown in FIG. 24, the selection transistor is processed.

  A mask pattern is formed using a lithography method. Using this mask pattern as a mask, the insulating film 240, the cover film 220, the conductive film 210, the second memory gate insulating film 180, the charge storage film 170, and the first memory gate insulating film 160 are etched by RIE. Note that the second gate insulating film 130 may be processed. Further, after the processing, an impurity element may be implanted by an implantation method.

  As shown in FIG. 24, this selection transistor needs to be processed deeper between the source line side selection transistors SS than between the bit line side selection transistors SB. This etching process can be realized, for example, by performing etching in the middle of the etching under conditions that allow a selection ratio between the conductive film 210 and the second memory gate insulating film 180 to be obtained.

  That is, when the etching process between the bit line side selection transistors SB reaches the second memory gate insulating film 180, the etching rate between the bit line side selection transistors SB becomes slow, and only the processing between the source line side selection transistors SS is performed. Can proceed. Then, after the etching process between the source line side select transistors SS reaches the second memory gate insulating film 180, the second memory gate insulating film 180 may be switched to a condition where the etching rate is high.

  Then, as shown in FIG. 25, a spacer film is formed, and then etched back by RIE to form spacers (sidewalls) 270. Further, the second impurity diffusion layer 260 is formed by implanting an impurity element by an implantation method.

  Note that the region between the spacer 270 of the bit line side select transistor SB (1) and the spacer 270 of the bit line side select transistor SB (2), the source line side select transistor, as shown in FIG. In the region between the spacer 270 of SS (1) and the spacer 270 of the source line side select transistor SS (2) and the low voltage transistor region, the semiconductor substrate 100 is etched. On the other hand, in the high voltage transistor region, the second gate insulating film 130 and the first gate insulating film 120 are etched. By this etching process, the recess 105 has a deeper region (first region) and a second region shallower than the first region.

  As the spacer film, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof is used. When the impurity element is implanted, the impurity element may be divided into regions by forming a mask in advance by a lithography method or the like. In FIG. 25, the second impurity diffusion layer 260 is illustrated without being distinguished.

  Then, as shown in FIG. 26, a stopper film 280 is formed. As the stopper film 280, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof is used.

  Then, as shown in FIG. 27, a first interlayer insulating film 290 is formed and planarized by CMP as necessary. For example, a silicon oxide film is used for the first interlayer insulating film 290.

  Then, as shown in FIG. 28, a resist pattern is formed on the first interlayer insulating film 290 by lithography. Using this resist pattern as a mask, the first interlayer insulating film 290 is etched by RIE so as to reach the stopper film 280. By this processing, a source line contact trench 300 and a bit line contact hole 310 are formed. At the same time, contact holes (not shown) for the source and drain regions of the low-voltage and high-voltage transistors may be formed.

  As described with reference to FIG. 4, the source line contact trench is formed in a line shape in the row direction. On the other hand, the bit line contact CB is formed in an elliptical shape for each bit line, for example. That is, the source line contact trench 300 has a larger area than the bit line contact hole 310 in plan view as viewed from above the substrate.

  Here, in the RIE of the fine hole or trench pattern, the etching rate is higher in the region where the area of the opening is large than in the narrow region. This can be explained, for example, by the fact that the etchant in RIE easily reaches the bottom of the hole or trench in the region having a large area, while the etchant hardly reaches the bottom of the hole or trench in the narrow region.

  Therefore, when the source line contact trench 300 and the bit line contact hole 310 are etched simultaneously, the source line contact trench 300 has a higher etching rate. In the present embodiment, a step due to the recess 105 is formed in the semiconductor substrate 100 between the source line side select transistors SS. That is, the semiconductor substrate 100 in the region where the source line contact trench 300 is formed is provided lower than the semiconductor substrate 100 in the region where the bit line contact hole 310 is formed. That is, the etched film formed with the source line contact trench 300 is thicker than the bit line contact hole 310.

  Due to the level difference of the recess 105, the bit line contact hole 310 and the source line contact trench 300 both have the same level of the first interlayer insulating film 290 (stopper) even though the etching speed of the source line contact trench is high. Until it reaches the film 280).

  If the recess 105 is not provided, if the bit line contact hole 310 is etched so as to reach the stopper film 280, the source line contact trench 300 penetrates the stopper film 280, and the second of the semiconductor substrate 100 is formed. There is a possibility of penetrating the impurity diffusion layer 260. When penetrating through the second impurity diffusion layer 260, the junction leakage current increases and the leakage current may increase.

  25, the semiconductor substrate 100 between the spacer 270 of the bit line side select transistor SB (1) and the bit line side select transistor SB (2) is etched. . Therefore, the bit line contact CB is provided in contact with the bottom at a position lower than the semiconductor substrate 100 in the region where the cell transistor is formed.

  Thereafter, as shown in FIG. 29, a mask pattern is formed on the first interlayer insulating film 290, and the first interlayer insulating film 290 is etched by RIE. By this processing, a first wiring trench 320 and a first wiring hole 325 are formed.

  Then, as shown in FIG. 30, a lower layer contact material is formed, and unnecessary contact material is removed while planarizing by CMP. Thereby, the bit line contact CB, the source line contact SLC, the first wiring 335, and the first wiring contact 333 are formed. The lower layer contact material includes, for example, a metal film and a barrier metal layer. For the metal film, tungsten, copper, aluminum, or the like is used. As the barrier metal layer, for example, titanium, tantalum, titanium nitride, tantalum nitride, or a laminate thereof is used.

  Then, as shown in FIG. 31, a second interlayer insulating film 340 is formed. A mask pattern is formed on the second interlayer insulating film 340 and etched by RIE to form an upper contact hole. Then, an upper layer contact material is formed, an unnecessary upper layer contact material is removed by CMP, and an upper layer contact 350 is formed.

  Thereafter, various wiring layers and circuit elements are formed using a general manufacturing method. In this way, the semiconductor memory device of this embodiment is manufactured.

  According to the semiconductor memory device of this embodiment, as shown in FIG. 5, a part of the region where the source line side select transistors SS (1) and SS (2) are formed, and the source line side select transistor SS. In the region between (1) and the source line side select transistor SS (2), a recess 105 is provided in the semiconductor substrate 100.

  By providing the recess 105 in the semiconductor substrate 100, the source line side select transistor SS is formed by bending the gate electrode, the gate insulating film, and the channel region. That is, a transistor with a long channel length can be formed as compared with a case where a transistor with a flat gate electrode is formed. That is, it is possible to form a selection transistor with a long channel length and better controllability.

  Further, as described above in the manufacturing method, the source line contact SLC and the bit line contact CB can be processed while simultaneously suppressing the problem.

  As shown in FIG. 28, since the recess 105 is provided in the semiconductor substrate 100, the semiconductor substrate 100 under the source line contact trench 300 is provided lower than the bit line contact hole 310. Therefore, even if the source line contact trench 300 has a larger area than the bit line contact hole 310 and the etching rate is high, the stopper film 280 prevents the bit line contact hole 310 and the source line contact trench 300 from forming. Both can stop processing.

  If the recess 105 is not provided, over-etching of the source line contact trench 300 occurs, and there is a concern that junction leakage increases between the source line contact SLC and the second impurity diffusion layer 260.

  Furthermore, according to the present embodiment, the recess 105 can be formed without adding a new process.

  As shown in FIG. 8, it is desirable to lower the semiconductor substrate 100 in the low voltage and high voltage transistor regions by etching. This is because, for example, in order to avoid the problem that the remaining of the element isolation film 200 occurs in the CMP at the time of forming the element isolation region STI shown in FIG. 17, the cell array cover film 190 and the peripheral cover film 150 are separated from the semiconductor substrate. This is because it is better to align the heights. Therefore, the semiconductor substrate 100 in the low-voltage and high-voltage transistor regions needs to be formed low in advance according to the film thickness to be formed in each region.

  Simultaneously with the etching of the semiconductor substrate 100 in the region where the low-voltage and high-voltage transistors are to be formed, the semiconductor substrate 100 can be etched as shown in FIG. As a result, the recess 105 can be formed without adding a new process. The formation of the recess 105 may be performed as a separate process.

  Hereinafter, modified examples will be described. 32A to 34B, FIG. 4A is a cross section taken along the line AA ′ in FIG. 4 (column direction), FIG. 4B is a cross section of the low voltage transistor in the peripheral circuit portion, and FIG. ) Shows a cross section of the high voltage transistor in the peripheral circuit section. 32 to 34 are different in aspect ratio from FIG. 5 for convenience of explanation.

  As a first modification, as shown in FIG. 32, a case where etching for forming the recess 105 and etching of the semiconductor substrate 100 in the high voltage transistor region of FIG. 7 are simultaneously performed is shown.

  In this case, the recess 105 may or may not be etched to simultaneously process the semiconductor substrate 100 in the memory cell region, the low voltage transistor region, and the high voltage transistor region. FIG. 33 shows the case where the etching process is not performed, and FIG. 34 shows the case where the etching process is performed.

  When etching is performed, the recess 105 can be formed deeper as shown in FIG. This is useful when the etching rate of the source line contact trench is faster than that of the bit line contact hole. Alternatively, the controllability of the source line side select transistor can be further improved.

  A second modification will be described. In the present embodiment, the case where the peripheral circuit includes the low voltage transistor and the high voltage transistor has been described. However, it does not matter if either one of the transistors is provided. In this case, the recess 105 may be formed simultaneously with the etching for lowering the semiconductor substrate 100 in the region where the transistor is to be formed in the memory cell region.

  A third modification will be described. The recess 105 of the semiconductor substrate 100 is not limited to a partial region between the source line side select transistors SS and below the gate electrode of the source line side select transistor SS.

  In order to easily form the bit line contact hole and the source line contact trench at the same time, it is sufficient that the recess 105 is formed on the lower side of the source line contact trench. That is, the recess 105 may be formed between the source line side select transistors SS or only on the contact surface between the source line contact trench and the semiconductor substrate 100.

  Conversely, the recess 105 can be widened. In this case, it is desirable not to overlap the region under the gate electrode of the dummy memory cell transistor. This is because there are concerns about adverse effects such as variations in the characteristics of the cell transistors.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope equivalent to the invention described in the claims.

DESCRIPTION OF SYMBOLS 5 ... Semiconductor memory device 7 ... Peripheral circuit 10 ... Memory cell array 15 ... Word line driver 20 ... Sense amplifier circuit 25 ... Column decoder 30 ... Input / output control circuit 35 ... Data input / output buffer 40 ... Address decoder 45 ... Controller 50 ... Control voltage Generating circuit 55... Parameter storage unit 100... Semiconductor substrate 105. Recess 110. Sacrificial oxide film 120... First gate insulating film 130 ... Second gate insulating film 140 ... Peripheral gate electrode film 150 ... Peripheral cover film 160 ... First memory gate Insulating film 170 ... Charge storage film 180 ... Second memory gate insulating film 190 ... Cell array cover film 200 ... Element isolation film 210 ... Conductive film 220 ... Cover film 230 ... First impurity diffusion layer 240 ... Insulating film 260 ... Second impurity diffusion Layer 270 ... Spacer 280 ... Stopper film 290 ... first interlayer insulating film 300 ... source line contact trench 310 ... bit line contact hole 320 ... first wiring trench 340 ... second interlayer insulating film 350 ... upper layer contact

Claims (9)

A semiconductor substrate having a recessed region formed recessed on the surface lower than the periphery;
A plurality of first cell transistors formed above the semiconductor substrate and connected in series;
A plurality of second cell transistors formed above the semiconductor substrate and connected in series;
A plurality of third cell transistors formed above the semiconductor substrate and connected in series;
Two source line side select transistors formed between the first cell transistor and the second cell transistor;
Two bit line side select transistors formed between the first cell transistor and the third cell transistor;
A source line contact formed between the two source line side select transistors and provided in contact with a bottom of the semiconductor substrate in the recess region;
And a bit line contact formed between the two bit line side select transistors and provided in contact with the semiconductor substrate at a position higher than the bottom of the source line contact.   The semiconductor memory device according to claim 1, wherein the recessed region is provided between the first cell transistor and the second cell transistor.   2. The semiconductor memory according to claim 1, wherein the recessed region is integrally provided in a region below a gate electrode of the two source line side select transistors and a region between the two source line side select transistors. apparatus. The recessed area has a first area and a second area,
The first region is provided deeper than the second region,
The source line contact is provided with a bottom portion in contact with the semiconductor substrate of the first region.
The semiconductor memory device according to claim 1. Each of the two source side selection transistors includes a sidewall,
The first region is provided between the sidewalls,
The semiconductor memory device according to claim 4.   The semiconductor memory device according to claim 1, wherein the bit line contact is provided at a position lower than the semiconductor substrate on which the first cell transistor is provided, with a bottom portion in contact therewith. Forming a recessed region formed on the surface lower than the surroundings above the semiconductor substrate,
Forming a plurality of adjacent first cell transistor gate electrodes, a plurality of adjacent second cell transistor gate electrodes, and a plurality of adjacent third cell transistor gate electrodes above the semiconductor substrate;
Two source line side select transistor gate electrodes disposed between the first cell transistor gate electrode and the second cell transistor gate electrode, and between the first cell transistor gate electrode and the third cell transistor gate electrode Forming two arranged bit line side select transistor gate electrodes;
Forming a source line contact trench disposed between the two source line side select transistor gate electrodes and a bit line contact hole disposed between the two bit line side select transistor gate electrodes;
A method for manufacturing a semiconductor memory device, comprising:
The plurality of first cell transistor gate electrodes and the plurality of second cell transistor gate electrodes are formed across the recessed region,
The two source line side select transistor gate electrodes are formed across the recessed region,
The source line contact trench is formed on the recessed region,
The bit line contact hole is formed at a position higher than the bottom of the source line contact trench.
Manufacturing method of semiconductor memory device.   8. The semiconductor memory according to claim 7, wherein the formation of the recessed area is formed simultaneously with the selective etching process for the semiconductor substrate in an area where a transistor of the peripheral circuit section is formed in the peripheral circuit section of the semiconductor memory device. Device manufacturing method.   The recess region is formed selectively in the peripheral circuit portion including at least two types of peripheral transistors having different thicknesses of the gate insulating film of the semiconductor memory device with respect to the semiconductor substrate in a region where one of the peripheral transistors is formed. The method of manufacturing a semiconductor memory device according to claim 7, wherein the method is formed simultaneously with an etching process.

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