JP2011138945A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of enhancing recording density while suppressing the number of stacked memory cells as compared with before. <P>SOLUTION: The nonvolatile semiconductor memory device includes memory strings MS, in which a plurality of transistors, including charge storage layers 133 formed over side surfaces of columnar semiconductor films 131 and gate electrode films 134 formed over the charge storage layers 133, are provided in a height direction of the semiconductor films 131, and which are arranged in a matrix shape substantially perpendicularly above a semiconductor substrate 101. In the nonvolatile semiconductor memory device, the gate electrode films 134 of the transistors at same height of the memory strings MS arranged in a first direction are connected to one another, and a distance, between the semiconductor films 131 at least in a position in which the transistor is formed at an uppermost layer in the memory strings MS adjacent to each other in the first direction, is smaller than double of thickness of the charge storage layers 133. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In the field of NAND flash memory, a stacked memory that can achieve high integration without being restricted by the resolution limit of lithography technology has attracted attention. For example, there are two memory strings in which a plurality of plate-like electrodes are arranged at predetermined intervals in the height direction so as to intersect a columnar semiconductor film in which an insulating film as a charge storage layer is formed so as to cover the side surface. A non-volatile semiconductor memory device having a structure in which planar electrodes are shared between memory strings that are arranged in a matrix in dimension and adjacent in a predetermined direction has been proposed (for example, see Patent Document 1).

  Such a nonvolatile semiconductor memory device is manufactured as follows. First, on a semiconductor substrate on which a peripheral circuit is formed, a plurality of layers of a polycrystalline silicon film to which a conductive impurity serving as a control gate is added and a silicon oxide film serving as an insulating film between the control gates are alternately stacked. Next, a memory plug hole is formed so as to penetrate the laminated film composed of the polycrystalline silicon film and the silicon oxide film. Then, an ONO film is formed only on the inner wall of the memory plug hole, an amorphous silicon layer is formed so as to fill the memory plug hole, and finally crystallized to obtain a nonvolatile semiconductor memory device having the above structure. It is done.

  As described above, in the conventional method, the columnar amorphous silicon layer must be formed after the ONO film is formed in the memory plug hole formed in the laminated film of the polycrystalline silicon film and the silicon oxide film. For this reason, there is a problem in that a flat electrode is inserted between adjacent memory strings in the direction in which the electrodes are shared, and it is difficult to reduce the distance between the adjacent columnar amorphous silicon layers. . As described above, the arrangement of memory cells on a plane is limited, and there is a limit to reducing the cell area. Therefore, in order to increase the storage density, the number of stacked polycrystalline silicon layers must be increased. For example, when the target of the half pitch is 20 nm, the half pitch of 65 to 50 nm is the limit of miniaturization in the conventional structure, so that the number of stacked polycrystalline silicon layers is 10 or more.

JP 2008-171918 A

  According to the present invention, memory strings in which a plurality of gate electrode films intersecting a columnar semiconductor film having gate dielectric films formed on the side surfaces are arranged in a height direction are two-dimensionally arranged in a matrix, and in a predetermined direction. Provided is a nonvolatile semiconductor memory device capable of increasing the memory bit density while suppressing the number of stacked memory cells as compared with the conventional nonvolatile semiconductor memory device having a structure in which adjacent gate electrode films of the same height are connected. The purpose is to do.

  According to one embodiment of the present invention, a transistor including a gate dielectric film formed on a side surface of a columnar semiconductor film and a gate electrode film formed on the gate dielectric film is formed in a height direction of the semiconductor film. A non-volatile semiconductor in which a plurality of memory strings are arranged in a matrix substantially vertically on a substrate, and the gate electrode films of the transistors having the same height of the memory strings arranged in a first direction are connected In the memory device, a distance between the semiconductor films in at least the uppermost layer of the memory strings adjacent in the first direction is less than twice the thickness of the gate dielectric film. A nonvolatile semiconductor memory device is provided.

  According to the present invention, memory strings in which a plurality of gate electrode films intersecting a columnar semiconductor film having gate dielectric films formed on side surfaces are arranged in a height direction are two-dimensionally arranged in a matrix, In the nonvolatile semiconductor memory device having a structure in which gate electrode films of the same height adjacent in the direction are connected, the memory bit density can be increased while the number of stacked memory cells is reduced as compared with the conventional case.

FIG. 1 is a perspective view schematically showing an example of the structure of a nonvolatile semiconductor memory device. FIG. 2A is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the first embodiment (part 1). FIG. 2-2 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the first embodiment (part 2). FIG. 3 is a perspective view of a part of a region where the memory cell transistor of the memory cell portion is formed. FIGS. 4-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 1). FIG. 4B is a sectional view schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 2). FIGS. 4-3 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 3). FIGS. 4-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 4). FIGS. 4-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 5). FIGS. 4-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 6). FIGS. 4-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 7). FIGS. 4-8 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 8). 4-9 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 9). 4-10 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 10). FIG. 5A is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the second embodiment (part 1). FIG. 5-2 is a sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the second embodiment (No. 2). FIGS. 6-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 1). FIG. 6B is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment (No. 2). 6-3 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 3). 6-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 4). 6-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 5). 6-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 6). 6-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 7). 6-8 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 8). 6-9 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 9). 6-10 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 10). FIG. 7 is a cross-sectional view schematically showing an example of the structure of the memory cell of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 8 is a diagram illustrating an example of a semiconductor film arrangement method. FIG. 9 is a diagram showing an example of a scaling scenario of the nonvolatile semiconductor memory device having the structures of the first and second embodiments. FIG. 10 is a perspective view of a part of the memory cell portion and the word line contact portion of the nonvolatile semiconductor memory device according to the fourth embodiment. FIG. 11A is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the fourth embodiment (part 1). FIG. 11-2 is a sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the fourth embodiment (No. 2). FIG. 12A is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 1). FIG. 12-2 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 2). FIG. 12C is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 3). 12-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 4th Embodiment (the 4). 12-5 is a sectional view schematically showing an example of a procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 5). FIG. FIG. 12-6 is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 6). FIG. 12-7 is a sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 7). FIG. 12-8 is a sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment (No. 8). FIG. 13 is a partial perspective view schematically showing the state of the memory cell portion and the word line contact portion in a state where the charge storage layer and the gate electrode film are formed on the semiconductor film. FIG. 14A is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the fifth embodiment (part 1). FIG. 14-2 is a sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the fifth embodiment (part 2). FIG. 15A is a cross-sectional view schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment (No. 1). FIGS. 15-2 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 5th Embodiment (the 2). FIG. 15C is a cross-sectional view schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment (No. 3). 15-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 5th Embodiment (the 4). FIG. 15-5 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment (No. 5). FIG. 15-6 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment (No. 6). 15-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 5th Embodiment (the 7). FIG. 15-8 is a sectional view schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment (No. 8). FIG. 15-9 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment (No. 9).

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. In addition, the perspective view and cross-sectional view of the nonvolatile semiconductor memory device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thickness of each layer, and the like are actual. Different. Furthermore, the film thickness shown below is an example and is not limited thereto.

  In the following embodiments, a SGT (Surrounding Gate Transistor) type having a semiconductor film as a channel provided in a columnar shape perpendicular to a substrate and a gate electrode film provided on a side surface of the semiconductor film via a charge storage layer is provided. The present invention is applied to a nonvolatile semiconductor memory device having a structure in which a plurality of memory cells (transistors) are provided in the height direction. Therefore, an example of the overall structure of such a nonvolatile semiconductor memory device will be described first, and then each embodiment will be described.

  FIG. 1 is a perspective view schematically showing an example of the structure of a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device 1 includes a memory cell unit 11, a word line driving circuit 12, a source side selection gate line driving circuit 13, a drain side selection gate line driving circuit 14, a sense amplifier 15, a word line 16, and a source side selection gate line. 17, a drain side select gate line 18, a bit line 19, and the like.

  The memory cell unit 11 includes a memory string having a plurality of memory cell transistors (hereinafter also simply referred to as memory cells) and a drain side selection transistor and a source side selection transistor provided at the upper end and lower end of the memory cell transistor row, respectively. It has a configuration arranged in a matrix on the top. As will be described later, the memory cell transistor has a structure in which a control gate electrode is provided on a side surface of a columnar semiconductor film serving as a channel via a charge storage layer. The drain side selection transistor and the source side selection transistor are formed in a columnar shape. A selection gate electrode is provided on a side surface of the semiconductor film via a charge storage layer as a gate dielectric film. Here, a case where four layers of memory cells are provided in one memory string is illustrated.

  The word line 16 connects between control gate electrodes of memory cells having the same height in adjacent memory strings in a predetermined direction. Hereinafter, the extending direction of the word line 16 is referred to as a word line direction. The source side select gate line 17 connects the select gate electrodes of the source side select transistors of the memory strings adjacent in the word line direction, and the drain side select gate line 18 is the drain of the memory strings adjacent in the word line direction. The selection gate electrodes of the side selection transistors are connected. Further, the bit line 19 is provided so as to be connected to the upper portion of each memory string in a direction intersecting the word line direction (here, an orthogonal direction). Hereinafter, the extending direction of the bit line 19 is referred to as a bit line direction.

  The word line driving circuit 12 is a circuit that controls the voltage applied to the word line 16, and the source side selection gate line driving circuit 13 is a circuit that controls the voltage applied to the source side selection gate line 17, and is on the drain side. The selection gate line driving circuit 14 is a circuit that controls a voltage applied to the drain side selection gate line 18. The sense amplifier 15 is a circuit that amplifies the potential read from the selected memory cell. In the following description, when there is no need to distinguish between the source-side selection gate line 17 and the drain-side selection gate line 18, they are simply referred to as selection gate lines. In addition, when there is no need to distinguish between the source side selection transistor and the drain side selection transistor, they are simply expressed as selection transistors.

  The word line 16, the source side selection gate line 17 and the drain side selection gate line 18 of the memory cell unit 11, and the word line driving circuit 12, the source side selection gate line driving circuit 13 and the drain side selection gate line driving circuit 14 are: The word line contact portions 20 provided in the memory cell portion 11 are connected via contacts. The word line contact part 20 is provided on the word line driving circuit 12 side of the memory cell part 11, and the word line 16 and the selection gate lines 17 and 18 connected to the memory cells and selection transistors at respective heights are stepped. It has a processed structure.

(First embodiment)
FIGS. 2-1 to 2-2 are sectional views schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 2-1A is a plan view of the memory cell portion. FIG. 2-1 (b) is a cross-sectional view taken along line AA in FIG. 2A, FIG. 2-1 (c) is a cross-sectional view taken along line BB in FIG. 2A, and FIG. It is sectional drawing of the direction perpendicular | vertical to the bit line direction of a word line contact part. FIG. 2-1 (a) corresponds to the CC cross section of FIGS. 2-1 (b) and (c). FIG. 3 is a perspective view of a part of a region where the memory cell transistor of the memory cell portion is formed.

  As shown in FIGS. 2A to 2C, the memory cell unit 11 includes a memory cell MC in which a gate electrode film 134 is formed on a side surface of a columnar semiconductor film 131 via a charge storage layer 133. Are arranged in a matrix substantially vertically on the semiconductor substrate 101 on which the source region 111 is formed. Here, it is assumed that the columnar semiconductor film 131 is made of a P-type semiconductor material such as P-type polycrystalline silicon.

  The memory string MS has a structure in which a plurality of transistors each having a structure in which a gate electrode film 134 is formed on a side surface of a columnar semiconductor film 131 via a charge storage layer 133 are connected in series in the height direction. Of these, the transistors at the upper and lower ends are selection transistors. 2B and 2C, the source side select transistor SGS is disposed on the lower side, and the drain side select transistor SGD is disposed on the upper side. One or more memory cell transistors MC are formed between these two select transistors SGS and SGD with a predetermined interval. As described above, in the first embodiment, the selection transistors SGS and SGD have the same structure as the memory cell transistor MC. A drain region 112 is formed at the upper end of the memory string MS. Further, in the memory cell unit 11, the select gate electrodes of the select transistors SGS and SGD of the memory string MS arranged in a predetermined direction are connected to each other, and the memory cell transistors MC of the same height of the memory string MS arranged in the predetermined direction are connected. These control gate electrodes are also connected to each other. In the following description, the gate electrode film 134 is used when it is not necessary to distinguish between the control gate electrode and the selection gate electrode.

  Specifically, as illustrated in FIG. 2C, a spacer film 121 surrounding the semiconductor film 131 is disposed at a predetermined interval in the height direction on the side surface of the columnar semiconductor film 131 functioning as a channel. The charge storage layer 133 covers the side surface of the columnar semiconductor film 131 including the spacer film 121, and the charge storage layer 133 is formed on the side surface of the columnar semiconductor film 131 in a region sandwiched between the upper and lower spacer films 121. Through this, a gate electrode film 134 is formed. Here, a region sandwiched between the upper and lower spacer films 121 in which the gate electrode film 134 is formed on the side surface of the columnar semiconductor film 131 via the charge storage layer 133 functions as one transistor. Transistors disposed at both upper and lower ends of the memory string MS are selection transistors SGS and SGD, and one or more transistors sandwiched between the two selection transistors SGS and SGD are memory cell transistors MC. Here, a case where four memory cell transistors MC are formed between two select transistors SGS and SGD is shown.

  As shown in FIG. 2B, a gate electrode film 134 extending from the memory cell unit 11 is stacked on the word line contact unit 20. The gate electrode film 134 has a stepped configuration so that the lower gate electrode film 134 is exposed. In the word line contact portion 20, the periphery of the gate electrode film 134 is surrounded by the charge storage layer 133, and a spacer film is interposed between the gate electrode films 134 surrounded by the charge storage layers 133 adjacent in the vertical direction. 121 is formed.

A planarization film 141 is formed on the stepped gate electrode film 134 in the word line contact portion 20, and on the memory strings MS of the memory cell portion 11, on the planarization film 141 of the word line contact portion 20, and the bit line. An interlayer insulating film 143 is formed between the memory strings MS adjacent in the direction. As the planarizing film 141, for example, a silicon oxide film can be used, and as the interlayer insulating film 143, for example, a TEOS (Tetraethyl orthosilicate) / O ₃ film can be used.

  On the interlayer insulating film 143, a multilayer wiring layer having a bit line, a source side selection gate line, a drain side selection gate line, and the like is formed. Here, a wiring layer 151, an interlayer insulating film 161, a wiring layer 152, an interlayer insulating film 162, a wiring layer 153, and an interlayer insulating film 163 are sequentially formed on the interlayer insulating film 143. The wiring layer 151 is connected to the upper surface of each memory string MS of the memory cell unit 11 and the gate electrode film 134 of the word line contact unit 20 by a contact 145. As a material of the contact 145 and the wiring layers 151 to 153, for example, W or Al can be used.

  Here, the material of the semiconductor substrate 101 and the columnar semiconductor film 131 can be selected from, for example, Si, Ge, SiGe, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or InGaAsP. The columnar semiconductor film 131 may be formed of a single crystal semiconductor or a polycrystalline semiconductor.

Further, as the charge storage layer 133, one having a tunnel insulating film / charge trap film / charge block film structure can be used. For example, an ONO (silicon oxide film / silicon nitride film / silicon oxide film) structure is used. Alternatively, an ANO (aluminum oxide film / silicon nitride film / silicon oxide film) structure may be used. Alternatively, instead of an aluminum oxide film having an ANO structure, a metal oxide film such as HfO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , or a combination of such metal oxide films is used. A film may be used. In these structures, an ONO film may be used as the tunnel insulating film.

Further, as the material of the gate electrode film 134, for example, W, TaN, TiN, TiAlN, WN, WSi, CoSi, NiSi, PrSi, NiPtSi, PtSi, Pt, Ru, RuO ₂ , B-doped polycrystalline silicon film, P-doped poly-silicon film A conductor film such as a crystalline silicon film can be used alone or in a stacked manner. Further, as the material of the spacer film 121, for example, a silicon oxide film or an organic film may be used.

  In the first embodiment, as shown in FIG. 3, the gate electrode is formed between transistors at the same height of the memory strings MS adjacent to each other in the word line direction. The charge storage layer 133 has a shape that intersects between adjacent transistors so that the film 134 is not inserted. Specifically, in the transistor sharing the gate electrode film 134, at least the charge storage layer 133 of the uppermost transistor is partly shared with adjacent memory cell transistors.

In order to achieve such a structure, the memory strings MS (semiconductor film 131) are arranged so that the following equation (0) is satisfied at the transistor formation position in the uppermost layer of the memory strings MS adjacent in the word line direction. . However, the distance between adjacent semiconductor films 131 (channels) is L, the thickness of the tunnel insulating film 133A is t _TNL , the thickness of the charge trap film 133B is t _CT, and the thickness of the charge block film 133C is t _CB .
L <(t _TNL + t _CT + t _CB ) × 2 (0)

In the structure satisfying the expression (0), at least two adjacent transistors in the uppermost layer have a merge structure in which a part of the charge block film 133C intersects, and therefore, between the semiconductor films 131 adjacent in the word line direction. Can close the distance. Note that further miniaturization can be realized by crossing up to the charge trap film 133B between adjacent transistors. However, if the charge trap film 133B is crossed, the charge stored in the charge trap film 133B can be realized. However, there is a possibility of leakage to adjacent transistors through the intersecting portion, which is not preferable. For this reason, the distance L between adjacent semiconductor films 131 is preferably set so as to satisfy the following expression (1).
L> (t _TNL + t _CT ) × 2 (1)

  In this structure, since the charge storage layer 133 is covered on the side surface of the columnar semiconductor film 131, the radius of curvature is different between the tunnel insulating film 133A and the charge block film 133C. Therefore, since the electric field can be concentrated more strongly by the tunnel insulating film 133A having a small curvature radius, the write / erase characteristics can be greatly improved as compared with the planar MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure. In addition, it is effective to perform MLC (Multi-Level Cell) operation.

In the above description, the semiconductor film 131 is a P-type polycrystalline silicon film, and a stacked memory to which an Inversion type transistor is connected is used. The Inversion type is a transistor that forms a channel by connecting depletion layers formed by applying a voltage to each gate electrode. Since there are no electrons in the channel, programming is possible even when V _pass is applied to a non-selected cell. Malfunction due to disturb and read disturb is unlikely to occur. In addition, since the semiconductor film 131 serving as a channel is P ⁻ type, holes can be easily drawn from the semiconductor substrate 101 during erasing, so that the erasing characteristics are good. Further, as will be described later, different selection transistors are not required unlike the case of the depletion type. Note that in the above description, the semiconductor film 131 can be formed of an N-type polycrystalline silicon film and driven as a Depletion-type transistor. However, in this case, in order to make the selection transistors SGS, SGD arranged above and below the memory cell MC row normally-off selection transistors, the channel portion is made of a P-type polycrystalline silicon film and an Inversion type. It is only necessary to drive as a transistor.

  Next, a method for manufacturing the nonvolatile semiconductor memory device having such a structure will be described. 4-1 to 4-10 are cross-sectional views schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. In these drawings, (a) shows a cross section in the word line direction, (b) shows a cross section in a direction perpendicular to the word line direction, and (c) is cut along the DD line in (a). (D) shows a cross-sectional plan view taken along line EE in (b), and (e) shows the word line direction of the word line contact portion. The cross section of is shown.

  First, a peripheral circuit (not shown) of the nonvolatile semiconductor memory device is formed on the semiconductor substrate 101. Further, as shown in FIG. 4A, a source region 111 is formed by implanting and activating an impurity of a predetermined conductivity type into the memory cell portion of the semiconductor substrate 101 by an ion implantation method. This source region 111 may be N-type, for example.

  Next, a plurality of spacer films 121 and sacrificial films 122 constituting memory cells are alternately stacked on the entire surface of the semiconductor substrate 101 by a film forming method such as PECVD (Plasma-Enhanced Chemical Vapor Deposition), and finally the spacer film 121 is stacked. End with. Further, a stopper film 123 serving as a stopper at the time of CMP (Chemical Mechanical Polishing) is formed on the uppermost spacer film 121 to form a laminated film. Here, the sacrificial film 122 is stacked so as to have six layers. As the sacrificial film 122, an insulating material having an etching rate larger than that of the spacer film 121 is selected by a later wet etching process. For example, a silicon oxide film can be used as the spacer film 121 and a silicon nitride film can be used as the sacrificial film 122. As the stopper film 123, for example, a silicon nitride film can be used. As a method for forming a laminated film, in addition to the PECVD method, a technique such as SACVD (Sub-Atmospheric CVD) method, LPCVD (Low Pressure CVD) method, sputtering method, Spin-On Dielectric (SOD) is appropriately combined. It is also possible to use it.

  Thereafter, as shown in FIG. 4B, a mask film (not shown) is formed on the entire surface of the stopper film 123, and spacers are formed by lithography technique and reactive ion etching technique (hereinafter referred to as RIE (Reactive Ion Etching) method). A laminated film composed of the film 121, the sacrificial film 122, and the stopper film 123 is processed at once, and a through hole 135 that embeds the semiconductor film 131 to be a channel later is formed in the memory cell portion. The through holes 135 are arranged in a matrix in the memory cell portion, and the bottom portion communicates with the semiconductor substrate 101. Here, for example, a CVD carbon film can be used as the mask film. Subsequently, the mask film is removed. Thereby, a template of the semiconductor film 131 is formed.

Next, as shown in FIG. 4C, a semiconductor film 131 to be a channel is formed by a film forming method such as an LPCVD method. At this time, the semiconductor film 131 is formed so as to be embedded in the through hole 135 and to be connected to the semiconductor substrate 101 at the lower end. Here, as the semiconductor film 131, for example, a B-doped polycrystalline silicon film can be used, and the B concentration at this time can be set to 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , for example. Note that the semiconductor film 131 may be formed so as to completely embed the through-hole 135 or may be formed so as to be embedded in a macaroni-like hollow. When embedded in the hollow, the thickness of the semiconductor film 131 controlled by the gate electrode film 134 is equal between the stacked memory cells MC, which is effective in suppressing variations in threshold voltage (Vth). . In the following description, a case where the through hole 135 is formed so as to be completely filled with the semiconductor film 131 is illustrated. In addition to the LPCVD method, a polycrystalline silicon film or a single crystal silicon film crystallized by laser annealing or a Ni catalyst method may be used as the semiconductor film 131.

  Thereafter, etch back is performed by the RIE method, and the semiconductor film 131 on the stopper film 123 is removed. As a result, the semiconductor film 131 remains only in the through hole 135. Subsequently, an impurity element having a predetermined conductivity type is ion-implanted into the upper portion of the semiconductor film 131 by using a lithography technique and an ion implantation technique, so that the drain region 112 is formed. Here, for example, arsenic can be used as the impurity element.

  Next, as shown in FIGS. 4-4 to 4-6, a process for processing the stacked film of the word line contact portion in a stepped manner is performed using a lithography technique and an RIE method. Here, with respect to the stacked film, the first spacer film 121, the first sacrificial film 122, the second spacer film 121, the second sacrificial film 122,..., The sixth spacer film 121, the first 6 sacrificial film 122 and seventh spacer film 121.

  First, in FIG. 4-4, the stopper film 123 to the fifth spacer film 121 are removed in the region from the vicinity of the center of the word line contact portion to the end opposite to the memory cell portion. As a result, two steps are formed. Thereafter, the same processing is repeated twice to process the word line contact portion having a structure in which the sacrificial film 122 of each layer is exposed in a stepped manner. Specifically, in the region from the vicinity of the center of the upper flat portion formed in FIG. 4-4 to the first step portion, from the stopper film 123 to the sixth spacer film 121, the lower flat portion In the region from the vicinity of the center to the end opposite to the memory cell portion, the fourth sacrificial film 122 to the third spacer film 121 are simultaneously removed. As a result, four steps are formed as shown in FIG. 4-5. Further, the stopper film 123 and the sixth spacer film 121 are removed in the region extending from the vicinity of the uppermost flat portion formed in FIG. 4-5 to the first step portion from the vicinity of the memory cell portion. Is done. At the same time, in the second to fourth flat portions from the top, the sacrificial film 122 for one layer is formed in the region extending from the vicinity of the center of each flat portion to the end opposite to the memory cell portion. The spacer film 121 is removed. As a result, as shown in FIG. 4-6, seven steps are formed, and the word line contact portion is formed.

  Next, as shown in FIG. 4-7, a planarization film 141 is formed on the entire surface of the semiconductor substrate 101. As the planarization film 141, for example, a silicon oxide film can be used. Thereafter, planarization is performed by a CMP technique until the stopper film 123 is exposed.

  Thereafter, a mask film (not shown) is formed on the entire surface of the semiconductor substrate 101, and the laminated film including the spacer film 121, the sacrificial film 122, and the stopper film 123, and the planarizing film 141 are collectively processed by lithography and RIE. Thus, the trench 142 is formed. The trench 142 has a shape extending in the word line direction so as to cut between the semiconductor films 131 adjacent in the bit line direction. Here, for example, a CVD carbon film can be used as the mask film. After forming the trench 142, the mask film is removed.

  Next, as shown in FIG. 4-8, the sacrificial film 122 is selectively removed by wet etching to form a cavity 122a between the upper and lower spacer films 121. At this time, since the semiconductor film 131 serves as a pillar and supports the spacer film 121, the cavity 122a is not crushed. Here, when a silicon oxide film is used for the spacer film 121 and a silicon nitride film is used for the sacrificial film 122, the silicon nitride film is selectively etched as compared with the silicon oxide film as a chemical solution for wet etching. Thus, for example, hot phosphoric acid can be used. The cavity 122a after the sacrificial film 122 is removed serves as a template for forming a later MONOS structure.

  After that, as shown in FIG. 4-9, the charge constituting the MONOS cell is formed so that the side surface of the columnar semiconductor film 131 partially covered with the spacer film 121 is covered by a film forming method such as a CVD method. The accumulation layer 133 is formed. The charge storage layer 133 has a laminated structure of a tunnel insulating film / charge trap film / charge block film. As the tunnel insulating film, for example, an ONO film formed by the LPCVD method can be used. As the charge trap film, a silicon nitride film formed by the ALD (Atomic Layer Deposition) method can be used. As the charge block film, An alumina film formed by the ALD method can be used. At this time, in at least the uppermost transistor adjacent in the extending direction of the trench 142 (word line direction), as shown in FIG. 3, a part of the charge storage layer 133 constituting the MONOS cell intersects in the word line direction. The above-described relationship (0) is established at least in the uppermost transistor.

This is achieved by forming the through hole 135 formed in FIG. 4-2 so as to satisfy the following expression (2).
Distance between adjacent through holes <(t _TNL + t _CT + t _CB ) × 2 (2)

  In this way, the distance between channels adjacent in the word line direction can be reduced, so that a higher bit density in the plane can be realized.

Further, after a gate electrode film 134 is formed on the side surface of the columnar semiconductor film 131 on which the charge storage layer 133 is formed by a film forming method such as a CVD method, a gate formed on the bottom of the trench 142 or the like by a dry etching method. The electrode film 134 is recessed and divided so as to be an electrode for each stacked transistor. As a material for the gate electrode film 134, for example, a tantalum nitride / tungsten laminated film can be used, and for example, CF ₄ can be used as an etching gas for dry etching.

4-10, an interlayer insulating film 143 is formed on the entire surface of the semiconductor substrate 101 so as to fill the trench 142 by a film forming method such as a CVD method. As the interlayer insulating film 143, a TEOS / O ₃ film can be used. Then, the surface of the interlayer insulating film 143 is planarized by the CMP technique.

  Next, a contact hole 144 communicating with the columnar semiconductor film 131 in the memory cell portion and the gate electrode film 134 in the word line contact portion is formed by lithography technique and RIE method. Thereafter, a conductive material film is embedded in the contact hole 144 by a film forming method such as a CVD method, and planarized by the CMP technique until the interlayer insulating film 143 is exposed, thereby forming a contact 145. As a material of the contact 145, for example, tungsten can be used.

  Thereafter, wiring layers 151 to 153 connected to the contact 145 are formed via the interlayer insulating films 161 to 163 to form a multilayer wiring layer. As described above, the nonvolatile semiconductor memory device having the structure shown in FIGS. 2-1 to 2-2 is obtained.

  In the first embodiment, the word lines are prevented from entering between the semiconductor films 131 adjacent in the word line direction. As a result, the distance between the semiconductor films 131 in the word line direction can be reduced to the processing limit, so that the memory cell pitch in the word line direction can be set between the adjacent semiconductor films 131 with the word line (gate electrode film 134). Compared to the conventional structure in which is inserted, compression can be greatly achieved.

For example, when the diameter of the semiconductor film 131 to be a channel is 50 nm and the film thickness of the charge storage layer 133 (ONO film) constituting the MONOS is 25 nm, the gate electrode film is inserted between the conventional adjacent semiconductor films 131. In the structure, the memory cell pitch in the word line direction is calculated by the following equation (3).
Memory cell pitch in the word line direction = charge storage layer thickness + semiconductor film diameter + charge storage layer thickness + gate electrode film width restricted by processing conditions = 25 nm + 50 nm + 25 nm + 50 nm
= 150 nm (3)

On the other hand, in the structure of the first embodiment, the memory cell pitch in the word line direction is calculated by the following equation (4).
Memory cell pitch in word line direction = semiconductor film diameter + total thickness of tunnel insulating film and charge trap film in charge storage layer + total thickness of tunnel insulating film and charge trap film in charge storage layer + closest Charge trap film distance = 50 nm + 10 nm + 10 nm + 5 nm
= 75 nm (4)

  Comparing the equations (3) and (4), according to the structure of the first embodiment, it is expected that the memory cell pitch in the word line direction can be almost halved as compared with the conventional structure. This indicates that about twice the bit density can be realized with the same number of stacks as in the prior art, or that the bit density equivalent to the memory formed by the prior art can be achieved with about 1/2 the number of stacks.

  As described above, according to the first embodiment, a higher bit density can be realized with a smaller number of stacked layers, that is, a lower three-dimensional structure. Therefore, a higher bit density nonvolatile semiconductor can be achieved without imposing a heavy burden on integration. A storage device can be provided.

  Also, by batch processing the stacked film, transistors can be stacked without greatly increasing the number of processes, and the bit capacity per unit area can be improved, and the degree of integration can be improved without miniaturization. become. Further, since the semiconductor film 131 is first embedded in the independent through-hole 135 before forming the gate electrode film 134, the channels merge even if the distance between the channels (semiconductor film 131) is reduced. There is no.

(Second Embodiment)
In the first embodiment, the nonvolatile semiconductor memory device having the structure in which the memory strings in which the select transistors are formed on the upper and lower ends are arranged in a matrix perpendicular to the substrate has been described. In the second embodiment, a non-volatile semiconductor memory device having a structure in which a pair of memory strings adjacent in the bit line direction is connected at the bottom will be described.

  5A and 5B are cross-sectional views schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the second embodiment. FIG. 5A is a plan view of the memory cell unit. 5-1 (b) is a cross-sectional view taken along line FF in FIG. 5 (a), FIG. 5-1 (c) is a cross-sectional view taken along line GG in FIG. 5 (a), and FIG. It is sectional drawing of the direction perpendicular | vertical to the bit line direction of a word line contact part. Note that FIG. 5-1 (a) corresponds to the HH cross section of FIGS. 5-1 (b) and (c).

  In the second embodiment, the memory cell unit 11 and the word line contact unit 20 are formed on the interlayer insulating film 102 formed on the semiconductor substrate 101. As shown in FIGS. 5A to 5C, the memory cell unit 11 has a memory in which a gate electrode film 134 is formed on a side surface of a hollow columnar semiconductor film 131 via a charge storage layer 133. Memory strings MS including the cells MC are arranged in a matrix shape on the interlayer insulating film 102 substantially vertically. Here, it is assumed that the hollow columnar semiconductor film 131 is made of a P-type semiconductor material such as P-type polycrystalline silicon. In addition, the bottom of the hollow columnar semiconductor film 131 is connected, and an insulating film 132 such as a silicon oxide film is formed so as to embed the inside of the hollow columnar semiconductor film 131.

Thus, by configuring the semiconductor film 131 in a hollow columnar shape (macaroni shape), the thickness of the channel (semiconductor film 131) controlled by the gate electrode film 134 becomes equal between the stacked memory cells MC. Variations in threshold voltage (V _th ) can be suppressed.

  The memory string MS has a structure in which a plurality of transistors having a structure in which a gate electrode film 134 is formed on a side surface of a hollow columnar semiconductor film 131 via a charge storage layer 133 are connected in series in the height direction. However, among these, the transistors at the upper end are the selection transistors SGS and SGD, and one or more memory cell transistors MC are formed below the selection transistors SGS and SGD (on the semiconductor substrate 101 side). Here, a case where four memory cell transistors MC are formed is shown. Also in the second embodiment, the selection transistors SGS and SGD have the same structure as the memory cell transistor MC. Note that the structures of the select transistors SGS, SGD and the memory cell transistor MC constituting the memory string MS are the same as those in the first embodiment, and thus the description thereof is omitted. In the memory cell unit 11, the select gate electrodes of the select transistors SGS, SGD of the memory strings MS arranged in a predetermined direction are connected to each other, and the memory cell transistors MC having the same height of the memory strings MS arranged in the predetermined direction are connected. The control gate electrodes are connected to each other.

  Further, a pair of memory strings MS adjacent in a direction crossing the gate electrode film 134 (for example, an orthogonal direction) is connected by a channel connection layer 137 formed in the interlayer insulating film 102. The channel connection layer 137 is made of a semiconductor material having a polarity different from that of the semiconductor film 131, and is made of an N-type semiconductor material such as N-type polycrystalline silicon.

  As described above, in the second embodiment, one memory cell column is configured by two memory strings MS connected by the channel connection layer 137. Therefore, the selection transistor of one memory string MS functions as the source side selection transistor SGS, and the selection transistor of the other memory string MS functions as the drain side selection transistor SGD. A source region 111 is formed at the upper end of the semiconductor film 131 of the memory string MS in which the source side select transistor SGS is formed, and a drain is formed at the upper end of the semiconductor film 131 of the memory string MS in which the drain side select transistor SGD is formed. Region 112 is formed.

  Note that as the materials of the semiconductor substrate 101, the spacer film 121, the semiconductor film 131, the charge storage layer 133, and the gate electrode film 134, the same materials as those in the first embodiment can be used. Since other configurations are substantially the same as those of the first embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  Furthermore, also in the second embodiment, the distance between the adjacent channels at the transistor formation position of the uppermost layer of the memory string MS adjacent in the word line direction (extending direction of the gate electrode film 134) is the same as that in the first embodiment. The memory strings MS are formed so that the relationship of the expression (0) is satisfied as in the embodiment.

  Next, a method for manufacturing the nonvolatile semiconductor memory device having such a structure will be described. FIGS. 6-1 to 6-10 are cross-sectional views schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment. In these drawings, (a) shows a cross section in the word line direction, (b) shows a cross section in a direction perpendicular to the word line direction, and (c) is cut along the II line in (a). (D) is a plan sectional view taken along line JJ of (b), and (e) is a word line direction of the word line contact portion. The cross section of is shown.

  First, a peripheral circuit (not shown) of the nonvolatile semiconductor memory device is formed on the semiconductor substrate 101. Thereafter, as shown in FIG. 6A, the interlayer insulating film 102 is formed in the formation region of the memory cell portion and the word line contact portion of the semiconductor substrate 101 on which the peripheral circuit is formed, and the channel connection layer is formed by lithography and RIE. A trench 136 for forming 137 is formed. The trench 136 is formed with a length capable of connecting two memory strings MS adjacent in the bit line direction. Next, a channel connection layer 137 made of an N-type semiconductor material is formed on the interlayer insulating film 102 in which the trench 136 is formed, and then recessed until the interlayer insulating film 102 is exposed by a method such as CMP. As a result, the channel connection layer 137 is formed only in the trench 136. Here, for example, a silicon oxide film can be used as the interlayer insulating film 102, and an N-type polycrystalline silicon film doped with P can be used as the channel connection layer 137.

  Thereafter, a plurality of layers of the spacer film 121 constituting the memory cell and the sacrificial film 122 to be removed later are alternately stacked on the entire surface of the semiconductor substrate 101 by a film forming method such as LPCVD, and the uppermost layer is the spacer film 121. End with. A stopper film 123 serving as a stopper at the time of CMP processing is formed on the uppermost spacer film 121 to form a laminated film. Here, the sacrificial film 122 is stacked so as to have five layers. As the sacrificial film 122, an insulating material having an etching rate larger than that of the spacer film 121 is selected in a later etching process. For example, a silicon oxide film can be used as the spacer film 121 and a silicon nitride film can be used as the sacrificial film 122. In addition to the LPCVD method, a method of forming the laminated film may be appropriately combined with techniques such as SACVD method, PECVD method, sputtering method, and SOD.

  Next, as shown in FIGS. 6-2 to 6-4, the stacked film of the word line contact portion is processed in a stepped manner using a lithography technique and an RIE method. Here, with respect to the stacked film, the first spacer film 121, the first sacrificial film 122, the second spacer film 121, the second sacrificial film 122,..., The fifth spacer film 121, the first 5 sacrificial film 122 and sixth spacer film 121.

  First, in FIG. 6B, the region from the stopper film 123 to the fourth spacer film 121 is removed in the region from the vicinity of the center of the word line contact portion to the end portion on the side opposite to the memory cell portion. As a result, two steps are formed. Thereafter, the same processing is repeated twice to process the word line contact portion having a structure in which the sacrificial film 122 of each layer is exposed in a stepped manner. Specifically, in the region from the vicinity of the center of the upper flat portion formed in FIG. 6-2 to the stepped portion, the stopper film 123, the sixth spacer film 121, and the memory cell from the vicinity of the center of the lower flat portion. The third sacrificial film 122 and the third spacer film 121 are removed at the same time in the region reaching the end opposite to the portion. As a result, four steps are formed as shown in FIG. 6-3. Further, the fifth sacrificial film 122 and the fifth spacer film 121 are removed in the region from the vicinity of the center of the second flat portion formed in FIG. 6-3 to the second stepped portion from the top. Is done. At the same time, in the fourth flat portion from the top, the sacrificial film 122 and the spacer film 121 for one layer are formed in the region from the vicinity of the center of each flat portion to the end opposite to the memory cell portion. Removed. As a result, six steps are formed as shown in FIG. 6-4, and the word line contact portion is formed.

  Next, as shown in FIG. 6-5, a planarization film 141 is formed on the entire surface of the semiconductor substrate 101. As the planarization film 141, for example, a silicon oxide film can be used. Thereafter, planarization is performed by CMP technique using the stopper film 123 as a stopper.

  Further, a mask film (not shown) is formed on the entire surface of the semiconductor substrate 101, and a laminated film composed of the spacer film 121, the sacrificial film 122, and the stopper film 123 is collectively processed by lithography and RIE to form a memory cell portion. A through hole 135 is formed. The through holes 135 are arranged in a matrix in the memory cell portion, and the bottom portion thereof communicates with the channel connection layer 137. For example, a CVD carbon film can be used as the mask film. After forming the through hole 135, the mask film is removed. Thus, a template for forming the semiconductor film 131 to be a channel is formed.

  Next, as shown in FIGS. 6-6, a semiconductor film 131 made of a P-type semiconductor material to be a channel is formed by a film forming method such as an LPCVD method. At this time, the semiconductor film 131 is formed so as to be embedded in the through hole 135 and connected to the channel connection layer 137 at the lower end. Here, as the semiconductor film 131, for example, a B-doped polycrystalline silicon film can be used. Note that the semiconductor film 131 may be formed so as to completely embed the through hole 135 as in the first embodiment, or may be formed so as to be embedded in a macaroni in a hollow manner. Here, it shall embed in hollow.

  Thereafter, an insulating film 132 made of a silicon oxide film or the like is formed by an ALD method so as to embed the inside of the semiconductor film 131 formed in a hollow macaroni shape. Next, etch back is performed by RIE to remove the semiconductor film 131 and the insulating film 132 on the stopper film 123. As a result, the hollow semiconductor film 131 and the insulating film 132 remain only in the through hole 135. Subsequently, using a lithography technique and an ion implantation technique, an impurity element having a predetermined conductivity type is ion-implanted into the upper portion of the semiconductor film 131 to form a source region 111 and a drain region 112. Here, for example, arsenic can be used as the impurity element.

  Next, as shown in FIGS. 6-7, a mask film (not shown) is formed on the entire surface of the semiconductor substrate 101, and the laminated film and the planarizing film 141 are collectively processed by lithography and RIE to form the trench 142. Form. The trench 142 has a shape extending in the word line direction so as to cut between the semiconductor films 131 adjacent in the bit line direction. For example, a CVD carbon film can be used as the mask film. After forming the trench 142, the mask film is removed.

  Next, as shown in FIGS. 6-8, the sacrificial film 122 is selectively removed by vapor phase etching to form a cavity 122a between the upper and lower spacer films 121. At this time, since the semiconductor film 131 serves as a pillar and supports the spacer film 121, the cavity 122a is not crushed. When a silicon oxide film is used for the spacer film 121 and a silicon nitride film is used for the sacrificial film 122, for example, a hydrofluoric acid gas is used so that the silicon nitride film is selectively etched as compared with the silicon oxide film. Phase etching can be used. The cavity 122a after the sacrificial film 122 is removed serves as a template for forming a later MONOS structure.

  Thereafter, as shown in FIGS. 6-9, the charge storage layer 133 constituting the MONOS cell is formed so that the side surface of the hollow columnar semiconductor film 131 partially covered with the spacer film 121 is covered. The charge storage layer 133 has a laminated structure of a tunnel insulating film / charge trap film / charge block film. As the tunnel insulating film, for example, a thermal oxide film formed by ISSG (In-Situ Steam Generator) oxidation can be used, and as the charge trap film, a silicon nitride film formed by the ALD method can be used. As the film, a hafnia film formed by an ALD method can be used. At this time, at least the uppermost memory cell adjacent in the trench extending direction (word line direction) has a shape in which a part of the charge storage layer 133 constituting the MONOS cell intersects in the word line direction, and at least the uppermost layer. In this transistor, the relationship of the expression (0) described in the first embodiment is established.

  This is achieved by forming the through hole 135 shown in FIG. 6-5 so as to satisfy the expression (2). As a result, the distance between adjacent channels can be reduced, so that a higher in-plane bit density can be realized.

Further, after forming the gate electrode film 134 on the side surface of the hollow columnar semiconductor film 131 on which the charge storage layer 133 is formed by a film forming method such as a CVD method, the gate electrode film 134 is formed on the bottom of the trench 142 or the like by a dry etching method. The gate electrode film 134 is recessed and divided so as to be an electrode for each stacked transistor. Here, as a material of the gate electrode film 134, for example, a titanium nitride / tungsten laminated film can be used, and as an etching gas for dry etching, for example, diluted ClF ₃ can be used.

Subsequently, as illustrated in FIG. 6-10, an interlayer insulating film 143 is formed on the entire surface of the semiconductor substrate 101 by a film forming method such as a CVD method so as to fill the trench 142. As the interlayer insulating film 143, a TEOS / O ₃ film can be used. Then, the surface of the interlayer insulating film 143 is planarized by the CMP technique.

  Next, a contact hole 144 communicating with the hollow columnar semiconductor film 131 in the memory cell portion and the gate electrode film 134 in the word line contact portion is formed by lithography technique and RIE method. Thereafter, a conductive material film is embedded in the contact hole 144 by a film forming method such as a CVD method, and planarized by the CMP technique until the interlayer insulating film 143 is exposed, thereby forming a contact 145. As a material of the contact 145, for example, tungsten can be used.

  Thereafter, wiring layers 151 to 153 connected to the contact 145 are formed via the interlayer insulating films 161 to 163 to form a multilayer wiring layer. As described above, the nonvolatile semiconductor memory device having the structure shown in FIGS. 5-1 to 5-2 is obtained.

  According to the second embodiment, the same effects as those of the first embodiment can be obtained.

(Third embodiment)
FIG. 7 is a cross-sectional view schematically showing an example of the structure of the memory cell of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 7A is a partial cross-sectional view in the bit line direction of the memory cell portion. (B) is a KK sectional view of (a). FIG. 8 is a diagram illustrating an example of a semiconductor film arrangement method.

As described above, in the manufacturing methods of the first and second embodiments, it is necessary to perform recessing by isotropic etching after the gate electrode film 134 is buried, and therefore, between the semiconductor films 131 adjacent in the bit line direction. The distance L is set to satisfy the following expression (5), where the width of the spacer film 121 is t _Spacer and the film thickness of the gate electrode film 134 is t _GATE .
L> (t _TNL + t _CT + t _CB + t _Spacer + t _GATE ) × 2 (5)

  This is because the recess of the gate electrode film 134 between the semiconductor films 131 adjacent in the bit line direction cannot be performed unless Expression (5) is satisfied. That is, in the structures of the first and second embodiments described above, miniaturization is possible in the word line direction, but miniaturization in the bit line direction is limited. Therefore, as shown in FIG. 8, as described in the first and second embodiments, the charge storage layer 133 on the side surface intersects in the word line direction by satisfying the equation (0) at the uppermost transistor formation position. The semiconductor film 131 is arranged in the bit line direction while satisfying the expression (5).

  FIG. 9 is a diagram showing an example of a scaling scenario of the nonvolatile semiconductor memory device having the structures of the first and second embodiments. Here, it is shown how the number of stacked layers for realizing 128 Gb NAND varies depending on the diameter of the semiconductor film 131 serving as a channel when the word line direction and the bit line direction are set to the minimum dimension. Therefore, the horizontal axis of this figure indicates the diameter (nm) of the semiconductor film 131 to be a channel, and the vertical axis indicates the number of stacked memory cells required for manufacturing a 128 Gb NAND flash memory. As shown in FIG. 9, the number of stacked layers can be greatly suppressed by reducing the diameter of the semiconductor film 131. In particular, when the diameter of the semiconductor film 131 is 20 nm, the number of stacked layers can be reduced to 10 or less.

  According to the third embodiment, the number of stacked memories can be reduced by reducing the diameter of the semiconductor film 131 serving as a channel, and the number of manufacturing steps can be reduced as compared with the case where the number of stacked memories is large. A nonvolatile semiconductor memory device can be manufactured. As a result, it is possible to further improve the bit density such as 256 Gb NAND flash memory and 1 Tb NAND flash memory.

(Fourth embodiment)
FIG. 10 is a perspective view of a part of the memory cell portion and the word line contact portion of the nonvolatile semiconductor memory device according to the fourth embodiment. FIGS. 11A to 11B are cross-sectional views schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the fourth embodiment, and FIG. 11-1 (b) is an LL sectional view of (a), FIG. 11-1 (c) is an MM sectional view of (a), and FIG. 2A is a cross-sectional view in the direction perpendicular to the bit line direction at the word line contact formation position of the word line contact portion, and FIG. 11B corresponds to the memory string formation position of the word line contact portion. It is sectional drawing of a direction perpendicular | vertical to the bit line direction in a position. In addition, FIG. 11-1 (a) is corresponded to the NN cross section of FIGS. 11-1 (b) and (c).

  In the fourth embodiment, for the transistors formed at each height of the memory string MS, the gate electrode film 134 disposed via the charge storage layer 133 is formed on both sides in the bit line direction with the semiconductor film 131 interposed therebetween. Each has an independent structure. In other words, by arranging two independent gate electrode films 134 at the same height of the semiconductor film 131, the storage density is increased by a factor of two compared to the structures of the first to third embodiments.

  In order to obtain such a structure, as shown in FIGS. 10, 11-1 (a) to (c) and FIG. 11-2 (b), the memory cell unit 11 has a memory string MS in a column shape. Except that the hollow semiconductor film 131 is filled with an insulating film 132, but the shape of the word line contact portion 20 extends from the memory cell portion 11. The film 134 is structured to separate into two in one memory string MS. Specifically, a hollow columnar semiconductor film 131 is arranged extending to the word line contact portion 20. At this time, also in the word line contact portion 20, the semiconductor film 131 adjacent in the word line direction is arranged so as to satisfy the relationship of the expression (0) described in the first embodiment. Accordingly, the gate electrode film 134 cannot enter between the semiconductor films 131 adjacent in the word line direction, and the two gate electrode films 134 formed on both sides in the bit line direction with the semiconductor film 131 interposed therebetween are electrically connected. It becomes possible to separate. The semiconductor film 131 disposed in the word line contact portion 20 does not constitute a memory string, but merely for separating the gate electrode films 134 disposed on both sides in the bit line direction with the semiconductor film 131 interposed therebetween. is there.

  Further, as shown in FIGS. 10 and 11-2 (a), two gate electrode films 134 of the memory cell MC or select transistors SGS and SGD formed at a certain height of the memory string MS, and a word (not shown) In order to connect the line drive circuit or the selection gate line drive circuit, in the word line contact portion 20, one contact 145 is provided on each side of the dummy semiconductor film 131 in the bit line direction. In addition, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the description is abbreviate | omitted.

  Next, a method for manufacturing the nonvolatile semiconductor memory device having such a structure will be described. 12A to 12E are cross-sectional views schematically illustrating an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. In these drawings, (a) shows a cross section in the word line direction, (b) shows a cross section in a direction perpendicular to the word line direction, and (c) is cut along the line OO in (a). (D) is a plan sectional view taken along the line P-P in (b), and (e) is a contact formation position of the word line contact portion. FIG. 6F shows a cross-sectional view in the word line direction at the dummy cell formation position of the word line contact portion.

  First, a peripheral circuit (not shown) of the nonvolatile semiconductor memory device is formed on the semiconductor substrate 101. Also, as shown in FIG. 12A, a source region 111 is formed by implanting and activating an impurity of a predetermined conductivity type into the memory cell portion of the semiconductor substrate 101 by an ion implantation method. As the source region 111, for example, an N-type source region can be used.

  Next, a plurality of spacer films 121 and sacrificial films 122 constituting a memory cell are alternately stacked on the entire surface of the semiconductor substrate 101 by a film forming method such as PECVD, and finally the spacer film 121 ends. A stopper film 123 serving as a stopper at the time of CMP processing is formed on the uppermost spacer film 121 to form a laminated film. Here, the sacrificial film 122 is stacked so as to have six layers. As the sacrificial film 122, an insulating material having an etching rate larger than that of the spacer film 121 is selected by a later wet etching process. For example, a silicon oxide film can be used as the spacer film 121 and a silicon nitride film can be used as the sacrificial film 122. As the stopper film 123, for example, a silicon nitride film can be used. In addition to the PECVD method, a method of forming a laminated film can be used by appropriately combining techniques such as SACVD, LPCVD, sputtering, and SOD.

  Next, as shown in FIG. 12B, a structure in which the laminated film of the word line contact portion is processed in a staircase shape by using a lithography technique and an RIE method, and the sacrificial film 122 of each layer is exposed in a staircase shape. The word line contact portion is formed. The stepped word line contact portion is formed by a method similar to the method described in FIGS. 4-4 to 4-6 of the first embodiment.

  Thereafter, as shown in FIG. 12C, a planarization film 141 is formed on the entire surface of the semiconductor substrate 101. As the planarization film 141, for example, a silicon oxide film can be used. Thereafter, planarization is performed by CMP until the stopper film 123 is exposed.

  Next, a mask film (not shown) is formed on the entire surface of the stopper film 123, and the laminated film of the memory cell portion and the word line contact portion is collectively processed by a known lithography technique and RIE method, and penetrates the semiconductor substrate 101. A hole 135 is formed. Here, for example, a CVD carbon film can be used as the mask film. At this time, unlike the first embodiment, the through-holes 135 are formed at the same density even for the word line contact portion that does not require the formation of a channel. Subsequently, the mask film is removed to form a channel semiconductor template.

Next, as shown in FIG. 12-4, a semiconductor film 131 to be a channel is formed by a film forming method such as an LPCVD method. At this time, the semiconductor film 131 is formed so as to be embedded in the through hole 135 and to be connected to the semiconductor substrate 101 at the lower end. Here, as the semiconductor film 131, for example, a B-doped polycrystalline silicon film can be used, and the B concentration at this time can be set to 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , for example. The semiconductor film 131 is formed along the inner surface of the through-hole 135 so as to be embedded in a macaroni hollow. By embedding in the hollow, the thickness of the semiconductor film 131 controlled by the gate electrode film 134 is equalized between the stacked memory cells MC, so that variation in transistor characteristics between the memory cells MC can be reduced, and a single film Interference between the memory cells MC when electrons are independently written into the memory cells MC on both sides of the channel (semiconductor film) is less likely to occur.

  Further, an insulating film 132 made of a silicon oxide film or the like is formed by the ALD method so as to fill the inside of the hollow columnar semiconductor film 131. Thereafter, etch back is performed by a method such as RIE, and the semiconductor film 131 and the insulating film 132 on the stopper film 123 are removed. As a result, the hollow columnar semiconductor film 131 and the insulating film 132 remain only in the through hole 135. Subsequently, an impurity element having a predetermined conductivity type is ion-implanted into the upper portion of the semiconductor film 131 by using a lithography technique and an ion implantation technique, so that the drain region 112 is formed. Here, for example, arsenic can be used as the impurity element.

  Thereafter, as shown in FIG. 12-5, a mask film (not shown) is formed on the entire surface of the semiconductor substrate 101, and the laminated film and the planarizing film 141 are collectively processed by the lithography technique and the RIE method to form the trench 142. Form. The trench 142 has a shape extending in the word line direction so as to cut between the semiconductor films 131 adjacent in the bit line direction. For example, a CVD carbon film can be used as the mask film. After forming the trench 142, the mask film is removed.

  Next, as shown in FIG. 12-6, the sacrificial film 122 is selectively removed by wet etching to form a cavity 122a between the upper and lower spacer films 121. At this time, since the semiconductor film 131 serves as a pillar to support the spacer film 121, the cavity 122a is not crushed. When a silicon oxide film is used for the spacer film 121 and a silicon nitride film is used for the sacrificial film 122, the silicon nitride film is selectively etched as compared with the silicon oxide film as a chemical solution for wet etching. For example, hot phosphoric acid can be used. The cavity 122a after the sacrificial film 122 is removed serves as a template for forming a later MONOS structure.

  Thereafter, as shown in FIG. 12-7, the charge constituting the MONOS cell is formed so that the side surface of the columnar semiconductor film 131 partially covered with the spacer film 121 is covered by a film forming method such as a CVD method. The accumulation layer 133 is formed. The charge storage layer 133 has a laminated structure of a tunnel insulating film / charge trap film / charge block film. For example, an ONO film formed by LPCVD can be used as the tunnel insulating film, a silicon nitride film formed by ALD can be used as the charge trap film, and an ALD method can be used as the charge block film. An alumina film can be used. At this time, in the transistor adjacent in the extending direction of the trench 142 (word line direction), a part of the charge storage layer 133 constituting the MONOS cell intersects in the word line direction, and all the transistors on the memory string MS In the transistor, the relationship of the expression (0) shown in the first embodiment is established.

  This is achieved by forming the through hole 135 formed in FIG. 12-3 so as to satisfy the expression (2) shown in the first embodiment. At this time, in the two memory cells adjacent in the word line direction, a part of the charge block film is merged with the adjacent memory cells. As a result, the distance between adjacent semiconductor films 131 can be reduced.

  Although further miniaturization is possible by crossing up to the charge trap film between adjacent cells, if the charge trap film crosses, it is adjacent through the part where the charge stored in the charge trap film crosses. This is not preferable because the memory cell may leak. Therefore, in consideration of the processing accuracy of the through-hole 135, it is possible to make the charge block film thicker so that a structure in which the charge block film intersects (shared) between adjacent memory cells can be ensured. Therefore, it is desirable to use a high dielectric constant material such as alumina, hafnia, or zirconia as the charge block film.

Further, after a gate electrode film 134 is formed on the side surface of the columnar semiconductor film 131 on which the charge storage layer 133 is formed by a film forming method such as a CVD method, a gate formed on the bottom of the trench 142 or the like by a dry etching method. The electrode film 134 is recessed and divided so as to be an electrode for each stacked transistor. As a material of the gate electrode film 134, for example, tungsten can be used, and as an etching gas for dry etching, for example, CF ₄ can be used.

  FIG. 13 is a partial perspective view schematically showing the state of the memory cell portion and the word line contact portion in a state where the charge storage layer and the gate electrode film are formed on the semiconductor film. When the gate electrode film 134 is formed, the charge storage layer 133 is formed in the space between the memory strings MS in the word line direction so that a part of the charge storage layer 133 is shared between adjacent transistors. The gate electrode film 134 is not formed. That is, the two gate electrode films 134 formed on both sides in the bit line direction with the semiconductor film 131 interposed therebetween are formed independently without being physically connected.

  In this way, by adopting a structure in which a part of the charge block film intersects with an adjacent transistor between adjacent transistors at all heights of the memory string MS, the gate electrode film is automatically sandwiched between the semiconductor films 131. 134 can be divided and can function as an independent electrode. That is, an additional processing step for dividing the gate electrode film 134 formed at the same height of the semiconductor film 131 in the bit line direction is not required. For this reason, by providing dummy cells in word line contact portions that are not originally provided with memory cells, the gate electrode film 134 is completely divided between the memory cell portions and the word line contact portions.

  In the structure of the fourth embodiment, an electrode is formed only on one side of the cylindrical channel (semiconductor film 131), and only one side of the cylindrical channel is used as a memory. Since the cell is a junction-free Inversion type cell, there is no problem in transistor operation, and only one side of the cylindrical channel silicon is inverted and used as a channel.

  As described above, the gate electrode films 134 for six layers are collectively formed. The first and sixth gate electrode films 134 from the top serve as selection gate electrodes (SG), and the second to fifth electrodes from the top serve as word lines. A control gate electrode (CG).

Subsequently, as shown in FIG. 12-8, an interlayer insulating film 143 is formed on the entire surface of the semiconductor substrate 101 so as to fill the trench 142 by a film forming method such as a CVD method. As the interlayer insulating film 143, a TEOS / O ₃ film can be used. Then, the surface of the interlayer insulating film 143 is planarized by the CMP technique.

  Next, a contact hole 144 communicating with the columnar semiconductor film 131 in the memory cell portion and the gate electrode film 134 in the word line contact portion is formed by lithography technique and RIE method. Thereafter, a conductive material film is embedded in the contact hole 144 by a film forming method such as a CVD method, and planarized by the CMP technique until the interlayer insulating film 143 is exposed, thereby forming a contact 145. As a material of the contact 145, for example, tungsten can be used.

  Thereafter, wiring layers 151 to 153 connected to the contact 145 are formed via the interlayer insulating films 161 to 163 to form a multilayer wiring layer. As described above, the nonvolatile semiconductor memory device having the structure shown in FIGS. 11A to 11B is obtained.

  In the fourth embodiment, the hollow columnar semiconductor film 131 is formed in the memory cell portion and the word line contact portion so that the expression (0) is satisfied at the formation positions of all the transistors in the height direction of the memory string MS. Since it is formed, two gate electrode films 134 that are physically (electrically) divided in the bit line direction are formed at the formation positions of the transistors in the semiconductor film 131, and the first to third embodiments are formed. As compared with the case of the above, there is an effect that the storage density can be doubled.

Also in the structure of the fourth embodiment, as in the first to third embodiments, the semiconductor film 131 can be brought close to the processing limit, so that the memory cell pitch in the bit line / word line direction is increased. As compared with the conventional structure in which a gate electrode film is inserted between adjacent semiconductor films. For example, if the diameter of the semiconductor film 131 (the outer diameter of the hollow columnar semiconductor film 131) is 50 nm and the film thickness of the charge storage layer 133 constituting the MONOS cell is 25 nm, it is adjacent to the conventional word line direction. In the structure in which the gate electrode film 134 is inserted between the matching semiconductor films 131, the memory cell pitch in the word line direction is calculated by the following equation (6).
Memory cell pitch in the word line direction = charge storage layer thickness + semiconductor film diameter + charge storage layer thickness + gate electrode film width restricted by processing conditions = 25 nm + 50 nm + 25 nm + 50 nm
= 150 nm (6)

Further, the memory cell pitch in the bit line direction is calculated by the following equation (7).
Bit line direction memory cell pitch = gate electrode film width restricted by processing conditions + charge storage layer thickness + semiconductor film diameter + charge storage layer thickness + gate electrode width restricted by processing conditions + restricted by processing conditions Gate electrode film interval = 25 nm + 25 nm + 50 nm + 25 nm + 25 nm + 50 nm
= 200 nm (7)

When the cell area of the conventional structure is calculated using the equations (6) and (7), it is found that about 30,000 nm ² is necessary.

On the other hand, in the structure of the fourth embodiment, the memory cell pitch in the word line direction is calculated by the following equation (8).
Memory cell pitch in word line direction = semiconductor film diameter + total thickness of tunnel insulating film and charge trap film in charge storage layer film + total thickness of tunnel insulating film and charge trap film in charge storage layer film + Distance between closest charge trap films = 50 nm + 10 nm + 10 nm + 5 nm
= 75nm (8)

The memory cell pitch in the bit line direction is the same as the conventional structure, and is 200 nm from the equation (7). In the fourth embodiment, in consideration of using both sides of the semiconductor film 131 as separate memory cells, the cell area in the fourth embodiment is calculated using the equations (7) and (8). Is calculated by the following equation (9).
Cell area = Pitch in the word line direction × Pitch in the bit line direction × 1/2
= 75 nm × 200 nm × 1/2
= 7,500 nm ² (9)

  As described above, according to the structure of the fourth embodiment, it is expected that the cell area can be reduced to about ¼ of the prior art. This indicates that a bit density of about 4 times can be realized with the same number of stacks as in the prior art, or a bit density equivalent to that of a memory formed in the prior art can be achieved with a stack number of about 1/4. For example, when 24 layers are conventionally required, according to the structure of the fourth embodiment, it is possible to achieve a bit density equivalent to the conventional case with 6 layers.

  As described above, according to the fourth embodiment, it is possible to realize a higher bit density with a smaller number of stacks, that is, a lower three-dimensional structure. Therefore, even higher bit density can be achieved without imposing a heavy burden on integration. It is possible to provide a non-volatile semiconductor memory device. Further, since the semiconductor film 131 is formed by embedding in the independent through-hole 135 before the formation of the gate electrode film 134, the channels can be fused even if the distance between the channels (semiconductor film 131) is reduced. Absent.

(Fifth embodiment)
In the fourth embodiment, the case where severe restrictions are imposed on the distance between the channels in order to separate the gate electrode films on both sides in the bit line direction across the semiconductor film is illustrated. In the fifth embodiment, a nonvolatile semiconductor memory device having a structure in which strict restrictions are not imposed on the distance between channels will be described in place of requiring alignment accuracy as compared with the fourth embodiment. In the following description, a non-volatile semiconductor memory device having a structure in which a pair of memory strings adjacent to each other in the bit line direction is connected to the lower portion as in the second embodiment is taken as an example and extends in the word line direction. A case where the charge storage layer and the gate electrode film are divided into two by an insulating film will be described.

  FIGS. 14A to 14B are cross-sectional views schematically showing an example of the configuration of the nonvolatile semiconductor memory device according to the fifth embodiment. FIG. 14A is a plan view of the memory cell unit. 14B is a cross-sectional view taken along the line Q-Q of FIG. 14A, FIG. 14C is a cross-sectional view taken along the line RR of FIG. 14A, and FIG. It is sectional drawing of the direction perpendicular | vertical to the bit line direction of a word line contact part. Note that FIG. 14-1 (a) corresponds to the SS cross section of FIGS. 14-1 (b) and 14 (c).

  As shown in FIGS. 14-1 (a) to (c), the memory cell portion has substantially the same structure as that of the second embodiment, but is provided at each height of the memory string MS. The charge storage layer 133 and the gate electrode film 134 have an insulating film 147 that extends in the word line direction and passes through substantially the center of the memory string MS so as to be separated on both sides in the bit line direction across the memory string MS. Provided. The insulating film 147 is provided up to the word line contact portion. In the fifth embodiment, the semiconductor film 131 adjacent in the word line direction may not be formed so as to satisfy the expression (0) described in the first embodiment.

  Further, as shown in FIG. 14B, the word line contact portion has substantially the same structure as that of the second embodiment, but the charge storage layer 133 and the gate electrode film 134 are arranged in the width direction ( They are separated by an insulating film not shown in the vicinity of the approximate center in the bit line direction. That is, the two gate electrode films 134 are independently drawn from the semiconductor film 131 formed at a certain height of the memory string MS. A contact 145 is provided on each gate electrode film 134. FIG. 14-2 shows a cross section on the gate electrode film 134 disposed on one side of the memory string MS. A contact 145 is similarly provided on the other gate electrode film 134 with the memory string MS interposed therebetween, but the position in the word line direction is different from the position of the contact 145 shown in the figure, and the contact 145 in the figure. The wiring layer 151 is not connected to the wiring layer 151. Since other configurations are the same as those of the second embodiment, the description thereof is omitted.

  Next, a method for manufacturing the nonvolatile semiconductor memory device having such a structure will be described. 15-1 to 15-9 are cross-sectional views schematically illustrating an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment. In these drawings, (a) shows a cross section in the word line direction, (b) shows a cross section in a direction perpendicular to the word line direction, and (c) is cut along the TT line in (a). (D) shows a cross-sectional plan view taken along the line U-U in (b), and (e) shows the word line direction of the word line contact portion. The cross section of is shown.

  First, a peripheral circuit (not shown) of the nonvolatile semiconductor memory device is formed on the semiconductor substrate 101. Further, as shown in FIG. 15A, an interlayer insulating film 102 is formed in the formation region of the memory cell portion and the word line contact portion of the semiconductor substrate 101 on which the peripheral circuit is formed, and channel connection is performed by the lithography technique and the RIE method. A trench 136 for forming the layer 137 is formed. The trench 136 is formed with a length capable of connecting two memory strings MS adjacent in the bit line direction. Next, a channel connection layer 137 made of an N-type semiconductor material is formed on the interlayer insulating film 102 in which the trench 136 is formed, and then recessed until the interlayer insulating film 102 is exposed by a method such as CMP. As a result, the channel connection layer 137 is formed only in the trench 136. Here, for example, a silicon oxide film can be used as the interlayer insulating film 102, and an N-type polycrystalline silicon film doped with P can be used as the channel connection layer 137.

  After that, a plurality of spacer films 121 constituting memory cells and sacrificial films 122 to be removed later are alternately stacked on the entire surface of the semiconductor substrate 101 by a film forming method such as PECVD, and the uppermost layer is a spacer film 121. End with. A stopper film 123 serving as a stopper at the time of CMP processing is formed on the uppermost spacer film 121 to form a laminated film. Here, the sacrificial film 122 is stacked so as to have five layers. As the sacrificial film 122, an insulating material having an etching rate larger than that of the spacer film 121 is selected in a later etching process. For example, a silicon oxide film can be used as the spacer film 121 and a silicon nitride film can be used as the sacrificial film 122. In addition to the PECVD method, a technique such as SACVD method, LPCVD method, sputtering method, SOD, or the like can be used in combination as a method for forming the laminated film.

  Next, as shown in FIG. 15B, a slit for forming the insulating film 147 is formed by dividing the gate electrode film 134 to be formed later on both sides in the bit line direction across the memory strings MS by lithography and RIE. 146 is formed. Then, an isolation film made of an insulating film 147 such as a silicon oxide film is formed in the slit 146.

  Next, as shown in FIG. 15C, using the lithography technique and the RIE method, a process for processing the stacked film of the word line contact portion in a step shape is performed, so that the lower sacrificial film 122 is exposed. To process. The stepped processing of the laminated film can be performed by a method similar to that described in FIGS. 6-2 to 6-4 of the second embodiment. Next, a planarization film 141 is formed on the entire surface of the semiconductor substrate 101. As the planarization film 141, for example, a silicon oxide film can be used. Thereafter, planarization is performed by CMP technique using the stopper film 123 as a stopper.

  Thereafter, as shown in FIG. 15-4, a mask film (not shown) is formed on the entire surface of the semiconductor substrate 101, and the laminated film of the memory cell portion is collectively processed by lithography and RIE to form a through hole 135. To do. The through holes 135 are arranged in a matrix shape on the region including the insulating film 147 formed in FIG. 15B in the memory cell portion, and the bottom portion communicates with the channel connection layer 137. For example, a CVD carbon film can be used as the mask film. After forming the through hole 135, the mask film is removed. Thus, a template for forming the semiconductor film 131 to be a channel is formed. Further, since the insulating film 147 is formed in the fifth embodiment, as described in the fourth embodiment, between the semiconductor films 131 adjacent to each other in the word line direction of each layer in the height direction, It is not necessary to form the through hole 135 so as to satisfy the expression (2).

Next, as shown in FIG. 15-5, a semiconductor film 131 made of a P-type semiconductor material to be a channel is formed by a film forming method such as an LPCVD method. At this time, the semiconductor film 131 is formed so as to be embedded in the through hole 135 and connected to the channel connection layer 137 at the lower end. Here, as the semiconductor film 131, for example, a B-doped polycrystalline silicon film can be used, and the B concentration at this time can be set to 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , for example. Note that the semiconductor film 131 is formed so as to be embedded in a macaroni hollow along the through hole 135 as in the fourth embodiment.

  Further, an insulating film 132 made of a silicon oxide film or the like is formed by a method such as ALD so as to embed the inside of the semiconductor film 131 formed in a hollow column shape. Thereafter, etch back is performed by a method such as RIE, and the semiconductor film 131 and the insulating film 132 on the stopper film 123 are removed. As a result, the hollow columnar semiconductor film 131 and the insulating film 132 remain only in the through hole 135. Subsequently, using a lithography technique and an ion implantation technique, an impurity element having a predetermined conductivity type is ion-implanted into the upper portion of the semiconductor film 131 to form a source region 111 and a drain region 112. Here, for example, arsenic can be used as the impurity element.

  Next, as shown in FIG. 15-6, a mask film (not shown) is formed on the entire surface of the semiconductor substrate 101, and the laminated film and the planarizing film 141 are collectively processed by the lithography technique and the RIE method to form the trench 142. Form. The trench 142 has a shape extending in the word line direction so as to cut between the semiconductor films 131 adjacent in the bit line direction. For example, a CVD carbon film can be used as the mask film. After forming the trench 142, the mask film is removed.

  Next, as shown in FIG. 15-7, the sacrificial film 122 is selectively removed by wet etching to form a cavity 122a between the upper and lower spacer films 121. At this time, since the semiconductor film 131 serves as a pillar to support the spacer film 121, the cavity 122a is not crushed. When a silicon oxide film is used for the spacer film 121 and a silicon nitride film is used for the sacrificial film 122, the silicon nitride film is selectively etched as compared with the silicon oxide film as a chemical solution for wet etching. For example, hot phosphoric acid can be used. The cavity 122a after the sacrificial film 122 is removed serves as a template for forming a later MONOS structure.

  Thereafter, as shown in FIG. 15-8, the charge storage layer 133 constituting the MONOS cell is formed so that the side surface of the hollow columnar semiconductor film 131 partially covered with the spacer film 121 is covered. The charge storage layer 133 has a laminated structure of a tunnel insulating film / charge trap film / charge block film. For example, an ONO film formed by LPCVD can be used as the tunnel insulating film, a silicon nitride film formed by ALD can be used as the charge trap film, and an ALD method can be used as the charge block film. An alumina film can be used. Further, as described above, since the through hole 135 does not necessarily satisfy the expression (2), the charge storage layer 133 (charge block film) is composed of two transistors adjacent to each other in the word line direction in each layer in the height direction. The structure does not have to be a part of the structure.

  Further, a gate electrode film 134 is formed on the side surface of the hollow columnar semiconductor film 131 in which the charge storage layer 133 is formed by a film forming method such as a CVD method. At this time, unlike the fourth embodiment, in the fifth embodiment, since the insulating film 147 is formed in a slit shape so as to penetrate the memory strings MS adjacent in the word line direction, the gate electrode film 134 is formed. Are automatically divided across the semiconductor film 131 and function as independent electrodes.

Thereafter, the gate electrode film 134 formed at the bottom of the trench 142 or the like is recessed by a dry etching method, and is divided so as to be an electrode for each stacked transistor. Here, as a material of the gate electrode film 134, for example, a tungsten nitride / tungsten laminated film can be used, and as an etching gas for dry etching, for example, CF ₄ can be used. With the above processing, five layers of gate electrode films 134 are formed in a lump, but the first gate electrode film 134 from the top serves as a selection gate electrode, and the second to fifth layers of gate electrode films 134 serve as word lines. The control gate electrode becomes.

Subsequently, as shown in FIG. 15-9, an interlayer insulating film 143 is formed on the entire surface of the semiconductor substrate 101 so as to bury the trench 142 by a film forming method such as a CVD method. As a result, the interlayer insulating film 143 is buried in the trenches 142 formed at predetermined intervals in the bit line direction formed in FIG. 15-6. As the interlayer insulating film 143, a TEOS / O ₃ film can be used. Then, the surface of the interlayer insulating film 143 is planarized by the CMP technique.

  Next, a contact hole 144 communicating with the hollow columnar semiconductor film 131 in the memory cell portion and the gate electrode film 134 in the word line contact portion is formed by lithography technique and RIE method. Thereafter, a conductive material film is embedded in the contact hole 144 by a film forming method such as a CVD method, and planarized by the CMP technique until the interlayer insulating film 143 is exposed, thereby forming a contact 145. As a material of the contact 145, for example, tungsten can be used.

  Thereafter, wiring layers 151 to 153 connected to the contact 145 are formed via the interlayer insulating films 161 to 163 to form a multilayer wiring layer. As described above, the nonvolatile semiconductor memory device having the structure shown in FIGS. 14A to 14B is obtained.

  According to the structure of the fifth embodiment, the slit-like insulating film 147 that divides the gate electrode film 134 into two in the bit line direction with the memory string MS interposed therebetween is provided. Unlike the embodiment, the gate electrode film 134 can be divided without the semiconductor film 131 serving as a channel being sufficiently close to the word line direction. Further, as in the fourth embodiment, the cell area can be reduced to about ¼ that of the prior art by reducing the distance between the semiconductor films 131 adjacent in the word line direction.

  Further, in the case of the fourth embodiment, when the through-hole 135 serving as the template of the semiconductor film 131 is tapered, it is adjacent to the word line direction at the position of the transistor formed in the lower layer. There may be a case where the distance between the through holes 135 does not satisfy the above formula (2) and the lower gate electrode film 134 is not divided well. However, according to the fifth embodiment, the slit-like insulating film that divides the semiconductor film 131 of the memory strings MS connected to each other by the gate electrode film 134 from the vicinity of the center of the memory strings MS to both sides in the bit line direction. Since 147 is provided, the semiconductor film 131 can be reliably divided into two independent gate electrode films 134 with the semiconductor film 131 interposed therebetween. As a result, a higher bit density can be realized with a smaller number of stacks, that is, a lower three-dimensional structure, and a higher bit density nonvolatile memory can be provided without placing a heavy burden on integration. Become.

  Further, since the peripheral circuit is provided on the semiconductor substrate 101 and the memory cell portion is provided thereon via the interlayer insulating film 102, the storage density can be further improved as compared with the fourth embodiment. It also has the effect of being able to.

  Note that the conductivity types of the semiconductor film 131 and the channel connection layer 137 in the above description are merely examples, and the present invention is not limited to this.

  DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device, 11 ... Memory cell part, 12 ... Word line drive circuit, 13 ... Source side selection gate line drive circuit, 14 ... Drain side selection gate line drive circuit, 15 ... Sense amplifier, 16 ... Word line , 17 ... Source side selection gate line, 18 ... Drain side selection gate line, 19 ... Bit line, 20 ... Word line contact portion, 101 ... Semiconductor substrate, 102, 143, 161 to 163 ... Interlayer insulating film, 111 ... Source region , 112 ... drain region, 121 ... spacer film, 122 ... sacrificial film, 122a ... cavity, 123 ... stopper film, 131 ... semiconductor film, 132, 147 ... insulating film, 133A ... tunnel insulating film, 133B ... charge trap film, 133C ... Charge block film, 133 ... Charge storage layer, 134 ... Gate electrode film, 135 ... Through hole, 136, 142 ... To Inch, 137 ... channel connection layer, 141 ... flattening film, 144 ... contact hole, 145 ... contact, 146 ... slits, 151153 ... wiring layer.

Claims (5)

A memory string having a gate dielectric film formed on a side surface of a columnar semiconductor film and a plurality of transistors each including a gate electrode film formed on the gate dielectric film in a height direction of the semiconductor film is formed on the substrate. A non-volatile semiconductor memory device in which the gate electrode films of the transistors at the same height of the memory strings arranged in a first direction are connected in a matrix form,
Nonvolatile, wherein a distance between the semiconductor films in at least the uppermost layer of the memory string adjacent in the first direction is less than twice the thickness of the gate dielectric film Semiconductor memory device. The distance between the semiconductor films at all the transistor formation positions of the memory strings adjacent in the first direction is smaller than twice the thickness of the gate dielectric film,
The gate electrode film formed at the transistor formation position at each height of the memory strings arranged in the first direction is electrically connected in a second direction perpendicular to the first direction across the semiconductor film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a wiring connected to a driving circuit of the transistor is connected to each of the divided gate electrode films.   The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor film operates as a channel of an Inversion type transistor. The gate dielectric film has a configuration in which a tunnel insulating film / charge trap film / charge block film are sequentially stacked,
The distance between the semiconductor films at the formation positions of all the transistors in the memory string adjacent in the first direction is greater than twice the film thickness of the tunnel insulating film and the charge trap film. The nonvolatile semiconductor memory device according to claim 1. The columnar semiconductor film is constituted by a hollow columnar semiconductor film,
The nonvolatile semiconductor memory device according to claim 1, wherein an insulating film is embedded in the hollow columnar semiconductor film.

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