KR100266028B1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- KR100266028B1 KR100266028B1 KR1019980021281A KR19980021281A KR100266028B1 KR 100266028 B1 KR100266028 B1 KR 100266028B1 KR 1019980021281 A KR1019980021281 A KR 1019980021281A KR 19980021281 A KR19980021281 A KR 19980021281A KR 100266028 B1 KR100266028 B1 KR 100266028B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract
본 발명은 반도체장치 및 그 제조방법에 관한 것으로서, 특히, LOCOS방법 등에 의하여 필드산화막을 형성하는 대신 반도체기판에 트렌치를 형성하고 일단의 활성영역이 이 트렌치내에 위치하도록 반도체소자를 형성하므로서 필드산화막과 같은 효과를 갖게 하여 필드산화막의 마진 확보 및 버즈 비크 현상을 방지하며 코아 부위와 주변부의 단차를 극복하도록한 반도체장치의 트렌지스터 및 그 제조방법에 관한 것이다. 이를 위하여 본 발명에 따른 반도체장치의 구조는 트렌치가 형성된 반도체기판과, 트렌치 표면을 포함하는 반도체기판 표면에 형성된 게이트절연막과, 트렌치 하부표면상에 위치하는 게이트절연막 상에 형성된 게이트와, 게이트 상부표면과 트렌치 외부에 위치하는 게이트절연막상에 위치하는 캡핑용절연막과, 게이트측면 하단부에 위치하는 반도체기판에 형성된 소스/드레인을 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, instead of forming a field oxide film by a LOCOS method or the like, a trench is formed in a semiconductor substrate and a semiconductor element is formed so that one end of an active region is located in the trench. The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, which have the same effect, to secure a margin of a field oxide film, to prevent a buzz beak phenomenon, and to overcome a step between a core part and a peripheral part. To this end, the structure of the semiconductor device according to the present invention includes a semiconductor substrate having a trench formed therein, a gate insulating film formed on the surface of the semiconductor substrate including the trench surface, a gate formed on the gate insulating film disposed on the lower surface of the trench, and a gate upper surface thereof. And a capping insulating film located on the gate insulating film outside the trench, and a source / drain formed on the semiconductor substrate located at the lower end of the gate side surface.
Description
본 발명은 반도체장치 및 그 제조방법에 관한 것으로서, 특히, LOCOS방법 등에 의하여 필드산화막을 형성하는 대신 반도체기판에 트렌치를 형성하고 일단의 활성영역이 이 트렌치내에 위치하도록 반도체소자를 형성하므로서 필드산화막과 같은 효과를 갖게 하여 필드산화막의 마진 확보 및 버즈 비크 현상을 방지하며 코아 부위와 주변부의 단차를 극복하도록한 반도체장치의 트렌지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, instead of forming a field oxide film by a LOCOS method or the like, a trench is formed in a semiconductor substrate and a semiconductor element is formed so that one end of an active region is located in the trench. The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, which have the same effect, to secure a margin of a field oxide film, to prevent a buzz beak phenomenon, and to overcome a step between a core part and a peripheral part.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 필드영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, the development of technology for reducing the field area occupying a considerable area of the semiconductor device is actively progressing.
일반적으로 반도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 격리하였다. LOCOS 방법은 활성영역을 한정하는 산화마스크인 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 버퍼산화막(buffer oxide)을 형성하고 산화시켜 필드영역으로 이용되는 필드산화막를 형성한다.In general, semiconductor devices have isolated devices by LOCOS (Local Oxidation of Silicon) method. The LOCOS method forms a thin film buffer oxide between the nitride film and the semiconductor substrate and oxidizes it to the field region to eliminate stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed.
그 후 활성영역에 트랜지스터 등의 소자를 형성하게 된다. 따라서 이와같이 제조되는 반도체장치는 필드산화막이 차지하는 면적이 전체 웨이퍼의 면적에서 과도한 면적을 차지하게 되고 구조적 특성상 주변부와 코아부의 단차가 필연적으로 발생하게 된다.After that, an element such as a transistor is formed in the active region. Therefore, in the semiconductor device manufactured as described above, the area occupied by the field oxide film occupies an excessive area in the area of the entire wafer, and a step between the peripheral part and the core part inevitably occurs due to its structural characteristics.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정단면도이다.1A to 1D are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art.
도 1a를 참조하면, 제 1 도전형 반도체기판(1) 상에 열산화 방법으로 버퍼산화막(2)을 형성하고, 이 버퍼산화막(2) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(3)을 형성한다. 그리고, 포토리쏘그래피(photolithography) 방법으로 마스크층(3)의 일부 표면이 노출되도록 포토레지스트패턴(4)을 형성한 다음 식각하여 마스크층(3) 및 버퍼산화막(2)을 선택적으로 제거하여 필드영역과 활성영역을 한정한다.Referring to FIG. 1A, a buffer oxide film 2 is formed on a first conductive semiconductor substrate 1 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 2. Silicon nitride is deposited to form a mask layer 3. Then, the photoresist pattern 4 is formed to expose a part of the surface of the mask layer 3 by photolithography and then etched to selectively remove the mask layer 3 and the buffer oxide film 2. Defines the area and active area.
그리고 채널저지용 이온주입을 제 1 도전형 불순물로 기판(1) 전면에 실시하여 노출된 마스크층(3) 표면 하부의 기판(1)내에 채널저지이온매몰층(도시안함)을 형성한다.The channel blocking ion implantation is performed on the entire surface of the substrate 1 with a first conductivity type impurity to form a channel blocking ion buried layer (not shown) in the substrate 1 under the exposed surface of the mask layer 3.
도 1b를 참조하면, 포토레지스트패턴(4)을 제거한 다음, 노출된 기판(1) 표면 즉, 노출된 필드영역을 산화하여 소정 두께의 필드산화막(5)을 형성한다. 이 때, 반도체기판(1)의 활성영역은 마스크층(3)에 의해 산화되지 않는다.Referring to FIG. 1B, after removing the photoresist pattern 4, the exposed surface of the substrate 1, that is, the exposed field region is oxidized to form a field oxide film 5 having a predetermined thickness. At this time, the active region of the semiconductor substrate 1 is not oxidized by the mask layer 3.
그리고 잔류한 질화막(3)과 버퍼산화막(2)을 제거한 다음 노출된 활성영역인 기판 표면을 열산화시켜 게이트산화막(6)을 형성한다.After the remaining nitride film 3 and the buffer oxide film 2 are removed, the gate oxide film 6 is formed by thermal oxidation of the exposed surface of the substrate.
도 1c를 참조하면, 게이트산화막(6)과 필드산화막(5)의 표면에 게이트를 형성하기 위하여 도핑된 폴리실리콘층(7)을 증착하여 형성한 다음, 그(7) 위에 캡핑용절연막(8)을 에이치엘디(HLD)로 형성한다.Referring to FIG. 1C, a doped polysilicon layer 7 is formed by depositing a gate oxide film 6 and a field oxide film 5 on the surfaces of the gate oxide film 6 and the field oxide film 5, and then a capping insulating film 8 is formed thereon. ) Is formed by HLD.
도 1d를 참조하면, 활성영역 상의 소정 부위에 게이트를 형성하기 위하여 사진식각공정을 실시하여 폴리실리콘층(7)과 캡핑용절연막(8)의 소정 부위를 선택적으로 제거하여 게이트(7)를 패터닝한다.Referring to FIG. 1D, the gate 7 is patterned by selectively removing a predetermined portion of the polysilicon layer 7 and the capping insulating layer 8 by performing a photolithography process to form a gate at a predetermined portion of the active region. do.
그 다음 기판(1)의 전면에 불순물 이온주입을 실시한 후 어닐링을 실시하여 소스/드레인(9)을 게이트(7) 측변 하부에 위치하는 기판부위에 형성한다.Then, after impurity ion implantation is performed on the entire surface of the substrate 1, annealing is performed to form the source / drain 9 on the substrate portion below the side of the gate 7.
이후, 도시되지는 아니하였으나 층간절연층과 콘택홀 및 배선을 형성하고 패시베이션층을 형성하여 트랜지스터를 완성한다.Subsequently, although not shown, an interlayer insulating layer, a contact hole and a wiring are formed, and a passivation layer is formed to complete the transistor.
그러나, 상술한 종래의 반도체장치 및 그 제조방법은 필드산화막 형성시 산화반응이 기판에 있어서 수직방향 뿐만 아니라 산화저지막인 질화막 하부로 즉 수평방향으로도 산소가 침투하여 산화반응이 일어나므로, 결국 활성영역이 감소하는 결과를 초래하게 되므로 소자영역이 감소하게 되어 고집적화가 곤란하고,또한 버즈 비크의 발생을 저지할 수 없는 문제점이 있다.However, in the above-described conventional semiconductor device and its manufacturing method, since the oxidation reaction occurs when the field oxide film is formed, the oxygen reaction penetrates not only in the vertical direction but also in the lower portion of the nitride film, that is, in the horizontal direction, in the substrate. Since the active area is reduced, the device area is reduced and high integration is difficult, and there is a problem in that occurrence of the buzz beak cannot be prevented.
따라서, 본 발명의 목적은 필드산화막 대신 트렌치를 형성하고 그 내부에 소자를 형성하므로서 일단의 활성영역이 하나의 트렌치 내부에 형성되게 하므로서 버즈빅에 의해 소자영역이 감소되고 주변부와 코아부의 단차를 극복할 수 있는 반도체장치 및 그 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to form a trench instead of a field oxide film and to form a device therein, thereby reducing the area of the device and reducing the periphery of the core and the core area by forming a group of active regions within one trench. A semiconductor device and a method of manufacturing the same are provided.
상기 목적을 달성하기 위해 본 발명에 따른 반도체장치의 구조는 트렌치가 형성된 반도체기판과, 트렌치 표면을 포함하는 반도체기판 표면에 형성된 게이트절연막과, 트렌치 하부표면상에 위치하는 게이트절연막 상에 형성된 게이트와, 게이트 상부표면과 트렌치 외부에 위치하는 게이트절연막상에 위치하는 캡핑용절연막과, 게이트측면 하단부에 위치하는 반도체기판에 형성된 소스/드레인을 포함하여 이루어진다.In order to achieve the above object, the structure of a semiconductor device according to the present invention includes a semiconductor substrate having a trench formed therein, a gate insulating film formed on the surface of the semiconductor substrate including the trench surface, a gate formed on the gate insulating film disposed on the lower surface of the trench; And a capping insulating film positioned on the gate upper surface and the gate insulating film outside the trench, and a source / drain formed on the semiconductor substrate located at the lower end of the gate side surface.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 반도체기판의 활성영역 형성 부위를 소정 깊이로 제거하여 트렌치를 형성하는 단계와, 트렌치 표면을 포함하는 반도체기판 표면에 게이트절연막을 형성하는 단계와, 트렌치를 매립하는 도전층을 트렌치 외부에 위치하는 게이트절연막의 표면과 동일평면상에 오도록 형성하는 단게와, 도전층과 노출된 게이트절연막의 표면에 캡절연막을 형성하는 단계와, 트렌치가 외부에 위치하는 캡절연막은 잔류시키고 동시에 트렌치 내부의 캡절연막과 도전층의 소정 부위를 제거하여 게이트를 패터닝하는 단계와, 게이트의 측변 하단에 위치한 반도체기판에 소스/드레인을 형성하는 단계를 포함하여 이루어진다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form a trench by removing the active region forming portion of the semiconductor substrate to a predetermined depth, and forming a gate insulating film on the surface of the semiconductor substrate including the trench surface And forming a cap insulating film on the surface of the conductive layer and the exposed gate insulating film, wherein the trench is formed so that the conductive layer filling the trench is coplanar with the surface of the gate insulating film located outside the trench. Patterning the gate by removing the cap insulating film and a predetermined portion of the conductive layer inside the trench while remaining outside the cap insulating film, and forming a source / drain on the semiconductor substrate at the lower side of the gate. Is done.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2는 본 발명에 따라 제조된 반도체장치의 구조단면도2 is a structural cross-sectional view of a semiconductor device manufactured according to the present invention.
도 3a 내지 도 3d는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정단면도3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
본 발명에서는 LOCOS 방식 등에 의한 필드산화막 형성 대신 트렌치를 형성하여 여기에 반도체소자를 형성하여 트랜지스터 등을 형성한다.In the present invention, instead of forming a field oxide film by a LOCOS method or the like, a trench is formed and a semiconductor device is formed thereon to form a transistor or the like.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따라 제조된 반도체장치의 구조단면도로서 하나의 트렌치 단위로 트랜지스터 등이 형성되어 있다.FIG. 2 is a structural cross-sectional view of a semiconductor device manufactured according to the present invention in which transistors and the like are formed in one trench unit.
도 2를 참조하면, 반도체기판(21)의 소정 부위가 제거되어 트렌치가 형성되어 있다. 트렌치를 포함하는 기판(21) 표면에는 게이트절연막(22)으로 게이트 산화막(22)이 형성되어 있다.트렌치 하부 표면에 위치하는 게이트절연막(22) 상에 게이트(23)가 위치하고 이러한 게이트(23) 상부 표면은 캡절연막(24)으로 덮혀있다. 그리고 트렌치를 제외한 기판(21) 표면에 위치하는 게이트 절연막(22) 상에도 역시 캡절연막(24)이 위치한다.Referring to FIG. 2, a predetermined portion of the semiconductor substrate 21 is removed to form a trench. A gate oxide film 22 is formed on the surface of the substrate 21 including the trench as a gate insulating film 22. The gate 23 is positioned on the gate insulating film 22 positioned on the lower surface of the trench. The upper surface is covered with a cap insulating film 24. The cap insulating film 24 is also located on the gate insulating film 22 positioned on the surface of the substrate 21 except for the trench.
게이트가 위치하지 않는 트렌치 하부에 위치한 기판(21)에는 게이트(23)를 중심으로 측면 하단에 소스/드레인(25)이 형성되어 있다.A source / drain 25 is formed at a lower side of the substrate 21 in the substrate 21 positioned below the trench where the gate is not located.
따라서 완성된 반도체 소자는 트렌치 단위로 이웃한 소자부와 격리되게 되어 별도의 필드산화막이 필요하지 아니하다. 또한, DRAM 소자 제조시에는 반도체소자의 상부 표면과 기판의 표면이 거의 동일 평면상에 위치하게 되어 코아부와 주변부의 단차가 거의 없게 된다.Therefore, the completed semiconductor device is isolated from the neighboring device parts in trench units, and thus a separate field oxide film is not required. In the manufacture of DRAM devices, the top surface of the semiconductor device and the surface of the substrate are positioned on substantially the same plane, so that there is almost no step between the core part and the peripheral part.
도 3a 내지 도 3d는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3a를 참조하면, 제 1 도전형 반도체기판(20) 상에 소자 활성영역이 형성될 기판 부위를 노출시키는 식각마스크(도시 안함)를 형성한 다음 식각마스크로 보호되지 아니하는 부위의 기판(21)을 소정 깊이로 제거하여 트렌치를 형성한다. 그리고 식각마스크를 제거한다.Referring to FIG. 3A, an etch mask (not shown) is formed on the first conductive semiconductor substrate 20 to expose a portion of the substrate on which the device active region is to be formed, and then the substrate 21 of the portion that is not protected by the etch mask. ) To a predetermined depth to form a trench. Then remove the etch mask.
트렌치의 내부 표면을 포함하는 기판(21) 표면에 열산화 방법으로 게이트절연막(22)으로 산화막(22)을 형성하고, 이 게이트절연용 산화막(22) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 게이트를 형성하기 위한 폴리실리콘층(23)을 증착한다. 이때 폴리실리콘층(23)은 도핑되지 아니하였으면 이후 소스/드레인 공정에서 도핑되어 도전성을 갖게 되거나, 처음부터 도핑된 폴리실리콘으로 형성한다. 그리고 증착 두께는 트렌치를 충분히 매립하는 두께로 증착하여 형성한다.On the surface of the substrate 21 including the inner surface of the trench, an oxide film 22 is formed by the gate insulating film 22 by a thermal oxidation method, and chemical vapor deposition is performed on the gate insulating oxide film 22. , A CVD method) to deposit a polysilicon layer 23 for forming a gate. In this case, the polysilicon layer 23 may be doped in a source / drain process to have conductivity, or may be formed of doped polysilicon from the beginning. The deposition thickness is formed by depositing a trench to sufficiently fill the trench.
그다음 폴리실리콘층(23)에 에치백을 실시하여 잔류한 폴리실리콘층(23) 표면과 트렌치가 형성되지 아니한 부위에 위치하는 게이트절연막(22) 표면이 동일 평면상에 위치하도록 평탄화작업을 실시한다. 이때, 에치백 대신 씨엠피공정을 실시하여 전체적인 평탄화를 달성할 수 있다.Then, the polysilicon layer 23 is etched back to planarize the remaining polysilicon layer 23 and the surface of the gate insulating film 22 positioned at the portion where no trench is formed. . In this case, the entire planarization may be achieved by performing CMP process instead of etch back.
도 3b를 참조하면, 잔류한 폴리실리콘층(23) 표면과 일부 노출된 게이트절연막(22) 표면에 캡핑용절연막(24)으로 에이치엘디층(24)을 형성한다.Referring to FIG. 3B, the HDL layer 24 is formed on the surface of the remaining polysilicon layer 23 and the partially exposed gate insulating layer 22 by the capping insulating layer 24.
캡핑용절연막(24) 상에 포토레지스트를 도포한 다음 게이트형성용 마스크를 이용한 사진공정을 실시하여 트렌치 내부에 게이트 형성부위와 트렌치가 위치하지 아니한 부위의 캡핑용절연막(24)만을 덮는 포토레지스트패턴(25)을 형성한다.A photoresist is applied on the capping insulating film 24 and then a photoresist using a gate forming mask is performed to cover only the capping insulating film 24 of the gate forming portion and the portion where the trench is not located in the trench. To form 25.
도 3c를 참조하면, 포토레지스트패턴(25)으로 보호되지 아니하는 부위의 캡핑용절연막(24)과 폴리실리콘층(23)을 게이트절연막(22)을 식각정지층으로 이용하는 이방성식각으로 제거하여 게이트(230를 패터닝한다.Referring to FIG. 3C, the capping insulating layer 24 and the polysilicon layer 23 of the portion not protected by the photoresist pattern 25 are removed by anisotropic etching using the gate insulating layer 22 as an etch stop layer. (Patterns 230.
도 3d를 참조하면, 노출된 게이트절연막(22)의 전면에 게이트(23)를 마스크로 이용하는 제 2 도전형 불순물 이온주입을 실시하여 트렌치 하부에 소스/드레인(25)을 형성한다.Referring to FIG. 3D, a second conductivity type impurity ion implantation using the gate 23 as a mask is applied to the entire surface of the exposed gate insulating layer 22 to form a source / drain 25 under the trench.
물론, 도시되지는 않았으나, 이때 제 2 도전형 불순물로 제 1 이온주입을 저농도로 하고 게이트 측면에 측벽을 형성한 다음 이를 이용하는 제 2 이온주입을 제 2 도전형 불순물로 고농도로 실시하면 엘디디(LDD) 구조를 갖는 소스/드레인을 형성한다.Of course, although not shown, when the first ion implantation is made low with the second conductivity type impurity, the sidewalls are formed on the side of the gate, and the second ion implantation using the second ion implantation with the second conductivity type impurity is performed. LDD) to form a source / drain having a structure.
따라서, 트랜지스터가 별도의 필드산화막 형성없이 트렌치에 의하여 이웃한 셀의 소자 등과 격리되고 완성된 소자의 표면단차가 거의 없게 된다.Therefore, the transistor is isolated from the elements of the neighboring cells by the trench without forming a separate field oxide film, and there is almost no surface step.
이후, 도시되지는 아니하였으나 층간절연층과 콘택홀 및 배선을 형성하고 패시베이션층을 형성하여 트랜지스터 드의 반도체장치를 제조한다.Subsequently, although not illustrated, an interlayer insulating layer, a contact hole and a wiring are formed, and a passivation layer is formed to manufacture a semiconductor device of the transistor.
따라서, 본 발명은 트렌치 단위로 활성영역간 격리를 이루므로서 종래기술인 LOCOS(local oxidation of silicon) 방식시 문제되는 3 차원으로 진행되는 산화반응현상인 버즈비크의 발생을 최소화할 수있고 따라서 소자의 활성영역을 최대한 확보할 수 있으므로 소자의 고집적화를 가능하게 하며, 또한 DRAM 소자 제조시에는 반도체소자의 상부 표면과 기판의 표면이 거의 동일 평면상에 위치하게 되어 코아부와 주변부의 단차를 제거하는 장점이 있다.Therefore, the present invention can minimize the occurrence of Buzzbee, which is an oxidation reaction that proceeds in three dimensions, which is a problem in the conventional local oxidation of silicon (LOCOS) method by forming isolation between active regions in the trench unit, and thus, device activation. As the area can be secured to the maximum, high integration of the device is possible, and when manufacturing a DRAM device, the upper surface of the semiconductor device and the surface of the substrate are located on substantially the same plane, thereby eliminating the step between the core part and the peripheral part. have.
Claims (7)
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