CN104078351A - Semiconductor structure manufacturing method - Google Patents
Semiconductor structure manufacturing method Download PDFInfo
- Publication number
- CN104078351A CN104078351A CN201410306980.8A CN201410306980A CN104078351A CN 104078351 A CN104078351 A CN 104078351A CN 201410306980 A CN201410306980 A CN 201410306980A CN 104078351 A CN104078351 A CN 104078351A
- Authority
- CN
- China
- Prior art keywords
- silicon nitride
- time
- etching technics
- nitride layer
- isolation structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 53
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 45
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000001039 wet etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 38
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000428 dust Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 37
- 229920005591 polysilicon Polymers 0.000 abstract description 37
- 238000000151 deposition Methods 0.000 abstract description 7
- 238000005429 filling process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 69
- 230000007547 defect Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000013064 process characterization Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
The invention provides a semiconductor structure manufacturing method which includes the steps of providing a semiconductor substrate, wherein a plurality of isolation structures are formed on the semiconductor substrate, active areas are arranged among the isolation structures, and each active area is sequentially provided with a buffer layer and a silicon nitride layer; carrying out etching for the first time and removing a part of the silicon nitride layers; carrying out wet etching to remove a part of isolation structures; carrying out etching for the second time after the wet process, removing remaining silicon nitride layers and exposing the buffer layers below; depositing polysilicon layers on the buffer layers among the isolation structures. The method can improve filling process quality of polysilicon, and solves the problems that the surfaces are concave after polysilicon filling and seams exist.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of manufacture method of semiconductor structure.
Background technology
Along with the development of semiconductor technology, the technology node of semiconductor technology constantly reduces, and the in the situation that of constant in gap, the characteristic size of active area constantly reduces.Make so just to cause the characteristic size of the silicon oxide layer of fleet plough groove isolation structure relatively to increase, the window that the polysilicon layer between fleet plough groove isolation structure is filled is more and more less.
Specifically please refer to the manufacture method cross-sectional view of the semiconductor structure of the prior art shown in Fig. 1 to Fig. 3.In Semiconductor substrate 10, be formed with fleet plough groove isolation structure 11, in the Semiconductor substrate 10 that between adjacent fleet plough groove isolation structure 11 is, be formed with successively silicon oxide layer 12 and silicon nitride layer 13.The material of described fleet plough groove isolation structure 11 is silica.Described silicon nitride layer 13 will be removed by etching technics follow-up.
Then, please refer to Fig. 2 and in conjunction with Fig. 1, carry out etching technics, remove silicon nitride layer 13.The etching technics of prior art utilizes phosphoric acid to carry out, and by described etching technics, removes silicon nitride layer 13.Between fleet plough groove isolation structure 11, form opening, expose silicon oxide layer 12.
Then, please refer to Fig. 3, the opening between fleet plough groove isolation structure 13 is filled polysilicon layer 14.Find that polysilicon is filled with defect, described defect comprises surface depression and gap.
Therefore, need a kind of manufacture method of semiconductor structure, can improve the processing quality that polysilicon is filled, solve surface depression and gap problem after polysilicon is filled.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of semiconductor structure, can improve the processing quality that polysilicon is filled, and solves surface depression and gap problem after polysilicon is filled.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor structure, comprising:
Semiconductor substrate being provided, being formed with some isolation structures in described Semiconductor substrate, is active region between isolation structure, is formed with successively resilient coating, silicon nitride layer on described active region;
Carry out etching technics for the first time, remove part silicon nitride layer;
Carry out wet-etching technology, remove part isolation structure;
After described wet processing, carry out etching technics for the second time, remove remaining silicon nitride layer, expose the resilient coating of below;
Deposit spathic silicon layer on the resilient coating between described isolation structure.
Alternatively, the material of described isolation structure is silica, and the material of described resilient coating is silica.
Alternatively, described etching technics for the first time utilizes phosphoric acid solution to carry out, and described etching technics for the second time utilizes phosphoric acid solution to carry out.
Alternatively, the temperature range of the described phosphoric acid solution of etching technics is for the first time 120-180 ℃, and the temperature range of the phosphoric acid solution of described etching technics is for the second time 120-180 ℃.
Alternatively, the concentration range of the described phosphoric acid solution of etching technics is for the first time 90%-96%, and the concentration range of the phosphoric acid solution of described etching technics is for the second time 90%-96%.
Alternatively, the thickness of the silicon nitride layer that described etching technics is for the first time removed accounts for the 1/6-2/3 of the thickness of the silicon nitride layer not being etched, and the thickness of the silicon nitride layer that etching technics is removed for the second time accounts for the 1/3-5/6 of the thickness of the silicon nitride layer not being etched.
Alternatively, described wet-etching technology utilizes hydrofluoric acid to carry out.
The thickness range of the isolation structure that alternatively, described wet-etching technology is removed is 70-130 dust.
Compared with prior art, the present invention has the following advantages:
The manufacture method of semiconductor structure provided by the invention, silicon nitride layer is carried out to etching technics and for the second time etching technics for the first time, between twice etching technique, increase wet-etching technology, utilize described wet-etching technology to remove part isolation structure (thickness of the isolation structure of removal is less), object is to make the top of isolation structure more round and smooth, expanded the filling opening of polysilicon layer, make polysilicon layer be more prone to fill, reduce the various defects that occur in polysilicon layer filling process.
Accompanying drawing explanation
The manufacture method cross-sectional view of the semiconductor structure of the prior art that Fig. 1 to Fig. 3 is.
Fig. 4-Fig. 7 is the manufacture method cross-sectional view of the semiconductor structure of one embodiment of the invention.
Embodiment
Prior art is found the polysilicon layer defectiveness of filling when polysilicon fill process.In conjunction with Fig. 2 and Fig. 3, technology node reduction due to semiconductor device, the characteristic size of fleet plough groove isolation structure 11 structures increases, opening between isolation structure 11 reduces relatively, thereby make the difficulty that polysilicon layer is filled become large, easily make the defect such as generation surface depression and gap on polysilicon layer 11.Traditional technology adopts the method for reduction silicon nitride layer to increase the filling opening of polysilicon layer, but reduce the height of silicon nitride layer, also can cause the height of the polysilicon layer 14 of filling to decline thereupon, affect follow-up multi crystal silicon chemical mechanical milling step, cannot guarantee the height of polysilicon layer chemical mechanical milling tech polysilicon layer afterwards.
In order to address the above problem, the present invention proposes a kind of manufacture method of semiconductor structure, can be when not reducing the height of silicon nitride layer, expand the filling opening of polysilicon layer, make the top of fleet plough groove isolation structure 11 rounder and more smooth, be more prone to fill polysilicon layer, reduce the various defects that occur in polysilicon layer filling process.Method of the present invention, silicon nitride layer etching technics is divided into two steps, between two Nitride Strip Process Characterization steps, increase an etching technics step, be used for removing part fleet plough groove isolation structure, make the top of fleet plough groove isolation structure more round and smooth, and the top of fleet plough groove isolation structure is more round and smooth.
Particularly, the manufacture method of semiconductor structure of the present invention comprises:
Semiconductor substrate being provided, being formed with some isolation structures in described Semiconductor substrate, is active region between isolation structure, is formed with successively resilient coating, silicon nitride layer on described active region;
Carry out etching technics for the first time, remove part silicon nitride layer;
Carry out wet-etching technology, remove part isolation structure;
After described wet processing, carry out etching technics for the second time, remove remaining silicon nitride layer, expose the resilient coating of below;
Deposit spathic silicon layer on the resilient coating between described isolation structure.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.For technical scheme of the present invention is described better, please refer to Fig. 4-Fig. 7 is the manufacture method cross-sectional view of the semiconductor structure of one embodiment of the invention.
First, please refer to Fig. 4, Semiconductor substrate 100 is provided, be formed with some isolation structures 110 in described Semiconductor substrate 100, is active region between isolation structure 110, is formed with successively resilient coating 120, silicon nitride layer 130 on described active region.As an embodiment, described isolation structure 110 is fleet plough groove isolation structure, and the material of described isolation structure 110 is silica.The material of described resilient coating 120 is silica.
Then, please refer to Fig. 5, carry out etching technics for the first time, remove part silicon nitride layer 130, the present invention removes silicon nitride layer 130 by twice etching technique, remove for the first time part silicon nitride layer, for the second time remaining silicon nitride layer is removed, between twice silicon nitride layer etching technics, increase by one and isolation structure is carried out to the processing step of wet etching with the height of inching isolation structure 110, make isolation structure more round and smooth, and increase the size of the opening of subsequent deposition polysilicon layer.For the first time after etching technics, the part silicon nitride layer 130 of reservation is using as the follow-up protective layer that isolation structure 110 is carried out to wet-etching technology, and the resilient coating 120 of protection below avoids being subject to the damage of described wet-etching technology.
As an embodiment, described etching technics for the first time utilizes phosphoric acid solution to carry out, and the temperature range of the described phosphoric acid solution of etching technics is for the first time 120-180 ℃, and the concentration range of the described phosphoric acid solution of etching technics is for the first time 90%-96%.The thickness of the silicon nitride layer that described etching technics is for the first time removed accounts for the 1/6-2/3 of the thickness of the silicon nitride layer not being etched.
Then, please refer to Fig. 6 and in conjunction with Fig. 5, carry out wet-etching technology, remove part isolation structure 110.The object of described wet-etching technology is to adjust isolation structure 110 height, object is that to adjust the pattern at top of isolation structure 110 more round and smooth, to expand the width of active region, increase the size of the opening of polysilicon layer deposition, in the situation that not regulating silicon nitride layer height, expand the process window of polysilicon layer deposition, avoid polysilicon layer deposition defect.
As an embodiment, described wet-etching technology utilizes hydrofluoric acid to carry out.The thickness range of the isolation structure 110 that described wet-etching technology is removed is 70-130 dust.
Through described wet-etching technology, the height of isolation structure 110 slightly reduces, and the top of isolation structure 110 is more round and smooth, to increase the width of active region, expanded the opening of polysilicon layer deposition, make polysilicon layer be more prone to fill, can effectively reduce the various defects that occur in polysilicon layer filling process.
Then, please continue to refer to Fig. 6, and in conjunction with Fig. 5, after described wet processing, carry out etching technics for the second time, remove remaining silicon nitride layer 130, the resilient coating 120 that exposes below, the opening of resilient coating 120 tops between described isolation structure 110 is for follow-up filling polysilicon layer.
As an embodiment, described etching technics for the second time utilizes phosphoric acid solution to carry out.The temperature range of the phosphoric acid solution of described etching technics is for the second time 120-180 ℃.The concentration range of the phosphoric acid solution of described etching technics is for the second time 90%-96%.The thickness of the silicon nitride layer that etching technics is removed for the second time accounts for the 1/3-5/6 of the thickness of the silicon nitride layer not being etched.
Then, please refer to Fig. 7, deposit spathic silicon layer 140 on the resilient coating 120 between described isolation structure 110.Owing to utilizing twice etching technique, silicon nitride layer is carried out to etching, and between the etching technics of twice silicon nitride layer, increase the etching technics to isolation structure, adjust the pattern of isolation structure 110, expanded the opening of polysilicon layer 140, made polysilicon layer 140 be more prone to deposition.
To sum up, the manufacture method of semiconductor structure provided by the invention, silicon nitride layer is carried out to etching technics and for the second time etching technics for the first time, between twice etching technique, increase wet-etching technology, utilize described wet-etching technology to remove part isolation structure, reduced the height of isolation structure, make the top of isolation structure more round and smooth, expanded the filling opening of polysilicon layer, made polysilicon layer be more prone to fill, reduced the various defects that occur in polysilicon layer filling process.
Therefore, above-mentioned preferred embodiment is only explanation technical conceive of the present invention and feature, and its object is to allow person skilled in the art can understand content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, within all should being encompassed in protection scope of the present invention.
Claims (8)
1. a manufacture method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate being provided, being formed with some isolation structures in described Semiconductor substrate, is active region between isolation structure, is formed with successively resilient coating, silicon nitride layer on described active region;
Carry out etching technics for the first time, remove part silicon nitride layer;
Carry out wet-etching technology, remove part isolation structure;
After described wet processing, carry out etching technics for the second time, remove remaining silicon nitride layer, expose the resilient coating of below;
Deposit spathic silicon layer on the resilient coating between described isolation structure.
2. the manufacture method of semiconductor structure as claimed in claim 1, is characterized in that, the material of described isolation structure is silica, and the material of described resilient coating is silica.
3. the manufacture method of semiconductor structure as claimed in claim 1, is characterized in that, described etching technics for the first time utilizes phosphoric acid solution to carry out, and described etching technics for the second time utilizes phosphoric acid solution to carry out.
4. the manufacture method of semiconductor structure as claimed in claim 3, is characterized in that, the temperature range of the described phosphoric acid solution of etching technics is for the first time 120-180 ℃, and the temperature range of the phosphoric acid solution of described etching technics is for the second time 120-180 ℃.
5. the manufacture method of semiconductor structure as claimed in claim 3, is characterized in that, the concentration range of the described phosphoric acid solution of etching technics is for the first time 90%-96%, and the concentration range of the phosphoric acid solution of described etching technics is for the second time 90%-96%.
6. the manufacture method of semiconductor structure as claimed in claim 1, it is characterized in that, the thickness of the silicon nitride layer that described etching technics is for the first time removed accounts for the 1/6-2/3 of the thickness of the silicon nitride layer not being etched, and the thickness of the silicon nitride layer that etching technics is removed for the second time accounts for the 1/3-5/6 of the thickness of the silicon nitride layer not being etched.
7. the manufacture method of semiconductor structure as claimed in claim 1, is characterized in that, described wet-etching technology utilizes hydrofluoric acid to carry out.
8. the manufacture method of semiconductor structure as claimed in claim 1, is characterized in that, the thickness range of the isolation structure that described wet-etching technology is removed is 70-130 dust.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410306980.8A CN104078351A (en) | 2014-06-30 | 2014-06-30 | Semiconductor structure manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410306980.8A CN104078351A (en) | 2014-06-30 | 2014-06-30 | Semiconductor structure manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104078351A true CN104078351A (en) | 2014-10-01 |
Family
ID=51599539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410306980.8A Pending CN104078351A (en) | 2014-06-30 | 2014-06-30 | Semiconductor structure manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104078351A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| CN110610856A (en) * | 2019-09-20 | 2019-12-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN115360193A (en) * | 2022-10-21 | 2022-11-18 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211846A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | On-chip system device thick grating oxide layer preparation method |
| CN102064128A (en) * | 2009-11-18 | 2011-05-18 | 上海华虹Nec电子有限公司 | Method for improving rounding of shallow trench isolation top angle by twice back-etching on silicon nitride |
| CN102117761A (en) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | Wet process method for improving chamfer smoothness on top of shallow trench isolation |
| CN102339782A (en) * | 2010-07-16 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Production method of shallow channel isolation region |
| CN103187258A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for removing silicon nitride layer in floating gate manufacturing process |
-
2014
- 2014-06-30 CN CN201410306980.8A patent/CN104078351A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211846A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | On-chip system device thick grating oxide layer preparation method |
| CN102064128A (en) * | 2009-11-18 | 2011-05-18 | 上海华虹Nec电子有限公司 | Method for improving rounding of shallow trench isolation top angle by twice back-etching on silicon nitride |
| CN102117761A (en) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | Wet process method for improving chamfer smoothness on top of shallow trench isolation |
| CN102339782A (en) * | 2010-07-16 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Production method of shallow channel isolation region |
| CN103187258A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for removing silicon nitride layer in floating gate manufacturing process |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| US10784117B2 (en) | 2018-05-23 | 2020-09-22 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Defect relieving method for floating gate, and semiconductor structure |
| CN110610856A (en) * | 2019-09-20 | 2019-12-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN115360193A (en) * | 2022-10-21 | 2022-11-18 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115360193B (en) * | 2022-10-21 | 2023-01-31 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9269820B2 (en) | Manufacturing method of polysilicon layer, and polysilicon thin film transistor and manufacturing method thereof | |
| US10192776B1 (en) | Manufacturing method of a flash wafer | |
| CN104078351A (en) | Semiconductor structure manufacturing method | |
| CN105118775A (en) | A shield grid transistor formation method | |
| WO2017048259A8 (en) | Methods for doping a sub-fin region of a semiconductor fin structure and devices containing the same | |
| CN102361007A (en) | Method for etching groove and semiconductor device | |
| CN104867826A (en) | Method for preventing thin film at edge of silicon chip from being peeled off | |
| CN106601687B (en) | Semiconductor device, preparation method thereof and electronic device | |
| CN103123912A (en) | Method for manufacturing top gate TFT (thin film transistor) array substrate | |
| CN102820260A (en) | Method for improving via hole pattern performance expression | |
| CN103839868A (en) | Manufacturing method for shallow-trench isolation structure | |
| TWI521643B (en) | Contact structure for a deep trench capacitor and method for manufacturing the same | |
| CN103996603A (en) | Self-alignment double-layer figure semiconductor structure manufacturing method | |
| CN104701184A (en) | Method for forming field emission transistor with multi-fin structure | |
| CN106783859A (en) | A kind of floating boom generation method, flash memory floating gate generation method and flash memory fabrication method | |
| CN102270607B (en) | Method for manufacturing grid stack and semiconductor device | |
| CN105720105A (en) | Bottom gate type thin film transistor and preparation method thereof | |
| CN110473775A (en) | Improve the method for film removing | |
| CN105097709B (en) | The forming method of flash memory | |
| CN103177955B (en) | A kind of manufacturing method thereof realizing peelable sidewall | |
| CN109817625B (en) | Word line polysilicon blocking oxide layer and manufacturing method thereof | |
| US10211107B1 (en) | Method of fabricating fins including removing dummy fins after fluorocarbon flush step and oxygen clean step | |
| CN104425354A (en) | Method for manufacturing shallow trench isolation structure | |
| CN105006432A (en) | Method for reducing the damage to a substrate surface in ONO etching | |
| CN105405769A (en) | Thin film transistor component and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141001 |