CN105006432A - Method for reducing the damage to a substrate surface in ONO etching - Google Patents

Method for reducing the damage to a substrate surface in ONO etching Download PDF

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Publication number
CN105006432A
CN105006432A CN201510490463.5A CN201510490463A CN105006432A CN 105006432 A CN105006432 A CN 105006432A CN 201510490463 A CN201510490463 A CN 201510490463A CN 105006432 A CN105006432 A CN 105006432A
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CN
China
Prior art keywords
ono
substrate surface
coating
surface damage
oxide skin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510490463.5A
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Chinese (zh)
Inventor
吴亚贞
刘宪周
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201510490463.5A priority Critical patent/CN105006432A/en
Publication of CN105006432A publication Critical patent/CN105006432A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

The invention provides a method reducing the damage to a substrate surface in ONO etching. The method comprises following steps; the first step, of depositing on a substrate successively a first oxide layer, a nitride layer and a second oxide layer to form an ONO structure on the substrate; the second step, of processing the ONO structure by the method of lithography and dry etching to expose the substrate surface; the third step, perform thermal oxidation treatment on the semiconductor structure after the second step to form a thermal oxidation layer on the surface of the semiconductor structure; the fourth step, of removing the thermal oxidation layer by a wet etching process.

Description

A kind of method reducing substrate surface damage in ONO etching
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of method reducing substrate surface damage in ONO etching.
Background technology
ONO (Oxide-Nitride-Oxide, oxide/nitride/oxide) structure is the structure of often encountering in fabrication of semiconductor device.And, often need to deposit ONO structure and etch in fabrication of semiconductor device.
Fig. 1 and Fig. 2 schematically shows the ONO etch step according to prior art.As depicted in figs. 1 and 2, on substrate 10 (being generally silicon substrate), successive sedimentation successively first oxide skin(coating) 21, nitride layer 22 and the second oxide skin(coating) 23 is first deposited, to form ONO structure over the substrate 10.Subsequently ONO structure is etched, thus expose section substrate surface 11.
But present Problems existing is, if the first oxide skin(coating) 21 of ONO structural base is too thin, then the section substrate surface 11 exposed is damaged due to undue dry etching possibly.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of method that section substrate surface that can prevent or reduce exposure is damaged by dry etching.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of method reducing substrate surface damage in ONO etching, comprising:
First step: at deposited on substrates successively successive sedimentation first oxide skin(coating), nitride layer and the second oxide skin(coating), to form ONO structure on substrate;
Second step: photoetching and dry etching are carried out to ONO structure, thus expose section substrate surface;
Third step: carry out thermal oxidation to the semiconductor structure after second step, to form thermal oxide layer at semicon-ductor structure surface;
4th step: utilize wet etching to remove thermal oxide layer.
Preferably, the thickness of described first oxide skin(coating) is between 18 ~ 25A.
Preferably, the thickness of described second oxide skin(coating) is between 140 ~ 255A.
Preferably, the thickness of described nitride layer is between 80 ~ 110A.
Preferably, the material of described first oxide skin(coating) and described second oxide skin(coating) is silicon dioxide.
Preferably, the material of described nitride layer is silicon nitride.
Preferably, described substrate is silicon substrate.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 and Fig. 2 schematically shows the ONO etch step according to prior art.
Fig. 3 schematically shows the flow chart of the method reducing substrate surface damage in ONO etching according to the preferred embodiment of the invention.
Fig. 4 to Fig. 7 schematically shows each step of the method reducing substrate surface damage in ONO etching according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 3 schematically shows the flow chart of the method reducing substrate surface damage in ONO etching according to the preferred embodiment of the invention.And Fig. 4 to Fig. 7 schematically shows each step of the method reducing substrate surface damage in ONO etching according to the preferred embodiment of the invention.
Present composition graphs 4 to Fig. 7 is also described with reference to Figure 3 the method reducing substrate surface damage in ONO etching according to the preferred embodiment of the invention.
The method reducing substrate surface damage in ONO etching according to the preferred embodiment of the invention comprises:
First step S1: first deposit successive sedimentation successively first oxide skin(coating) 21, nitride layer 22 and the second oxide skin(coating) 23 on substrate 10 (being generally silicon substrate), to form ONO structure over the substrate 10, as shown in Figure 4;
Preferably, the thickness of described first oxide skin(coating) 21 is between 18 ~ 25A.Preferably, the thickness of described second oxide skin(coating) 23 is between 140 ~ 255A.Preferably, the thickness of described nitride layer 22 is between 80 ~ 110A.The gross thickness of the oxide on nitride layer 22 is 140 ~ 255A.
Preferably, the material of described first oxide skin(coating) 21 and described second oxide skin(coating) 23 is silicon dioxide.Preferably, the material of described nitride layer 22 is silicon nitrides.
Second step S2: photoetching and dry etching are carried out to ONO structure, thus expose section substrate surface 11, as shown in Figure 5;
Third step S3: thermal oxidation is carried out to the semiconductor structure (structure namely shown in Fig. 2) after second step S2, to form thermal oxide layer 30 at semicon-ductor structure surface, as shown in Figure 6;
The thermal oxidation of third step S3 can be repaired the silicon face forming device, because in the ONO etching of second step S2, the thickness of bottom oxide is very thin, and silicon face may be damaged because of etching, and the thermal oxidation of third step S3 can be repaired damage.
4th step S4: utilize wet etching to remove thermal oxide layer 30, as shown in Figure 7.Wet etching can reduce the thickness of the oxide on nitride layer 22, makes the thickness of the oxide on nitride layer 22 reduce to roughly 40 ~ 55A originally thus.
According to the present invention, the damage that the section substrate surface that can prevent or reduce exposure is caused by dry etching.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.

Claims (8)

1. reduce a method for substrate surface damage in ONO etching, it is characterized in that comprising:
First step: at deposited on substrates successively successive sedimentation first oxide skin(coating), nitride layer and the second oxide skin(coating), to form ONO structure on substrate;
Second step: photoetching and dry etching are carried out to ONO structure, thus expose section substrate surface;
Third step: carry out thermal oxidation to the semiconductor structure after second step, to form thermal oxide layer at semicon-ductor structure surface;
4th step: utilize wet etching to remove thermal oxide layer.
2. the method for substrate surface damage in minimizing ONO etching according to claim 1, it is characterized in that, the thickness of described first oxide skin(coating) is between 18 ~ 25A.
3. the method for substrate surface damage in minimizing ONO etching according to claim 1 and 2, it is characterized in that, the thickness of described second oxide skin(coating) is between 140 ~ 255A.
4. the method for substrate surface damage in minimizing ONO etching according to claim 1 and 2, it is characterized in that, the thickness of described nitride layer is between 80 ~ 110A.
5. the method for substrate surface damage in minimizing ONO etching according to claim 1 and 2, it is characterized in that, the material of described first oxide skin(coating) is silicon dioxide.
6. the method for substrate surface damage in minimizing ONO etching according to claim 1 and 2, it is characterized in that, the material of described second oxide skin(coating) is silicon dioxide.
7. the method for substrate surface damage in minimizing ONO etching according to claim 1 and 2, it is characterized in that, the material of described nitride layer is silicon nitride.
8. the method for substrate surface damage in minimizing ONO etching according to claim 1 and 2, it is characterized in that, described substrate is silicon substrate.
CN201510490463.5A 2015-08-11 2015-08-11 Method for reducing the damage to a substrate surface in ONO etching Pending CN105006432A (en)

Priority Applications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108054080A (en) * 2017-11-30 2018-05-18 武汉新芯集成电路制造有限公司 A kind of method in acquisition thermal oxide layer on substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6723638B1 (en) * 2003-02-05 2004-04-20 Advanced Micro Devices, Inc. Performance in flash memory devices
CN101587864A (en) * 2008-05-23 2009-11-25 中芯国际集成电路制造(北京)有限公司 Nrom device and manufacturing method thereof
CN102064101A (en) * 2009-11-18 2011-05-18 上海华虹Nec电子有限公司 Method for restraining gate electrode injection by using P-type polysilicon electrode
CN102280378A (en) * 2011-08-31 2011-12-14 上海宏力半导体制造有限公司 SONOS structure and SONOS memory formation method
CN102456572A (en) * 2010-10-18 2012-05-16 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device structure comprising stress layer
CN102810481A (en) * 2011-06-02 2012-12-05 中芯国际集成电路制造(北京)有限公司 Manufacturing method of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6723638B1 (en) * 2003-02-05 2004-04-20 Advanced Micro Devices, Inc. Performance in flash memory devices
CN101587864A (en) * 2008-05-23 2009-11-25 中芯国际集成电路制造(北京)有限公司 Nrom device and manufacturing method thereof
CN102064101A (en) * 2009-11-18 2011-05-18 上海华虹Nec电子有限公司 Method for restraining gate electrode injection by using P-type polysilicon electrode
CN102456572A (en) * 2010-10-18 2012-05-16 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device structure comprising stress layer
CN102810481A (en) * 2011-06-02 2012-12-05 中芯国际集成电路制造(北京)有限公司 Manufacturing method of semiconductor device
CN102280378A (en) * 2011-08-31 2011-12-14 上海宏力半导体制造有限公司 SONOS structure and SONOS memory formation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108054080A (en) * 2017-11-30 2018-05-18 武汉新芯集成电路制造有限公司 A kind of method in acquisition thermal oxide layer on substrate
CN108054080B (en) * 2017-11-30 2019-11-01 武汉新芯集成电路制造有限公司 A method of in acquisition thermal oxide layer on substrate

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