CN106409662A - Silicide-damage-free stress approaching technology etching method - Google Patents
Silicide-damage-free stress approaching technology etching method Download PDFInfo
- Publication number
- CN106409662A CN106409662A CN201610985909.6A CN201610985909A CN106409662A CN 106409662 A CN106409662 A CN 106409662A CN 201610985909 A CN201610985909 A CN 201610985909A CN 106409662 A CN106409662 A CN 106409662A
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- Prior art keywords
- protection layer
- layer film
- stress
- side wall
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000005516 engineering process Methods 0.000 title claims abstract description 39
- 238000005530 etching Methods 0.000 title claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 61
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 81
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 230000009969 flowable effect Effects 0.000 claims description 6
- 239000012528 membrane Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 41
- 230000008569 process Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- -1 silicide metals Chemical class 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
Abstract
The invention provides a silicide-damage-free stress approaching technology etching method. The method comprises: step one, a source electrode and a drain electrode are formed in a substrate, a gate having a side wall 30 is formed on the substrate, and metal silicide is formed on the surfaces of the gate, the source electrode, and the drain electrode; step two, a protection layer film is deposited, wherein the protection layer film on the side wall is thinner than the protection layer film arranged on the metal silicide formed on the surfaces of the gate, the source electrode, and the drain electrode; step three, stress-approaching-technology-based etching is carried out with the etching time matching the thickness of the protection layer film and thus the protection layer film on the side wall is removed completely, wherein the side wall thickness is reduced; and the protection layer film on the metal silicide formed on the surfaces of the gate, the source electrode, and the drain electrode is thinned to form a reduced protection layer film; and step four, a high-stress film is deposited.
Description
Technical field
A kind of the present invention relates to field of semiconductor manufacture, it is more particularly related to the stress that no silicide damages
Close on technology lithographic method.
Background technology
The reducing of development with CMOS integrated circuit fabrication process and critical size, much new method is applied to
In device fabrication, in order to improve device performance.
Heavily stressed contact through hole etching barrier layer (high stress CESL) is by applying stress, Neng Gouyou at raceway groove
Effect improves the performance of device, has been widely used for below 65nm chip manufacturing process.And device performance lifting degree with thin
The stress of film itself, thickness, and the degree of closeness of raceway groove has direct relation.Industry stress film be positioned over closer to
The method of raceway groove is called stress and closes on technology (SPT：Stress Proximity Technology).Heavily stressed silicon nitride film
Application include on the semiconductor device as contact through hole etching barrier layer.And so-called SPT technology, actually will
Side wall between stress silicon nitride and grid becomes thinner, allows stress silicon nitride more with raceway groove closer to so having and become apparent from
Device performance reinforced effects.
Traditional SPT techniqueflow, after metal silicide formation, performs etching to side wall sealing coat.In this process
In, because metal silicide is exposed in the middle of etching atmosphere, so silicide certainly exists certain damage, final result is anti-
Reflect on device is that resistance becomes big.It should be noted that in order to avoid the damage of silicide is too serious, the removal amount of side wall also will
It is controlled.So be commonly seen is all that offside wall silicon nitride layer carries out partial etching, rather than remove completely.Although from increasing
The angle of strong stress is said, the spacer medium of side wall is removed completely and is more beneficial for device performance.
Content of the invention
The technical problem to be solved is that there is drawbacks described above in prior art, provides one kind no silicide
The stress damaging closes on technology lithographic method.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided the stress that a kind of no silicide damages closes on technology
Lithographic method, including：
First step：Form source electrode and drain electrode in the substrate, and form the grid with side wall 30 on substrate, and
Form metal silicide on the surface of grid, source electrode and drain electrode；
Second step：Deposition protection layer film, the protection layer film on the wall of side wall side compares the table of grid, source electrode and drain electrode
The protection layer film on metal silicide being formed on face is thinner；
Third step：Carry out stress close on technology etching, wherein etch period with protection layer film thickness cooperation so that
Protection layer film on the wall of side wall side is completely removed, and side wall thicknesses are thinning, and on the surface of grid, source electrode and drain electrode
Protection layer film on the metal silicide being formed is thinned to form thinning protection layer film；
Four steps：Deposit heavily stressed thin film.
Preferably, described side wall is the sidewall spacers comprising silicon oxide and silicon nitride film.
Preferably, protection layer film is deposited using high-density plasma silicon oxide deposition technique.
Preferably, protection layer film is deposited using flowable chemical vapor deposition method.
Preferably, heavily stressed thin film is heavily stressed silicon nitride film, the membrane stress of heavily stressed silicon nitride film between-
Between 3.5Gpa to+2Gpa.
In order to realize above-mentioned technical purpose, according to the present invention, additionally provide a kind of stress of no silicide damage and close on skill
Art lithographic method, including：
First step：Form source electrode and drain electrode in the substrate, and form the grid with side wall 30 on substrate, and
Form metal silicide on the surface of grid, source electrode and drain electrode；
Second step：Deposition protection layer film, the protection layer film on the wall of side wall side compares the table of grid, source electrode and drain electrode
The protection layer film on metal silicide being formed on face is thinner；
Third step：Carry out stress close on technology etching, wherein etch period with protection layer film thickness cooperation so that
The protective layer on metal silicide being formed on the surface of the protection layer film on the wall of side wall side and grid, source electrode and drain electrode is thin
Film is completely removed, and side wall thicknesses are thinning；
Four steps：Deposit heavily stressed thin film.
Preferably, described side wall is the sidewall spacers comprising silicon oxide and silicon nitride film.
Preferably, protection layer film is deposited using high-density plasma silicon oxide deposition technique.
Preferably, protection layer film is deposited using flowable chemical vapor deposition method.
Preferably, heavily stressed thin film is heavily stressed silicon nitride film, the membrane stress of heavily stressed silicon nitride film between-
Between 3.5Gpa to+2Gpa.
The present invention proposes a kind of it can be avoided that the stress that metal silicide damages closes on technology, it can be avoided that or reducing side
The damage to silicide for the wall etching process, and then improve the performance of semiconductor device.
Brief description
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features are more easily understood, wherein：
The stress that Fig. 1 schematically shows no silicide damage according to the preferred embodiment of the invention closes on technology etching
The first step of method.
The stress that Fig. 2 schematically shows no silicide damage according to the preferred embodiment of the invention closes on technology etching
The second step of method.
The stress that Fig. 3 schematically shows no silicide damage according to the preferred embodiment of the invention closes on technology etching
The third step of method.
The stress that Fig. 4 schematically shows no silicide damage according to the preferred embodiment of the invention closes on technology etching
The four steps of method.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
The present invention proposes a kind of it can be avoided that the stress that metal silicide damages closes on technology, provides and has formed grid knot
Structure simultaneously completes the substrate of silicification technics, has side wall sealing coat between grid and source drain silicide metals.Carrying out side wall
Before sealing coat reduction process, first pass through specific thin film deposition processes and certain thickness protective film, institute are formed on wafer
State protective film thicker in silicide regions thickness, thickness is thinner on side wall, then carry out side wall etching again.By above-mentioned side
Method, it can be avoided that the damage to silicide for the side wall etching process, and then improve the performance of semiconductor device.
The preferred embodiments of the present invention are described below.
<First embodiment>
The stress that Fig. 1 to Fig. 4 schematically shows the no silicide damage according to first preferred embodiment of the invention faces
Each step of nearly technology lithographic method.
As shown in Figures 1 to 4, the stress that the no silicide according to first preferred embodiment of the invention damages closes on technology and carves
Etching method includes：
First step：Form source electrode 10 and drain electrode 20 in substrate 100, and formation has side wall 30 on the substrate 100
Grid, and grid, source electrode 10 and drain electrode 20 surface formed metal silicide 40；
Typically, described side wall 30 is the sidewall spacers comprising silicon oxide and silicon nitride film.It is further preferred that it is described
The overall width of side wall 30 is 200-500A.
Second step：Deposition protection layer film 50, the protection layer film on side wall 30 side wall compares grid, source electrode 10 and leakage
The protection layer film on metal silicide 40 being formed on the surface of pole 20 is thinner；
Preferably, can be using HDP (high-density plasma) silicon oxide deposition technique and FCVD (flowable chemistry gas
Phase depositing operation protects layer film 50 to deposit.For example, protection layer film 50 is silicon oxide film or silicon nitride film.With HDP work
As a example skill, can be implemented in top portions of gates and the thickness of source drain by processing procedure regulation is 300-500A, but in side wall
On thickness be less than 100A.
Third step：Carry out stress close on technology etching, wherein etch period with protection layer film thickness cooperation so that
Protection layer film 50 on side wall 30 side wall is completely removed, and side wall 30 is thinned as thinning side wall 31, and grid,
Protection layer film on the metal silicide 40 being formed on the surface of source electrode 10 and drain electrode 20 is thinned to form thinning protection
Layer film 51；
For example, when the silicon oxide film on metal silicide consumes 300A, metal silicide does not also expose, but side
The spacer medium layer of wall has consumed 200A.
Four steps：Deposit heavily stressed thin film 60.Typically, heavily stressed thin film 60 can be heavily stressed silicon nitride film, thin
The change that membrane stress can pass through process parameter is adjusted between -3.5Gpa to+2Gpa.
If it is emphasized that the damage of metal silicide will be avoided completely, protection layer film is permissible in SPT etching
Not exclusively remove, will remaining protection layer film be retained on final product.Can certainly select to remove it completely
(seeing below continuous second embodiment), although so silicide layer can damage, for comparing traditional handicraft, this damage
Almost can ignore.
<Second embodiment>
The stress that no silicide according to second preferred embodiment of the invention damages closes on technology lithographic method and includes：
First step：Form source electrode 10 and drain electrode 20 in substrate 100, and formation has side wall 30 on the substrate 100
Grid, and grid, source electrode 10 and drain electrode 20 surface formed metal silicide 40；
Typically, described side wall 30 is the sidewall spacers comprising silicon oxide and silicon nitride film.It is further preferred that it is described
The overall width of side wall 30 is 200-500A.
Second step：Deposition protection layer film 50, the protection layer film on side wall 30 side wall compares grid, source electrode 10 and leakage
The protection layer film on metal silicide 40 being formed on the surface of pole 20 is thinner；
Preferably, can be using HDP (high-density plasma) silicon oxide deposition technique and FCVD (flowable chemistry gas
Phase depositing operation protects layer film 50 to deposit.For example, protection layer film 50 is silicon oxide film or silicon nitride film.With HDP work
As a example skill, can be implemented in top portions of gates and the thickness of source drain by processing procedure regulation is 300-500A, but in side wall
On thickness be less than 100A.
Third step：Carry out stress close on technology etching, wherein etch period with protection layer film thickness cooperation so that
Protection layer film 50 on side wall 30 side wall is completely removed, and side wall 30 is thinned as thinning side wall 31；Real with first
Apply unlike example, grid, source electrode 10 and drain electrode 20 surface on formed metal silicide 40 on protection layer film also by
Remove completely；
For example, when the silicon oxide film on metal silicide consumes 300A, metal silicide does not also expose, but side
The spacer medium layer of wall has consumed 200A.
Four steps：Deposit heavily stressed thin film 60.Typically, heavily stressed thin film 60 can be heavily stressed silicon nitride film, thin
The change that membrane stress can pass through process parameter is adjusted between -3.5Gpa to+2Gpa.
The present invention proposes a kind of it can be avoided that the stress that metal silicide damages closes on technology, it can be avoided that or reducing side
The damage to silicide for the wall etching process, and then improve the performance of semiconductor device.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " 3rd " etc. describes each assembly being used only in differentiation description, element, step etc., rather than is used for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
And it should also be understood that the present invention is not limited to specific method described herein, compound, material, system
Make technology, usage and application, they can change.It should also be understood that term described herein be used merely to describe specific
Embodiment, rather than be used for limiting the scope of the present invention.Must be noted that herein and claims used in
Singulative " one ", " a kind of " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
As the citation of " element " meaned with the citation to one or more elements, and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
Multiple steps or the citation of device, and potentially include secondary step and second unit.Should be managed with broadest implication
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of this structure
Equivalent.Can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
And, the method for the embodiment of the present invention and/or the realization of system may include manual, automatic or execute selected in combination
Task.And, the real instrument of the embodiment of the method according to the invention and/or system and equipment, available operating system is led to
Cross hardware, software or a combination thereof and realize several selected tasks.
Claims (10)
1. the stress that a kind of no silicide damages closes on technology lithographic method it is characterised in that including：
First step：Form source electrode and drain electrode in the substrate, and form the grid with side wall 30 on substrate, and in grid
The surface of pole, source electrode and drain electrode forms metal silicide；
Second step：Deposition protection layer film, the protection layer film on the wall of side wall side is compared on the surface of grid, source electrode and drain electrode
The protection layer film on metal silicide being formed is thinner；
Third step：Carry out stress and close on technology etching, wherein etch period and the thickness cooperation of protection layer film are so that side wall
Protection layer film on the wall of side is completely removed, and side wall thicknesses are thinning, and is formed on the surface of grid, source electrode and drain electrode
Metal silicide on protection layer film be thinned to form thinning protection layer film；
Four steps：Deposit heavily stressed thin film.
2. the stress that no silicide according to claim 1 damages closes on technology lithographic method it is characterised in that described side
Wall is the sidewall spacers comprising silicon oxide and silicon nitride film.
3. the stress that no silicide according to claim 1 and 2 damages closes on technology lithographic method it is characterised in that adopting
Deposit protection layer film with high-density plasma silicon oxide deposition technique.
4. the stress that no silicide according to claim 1 and 2 damages closes on technology lithographic method it is characterised in that adopting
Deposit protection layer film with flowable chemical vapor deposition method.
5. the stress that no silicide according to claim 1 and 2 damages closes on technology lithographic method it is characterised in that height
Stress film is heavily stressed silicon nitride film, and the membrane stress of heavily stressed silicon nitride film is between -3.5Gpa to+2Gpa.
6. the stress that a kind of no silicide damages closes on technology lithographic method it is characterised in that including：
First step：Form source electrode and drain electrode in the substrate, and form the grid with side wall 30 on substrate, and in grid
The surface of pole, source electrode and drain electrode forms metal silicide；
Second step：Deposition protection layer film, the protection layer film on the wall of side wall side is compared on the surface of grid, source electrode and drain electrode
The protection layer film on metal silicide being formed is thinner；
Third step：Carry out stress and close on technology etching, wherein etch period and the thickness cooperation of protection layer film are so that side wall
The protection layer film quilt on metal silicide being formed on the surface of the protection layer film on the wall of side and grid, source electrode and drain electrode
Remove completely, and side wall thicknesses are thinning；
Four steps：Deposit heavily stressed thin film.
7. the stress that no silicide according to claim 6 damages closes on technology lithographic method it is characterised in that described side
Wall is the sidewall spacers comprising silicon oxide and silicon nitride film.
8. the stress that the no silicide according to claim 6 or 7 damages closes on technology lithographic method it is characterised in that adopting
Deposit protection layer film with high-density plasma silicon oxide deposition technique.
9. the stress that the no silicide according to claim 6 or 7 damages closes on technology lithographic method it is characterised in that adopting
Deposit protection layer film with flowable chemical vapor deposition method.
10. the stress that no silicide according to claim 6 or 7 damages closes on technology lithographic method it is characterised in that height
Stress film is heavily stressed silicon nitride film, and the membrane stress of heavily stressed silicon nitride film is between -3.5Gpa to+2Gpa.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610985909.6A CN106409662A (en) | 2016-11-09 | 2016-11-09 | Silicide-damage-free stress approaching technology etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610985909.6A CN106409662A (en) | 2016-11-09 | 2016-11-09 | Silicide-damage-free stress approaching technology etching method |
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| Publication Number | Publication Date |
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| CN106409662A true CN106409662A (en) | 2017-02-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201610985909.6A Pending CN106409662A (en) | 2016-11-09 | 2016-11-09 | Silicide-damage-free stress approaching technology etching method |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112930591A (en) * | 2018-09-18 | 2021-06-08 | 应用材料公司 | In-situ integrated chamber |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050272215A1 (en) * | 2004-06-02 | 2005-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide |
| CN101150064A (en) * | 2006-09-21 | 2008-03-26 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
| CN103094084A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method of eliminating silicon nitride side wall, formation transistor and semi-conductor device |
| CN104716096A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
-
2016
- 2016-11-09 CN CN201610985909.6A patent/CN106409662A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050272215A1 (en) * | 2004-06-02 | 2005-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide |
| CN101150064A (en) * | 2006-09-21 | 2008-03-26 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
| CN103094084A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method of eliminating silicon nitride side wall, formation transistor and semi-conductor device |
| CN104716096A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112930591A (en) * | 2018-09-18 | 2021-06-08 | 应用材料公司 | In-situ integrated chamber |
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Application publication date: 20170215 |
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