CN103295883B - Improve the method for critical size load effect - Google Patents
Improve the method for critical size load effect Download PDFInfo
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- CN103295883B CN103295883B CN201310221342.1A CN201310221342A CN103295883B CN 103295883 B CN103295883 B CN 103295883B CN 201310221342 A CN201310221342 A CN 201310221342A CN 103295883 B CN103295883 B CN 103295883B
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Abstract
The present invention relates to a kind of method improving critical size load effect, be applied in the hard mask etching technique of polysilicon, it is characterized in that, described method comprises: provide the substrate that has a polysilicon layer, and the upper surface of this polysilicon layer is coated with hard mask layer; Form photoresistance pattern at described hard mask layer upper surface, with this photoresistance pattern for mask carries out dry etching to described hard mask layer, form the hard mask pattern with isolated area and close quarters; Photoresistance pattern is removed in ashing; Adopt isotropic plasma to carry out the different dry etching of etch rate to described isolated area with described close quarters, to form new hard mask pattern, this new hard isolated area of mask pattern and the critical size of close quarters reach unanimity simultaneously.
Description
Technical field
The present invention relates to a kind of method reducing defective workmanship in process for fabricating semiconductor device, particularly relate to a kind of method improving critical size load effect.
Background technology
Etching polysilicon is one of critical process of cmos device formation, along with constantly reducing of dimensions of semiconductor devices, photoresist thickness is restricted, the etch thicknesses of polysilicon then too not large reduction, thus make photoresist can not meet as thickness requirement during mask layer in polycrystalline silicon etching process, so after the technology node of 130nm, industry extensively adopts silicon nitride hard mask as the hard mask technology of mask in polycrystalline silicon etching process to carry out polycrystalline silicon etching process.
The polycrystalline silicon etching process carried out based on hard mask technology, first need to make to etch hard mask as mask layer with photoresist, after hard mask has etched, the bottom critical dimension of hard mask finally can affect the critical size of the polysilicon after etching.And hard mask etched after bottom critical dimension isolate at the ISO(of device) region and Dense(compact district) region is differentiated, as shown in Figure 1, what formed after etching is arranged in the hard mask pattern 1041 in device ISO region 1 and the hard mask pattern 1042 in Dense region 2, its top critical size is all identical, and there is larger difference in the critical size of bottom, at this moment, if continue adopt this hard mask and etch the polysilicon below it, critical size difference between the I/Dloading(ISO region of the polysilicon after etching and Dense region) also larger.This just causes cannot taking into account in the ISO region of cmos device and the final electric property in Dense region.
Traditional solution for the problems referred to above distinguishes ISO region and Dense region from the design of device or uses optical approach effect correction (opticalproximitycorrection in the fabrication process, being called for short OPC) technology distinguishes polysilicon ADI critical size, because this needs to process respectively the photoresist mask plate of each product, therefore to require a great deal of time, man power and material.
Chinese patent (publication number: CN102263018A) discloses a kind of method improving the load effect of grid-electrode side wall growth of chip and comprises step: design one group of pattern filling; After the gate layer growth of described chip, needing in described gate layer regulates on the region of the load effect of pattern density and the growth of subsequent gate side wall, in described one group of pattern filling, select a described pattern filling to carry out grid layout, thus the load effect making the pattern density of described chip reach the grid-electrode side wall growth of targeted graphical density and described chip reach targeted loads effect.Then method disclosed in this patent selects a figure to carry out grid layout by first designing one group of pattern filling in pattern filling, this method has certain limitation, need design targetedly each specific product, therefore need when industrial volume production to spend a large amount of man power and materials.
Summary of the invention
In view of the above problems, the invention provides a kind of method improving critical size load effect.
The technical scheme that technical solution problem of the present invention adopts is:
Improve a method for critical size load effect, be applied in the hard mask etching technique of polysilicon, wherein, described method comprises:
There is provided the substrate that has a polysilicon layer, and the upper surface of this polysilicon layer is coated with hard mask layer;
Photoresistance pattern is formed at the upper surface of described hard mask layer, and with this photoresistance pattern for mask etches described hard mask layer, form the hard mask pattern with isolated area and close quarters, and the critical size being positioned at the hard mask pattern of described isolated area is not identical with the critical size of the hard mask pattern being positioned at described close quarters;
Remove described photoresistance pattern;
The critical size of isotropic plasma to described hard mask pattern is adopted to revise, to reduce the difference between the critical size at the hard mask pattern of described isolated area and the critical size of the hard mask pattern at described close quarters.
The method of described improvement critical size load effect, wherein, is greater than the etch rate to described close quarters to the etch rate of described isolated area.
The method of described improvement critical size load effect, wherein, employing flow is that isotropic plasma of 50sccm-100sccm carries out the different dry etching of etch rate to described isolated area with described close quarters simultaneously.
The method of described improvement critical size load effect, wherein, adopts fluorine-containing and gas that is carbon after plasma metallization processes, form described isotropic plasma.
The method of described improvement critical size load effect, wherein, described fluorine-containing and gas that is carbon is CF
4or CHF
3.
The method of described improvement critical size load effect, wherein, described plasma metallization processes comprises: adopting plasma generator, is 400W-800W at plasma source power, substrate bias power is 0V-50V, and pressure is prepare described isotropic plasma under the condition of 3mT-8mT.
The method of described improvement critical size load effect, wherein, the plasma generator selecting plasma source power to be separated with substrate bias power carries out described plasma metallization processes.
The method of described improvement critical size load effect, wherein, described plasma generator is any one in the CCP plasma generator of uncoupling, TCP plasma generator, ICP plasma generator.
The method of described improvement critical size load effect, wherein, the material of described hard mask is silicon nitride.
Technique scheme tool has the following advantages or beneficial effect:
The dry etch process that the present invention adopts isotropic plasma to revise hard mask pattern by increasing by a step after traditional hard mask polysilicon etching technics, to revise hard mask pattern in ISO region and critical size differs greatly in Dense region problem, hard mask pattern after revising etching is reached unanimity in ISO region and the critical size in Dense region, thus the problem that the critical size decreasing the grid formed in gate process in zones of different at follow-up etching polysilicon there are differences.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is the device architecture schematic diagram that in prior art, etching forms hard mask polysilicon pattern;
Fig. 2 ~ Fig. 7 is the device architecture schematic diagram carried out in the inventive method embodiment in polycrystalline silicon gate grid etching process.
Embodiment
The invention provides a kind of method improving critical size load effect.The present invention can be used for technology node to be 65/55nm, 45/40nm, 32/28nm and to be less than or equal in the technique of 22nm; The present invention can be used in the technology platforms such as Logic, Memory, HV, Flash.
The present invention is main but be not limited only to be applied in the etching technics of hard mask polysilicon, for the problem easily causing the bottom characteristic size of the ISO region of device and the hard mask in Dense region there are differences existed in conventional etch processes, by increasing a step hard mask critical size correction etching technics again after the hard mask etching technique of buffering completes, thus the critical size bottom the hard mask in device zones of different is reached unanimity, and then make follow-up with hard mask be stop polycrystalline silicon etching process after polysilicon feature dimension also can region consistent.
Below in conjunction with specific embodiments and the drawings, the inventive method is described in detail.
The inventive method embodiment comprises following processing step:
As shown in Figure 1, a substrate 201 is provided.Wherein, this substrate can be silicon substrate or other forms of substrate.
Prepare insulating oxide 202(GOX) cover the upper surface of this silicon substrate 201, the material of this insulating oxide 202 can be SiO
2deng.
Continue to prepare the upper surface that polysilicon layer 203 covers insulating oxide 202.
Continue to prepare the upper surface that hard mask layer 204 covers polysilicon layer 203, this hard mask layer 204 carries out for the polysilicon of reserve part provides the hard mask layer of stop in polycrystalline silicon etching process for follow-up, and the material of this hard mask layer can be that silicon nitride or bottom are silicon nitride and top layer is the mixed materials of silicon dioxide.
As shown in Figure 3, spin coating photoresist on this hard mask layer 304, to cover the upper surface of this hard mask layer, and photoetching process is carried out to this photoresist, to form photoresistance pattern 305, wherein, photoresistance pattern comprise be arranged in device ISO(and isolate) part in region 1 and to be arranged in device Dense(intensive) part in region 2.
As shown in Figure 4, be that mask etches the hard mask layer be positioned at below it with this photoresistance pattern 405, to form required hard mask pattern 404.In this step, can this hard mask layer be etched using plasma etching technics.Wherein, this hard mask pattern is divided into ISO region 1 and Dense region 2, due to polymer (polymer) can be formed in the process of etching, this polymer can form protection to the place covered, therefore the process etched hard mask layer is an etching and protect the process of synchronously carrying out, , the polymer formed in the hard mask layer etching technics carrying out ISO region 1 is more than to the polymer formed in the hard mask layer etching technics in Dense region 2, so the bottom critical dimension just causing the part being positioned at ISO region 1 in the hard mask layer after etching technics is greater than the bottom critical dimension of the part being positioned at Dense region 2.
Then, as shown in Figure 5, the photoresistance pattern (not illustrating in the drawings) at hard mask pattern 504 top after being positioned at etching is removed in ashing, and the hard mask pattern formed is carried out to the correction etching of critical size, as shown in Figure 6, dotted portion around the hard mask pattern illustrated in figure is by revising the part etching removal in etching technics, and bold portion is remaining part.The correction etching technics of this critical size specifically comprises: adopt high-power plasma source and lower powered bias generator, the plasma with isotropic etching ability is obtained under lower air pressure, and utilize the diffusion rate of this plasma fast and in the slow characteristic of close quarters in depletion region, to revise formed hard mask pattern; Wherein, isotropic plasma is the carbon containing of large discharge and the plasma of fluorine, as CF
4, CHF
3deng.In this step, lower powered bias generator can adopt the bias generator of zero-bias; High-power plasma source can adopt 400W-800W(as 400W, 500W, 600W, 700W, 800W etc.) plasma source; Substrate bias power is that 0V-50V(is as 0V, 10V, 20V, 30V, 40V, 50V etc.); Air pressure is that 3mT-8mT(is as 3mT, 4mT, 5mT, 6mT, 7mT, 8mT); The flow of plasma is 50sccm, 60sccm, 70sccm, 80sccm, 90sccm, the 100sccm etc. such as 50sccm-100sccm(); Correction time is according to the difference of the critical size in ISO region and Dense region and revise speed and determine.
Because the hard mask feature size being positioned at depletion region in the etching technics of hard mask is greater than the hard mask feature size being positioned at close quarters, therefore, the above-mentioned plasma mentioned is utilized to be greater than this characteristic of close quarters diffusion rate in depletion region diffusion rate, carrying out the hard mask pattern revised after technique can make its characteristic size being positioned at the part of depletion region reach unanimity with the critical size of the part being positioned at close quarters, as shown in Figure 7, and then the grid (702 formed in follow-up polycrystalline silicon gate grid etching process, 703) with in Dense region 2, all there is close or identical characteristic size in ISO region 1, effectively prevent the difference of the critical size in I/Dloading(ISO region and Dense region), the load effect of the final critical size improved in polycrystalline silicon gate grid etching process.
Plasma generator can be adopted in the inventive method to carry out above-mentioned plasma etch process.The plasma generator that this plasma generator need adopt plasma source power to be separated with substrate bias power, capacitance coupling plasma (the CapacitivelyCoupledPlasma of all uncouplings, being called for short CCP) generator, inductively coupled plasma (InductivelyCoupledPlasma, be called for short ICP) generator and planar coil inductively coupled plasma (TCP) generator all can be used as application vector of the present invention.It is pointed out that reactive ion etching (ReactiveIonEtching the is called for short RIE) plasma generator by means of only single channel input power is not then suitable for the present invention.
In sum, because the hard mask pattern that formed after traditional hard mask etching technique to form the difference of critical size in ISO region and Dense region, so the present invention is directed to this problem, by increasing the technique that a step adopts isotropic plasma to revise hard mask pattern after traditional hard mask etching technique, make to reduce through the difference of revised hard mask pattern at the critical size in ISO region and Dense region, thus the grid being arranged in ISO region formed in the etching technics of follow-up polysilicon gate reduces with the difference of grid on critical size being positioned at Dense region, improve the critical size load effect in polycrystalline silicon gate grid etching process, and then ensure that the Performance And Reliability of semiconductor device.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (8)
1. improve a method for critical size load effect, be applied in the hard mask etching technique of polysilicon, it is characterized in that, described method comprises:
There is provided the substrate that has a polysilicon layer, and the upper surface of this polysilicon layer is coated with hard mask layer;
Photoresistance pattern is formed at the upper surface of described hard mask layer, and with this photoresistance pattern for mask etches described hard mask layer, form the hard mask pattern with isolated area and close quarters, and the critical size being positioned at the hard mask pattern of described isolated area is not identical with the critical size of the hard mask pattern being positioned at described close quarters;
Remove described photoresistance pattern;
Adopt fluorine-containing and gas that is carbon after plasma metallization processes, form the critical size of isotropic plasma to described hard mask pattern to revise, to reduce the difference between the critical size at the hard mask pattern of described isolated area and the critical size of the hard mask pattern at described close quarters.
2. improve the method for critical size load effect as claimed in claim 1, it is characterized in that, the etch rate to described close quarters is greater than to the etch rate of described isolated area.
3. improve the method for critical size load effect as claimed in claim 1, it is characterized in that, employing flow is that isotropic plasma of 50sccm-100sccm carries out the different dry etching of etch rate to described isolated area with described close quarters simultaneously.
4. improve the method for critical size load effect as claimed in claim 1, it is characterized in that, described fluorine-containing and gas that is carbon is CF
4or CHF
3.
5. improve the method for critical size load effect as claimed in claim 1, it is characterized in that, described plasma metallization processes comprises: adopt plasma generator, be 400W-800W at plasma source power, substrate bias power is 0V-50V, and pressure is prepare described isotropic plasma under the condition of 3mT-8mT.
6. improve the method for critical size load effect as claimed in claim 5, it is characterized in that, the plasma generator selecting plasma source power to be separated with substrate bias power carries out described plasma metallization processes.
7. improve the method for critical size load effect as claimed in claim 6, it is characterized in that, described plasma generator is any one in the CCP plasma generator of uncoupling, TCP plasma generator, ICP plasma generator.
8. improve the method for critical size load effect as claimed in claim 1, it is characterized in that, the material of described hard mask is silicon nitride.
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| JP6289996B2 (en) * | 2014-05-14 | 2018-03-07 | 東京エレクトロン株式会社 | Method for etching a layer to be etched |
| CN107908893B (en) * | 2017-11-29 | 2021-03-12 | 上海华力微电子有限公司 | Layout processing method for missing process hot spot on top of metal layer photoresist |
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| CN1624865A (en) * | 2003-09-19 | 2005-06-08 | 应用材料有限公司 | Method of controlling critical dimension microloading of photoresist trimming process by polymer deposition |
| CN100499029C (en) * | 2003-07-09 | 2009-06-10 | 富士通微电子株式会社 | Semiconductor device manufacture method and etching system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100499029C (en) * | 2003-07-09 | 2009-06-10 | 富士通微电子株式会社 | Semiconductor device manufacture method and etching system |
| CN1624865A (en) * | 2003-09-19 | 2005-06-08 | 应用材料有限公司 | Method of controlling critical dimension microloading of photoresist trimming process by polymer deposition |
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