CN104538360B - A kind of memory cell grid preparation method of flash memory - Google Patents
A kind of memory cell grid preparation method of flash memory Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 65
- 238000007667 floating Methods 0.000 claims abstract description 58
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000001360 synchronised effect Effects 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 230000008878 coupling Effects 0.000 claims abstract description 5
- 238000010168 coupling process Methods 0.000 claims abstract description 5
- 238000005859 coupling reaction Methods 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 43
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 230000008569 process Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of memory cell grid preparation method of flash memory, comprise the following steps：(1) in sequentially forming gate dielectric layer in a semiconductors coupling structure with fleet plough groove isolation structure, floating gate structure layer, dielectric layer and control gate structure sheaf between grid, and form patterning photoresist layer in control gate structure layer surface；(2) control gate structure sheaf is performed etching according to patterning photoresist layer, to remove part control gate structure sheaf；(3) etching is synchronized dielectric layer control gate structure sheaf, grid and floating gate structure layer, floating gate structure layer is had residual；(4) the floating gate structure layer of residual is performed etching using high selectivity etching technics, with complete floating gate structure layer.Because the present invention using dielectric layer the grid and the same step etching method of the floating gate structure, the lithographic method can effectively reduce the loss of shallow trench isolation region, technique is simple, saves the production time, improves production efficiency.
Description
Technical field
The present invention relates to the memory cell grid preparation method of a kind of semiconductor fabrication, more particularly to a kind of flash memory.
Background technology
Flash memory is non-volatile memory devices main currently on the market, is widely used in the number such as mobile phone, palm PC
Code equipment.
As shown in figure 1, the grid of the memory cell areas of flash memory is by dielectric layer 2, floating gate knot between control gate structure sheaf 1, grid
Structure layer 3, gate dielectric layer 4, silicon substrate 5, shallow-trench isolation plot structure 6 are formed.Conventional control gate lithographic method is：First controlled
The etching of grid structure sheaf 1 processed, terminates in dielectric layer 2 between touching grid；Then by the control gate knot between floating gate structure layer 3
Structure layer 1 removes；Continue to etch dielectric layer 2 between gate dielectric layer 4 and grid；Finally etch floating gate structure layer 3.Due to floating gate knot
There is ladder height in the side wall of structure layer 3, the step needs the enough time to remove gate dielectric layer 4 completely, and this can be caused necessarily
The shallow-trench isolation loss of amount, while complex manufacturing.
Number of patent application is 200510126274.6 Chinese patent, discloses a kind of anisotropic polysilicon of raising and carves
Etching technique, comprise the following steps：Through etching, pulse etching, pulse main etching, over etching.Wherein pulse main etching includes tool
There is the first technique of the first radio-frequency pulse power, first gas flow, the pulse main etching also includes having the second radio frequency source arteries and veins
The second technique of power, second gas flow is rushed, wherein the first technique and the second technique are alternately, in the second radio frequency source pulse
Cycle is substantially carried out the generation of polymer and the protection of side wall；Polysilicon is substantially carried out in the first radio frequency source pulse period longitudinally to carve
Erosion, the technical scheme reduce lateral etch rate, and with good longitudinal etching speed, pack etch rate and larger
Etch area.It can thus be appreciated that during this mode etches, the first technique mainly carries out longitudinal etching, the second technique to polysilicon
The generation of polymer and the protection of side wall are substantially carried out, the first technique alternately, improves longitudinal etching with the second technique
Speed, horizontal etch rate is reduced, and cutd open so that forming good anisotropic etching during plasma etching
Face, but floating gate structure layer and fleet plough groove isolation structure be by once etching shaping, actually floating gate structure layer with it is shallow
A ladder height between groove isolation construction be present, the control gate made using such a mode, can to shallow trench isolation region or
Person's floating gate layer causes damage, or shallow trench isolation region causes damage simultaneously with floating gate layer.
Number of patent application is 200310108277 Chinese patent, is disclosed a kind of for manufacturing flash memory control gate
The improved method of packed structures formation process, it is characterised in that during the preceding road technique Integrated manufacture of flash memory, floating
After dynamic formation, before control gate is formed, using following process：
(1) second of tunnel gate oxidation prerinse is carried out；(2) second of tunnel gate oxidation is carried out, forms SIO2/HTO/
SIO2Three-decker；(3) depositing polysilicon and its doping；(4) tungsten silicide thin film is deposited；(5) conventional photolithography is carried out, it is walked
It is rapid as follows：(a) organic antireflection layer is coated；(b) photoresist is coated；(c) exposure is developed；(6) dry etching, its step is such as
Under：(a) a step dry etching is carried out, its step is as follows：First carry out organic antireflection layer etching, then carry out tungsten silicide and
Polysilicon film etches；(b) wet method, which is peeled off, removes photoresist.
The flash memory control gate for adopting this method the manufacturing has the advantage that and is the reduction of process complexity, drops
Low production cost, shorten technological process and production time, that is, improve output, extraordinary technology stability；Obtain
More preferable control gate packed structures pattern, so as to improve yield rate and reliability.It can be seen that improved method use is still
Conventional photo-mask process and dry etching, equally can be high because of the ladder between floating gate structure layer and fleet plough groove isolation structure
Degree, to shallow trench isolation region, either floating gate layer causes damage or shallow trench isolation region and floating gate layer while caused damage.To rear
Continuous technique adversely affects, and finally influences the Performance And Reliability of semiconductor devices.
The content of the invention
The technical problem to be solved in the present invention is, for the drawbacks described above of prior art, there is provided a kind of technique is simple, shallow
Groove isolated area loses the preparation method of the memory cell grid of small flash memory, improves performance of integrated circuits.
The technical proposal for solving the technical problem of the invention is as follows：
A kind of memory cell grid preparation method of flash memory, comprises the following steps：
Step 1, in sequentially forming gate dielectric layer in the semiconductors coupling structure that one has fleet plough groove isolation structure, float
Grid structure sheaf, dielectric layer and control gate structure sheaf between grid, and form patterning photoresist layer in the control gate structure layer surface；
Step 2, the control gate structure sheaf is performed etching according to the patterning photoresist layer, to remove the photoresistance
The control gate structure sheaf above the floating gate structure layer in layer exposed region, and make on the fleet plough groove isolation structure
The control gate structure sheaf of side has residual；
Step 3, dielectric layer and the floating gate structure layer the control gate structure sheaf (1), the grid are synchronized
Etching, to remove the control gate knot of residual above the fleet plough groove isolation structure in the photoresist layer exposed region completely
Structure layer, and remove completely at the top of the floating gate structure layer in the photoresist layer exposed region, the floating gate structure layer
Dielectric layer between the grid of both sides, and the grid at the top of the fleet plough groove isolation structure in the photoresist layer exposed region are removed completely
Dielectric layer, and the certain thickness floating gate structure layer in the photoresist layer exposed region is removed, and make the floating gate
Structure sheaf has residual；
Step 4, the floating gate knot using high selectivity etching technics to the residual in the photoresist layer exposed region
Structure layer performs etching, to remove the floating gate structure layer in the photoresist layer exposed region, and the shallow trench isolation junction completely
The surface of structure is not etched
As further preferred embodiment, the etch period of step 2 of the present invention is 2s-5s so that the shallow ridges
The remaining balance scope of control gate structure sheaf above recess isolating structure is 400
As further preferred embodiment, the etch period of step 3 of the present invention is 25s-35s, and etching temperature is
40 DEG C -60 DEG C so that the remaining balance scope of the floating gate structure layer is 200
As further preferred embodiment, for the present invention in the step 1, the material of the gate dielectric layer is oxidation
Silicon, the material of the floating gate structure layer are polysilicon, and the material of dielectric layer is silica or silicon nitride between the grid, the control
The material of grid structure sheaf processed is polysilicon.
As further preferred embodiment, the present invention in the step 3, the synchronous etching using have it is each to
The plasma etching industrial of anisotropic etch ability.
As further preferred embodiment, plasma etching industrial of the present invention is to polysilicon, silica, silicon nitride
Selection compare for 1:1:1.
As further preferred embodiment, the plasma source power of plasma etching industrial of the present invention is 600W-
900W, it is 80V-150V that bias, which sets scope, and etching air pressure range is 3-8MT, gas CF4, gas flow 100sccm.
As further preferred embodiment, the scope of the etch period of step 4 of the present invention is 20s-30s, etching
The scope of speed is
As further preferred embodiment, in the step 4, the high selectivity etching technics uses the present invention
Be HBr and O2Mixed gas, selection of the high selectivity etching technics to polysilicon and silica compare for 100：1.
As further preferred embodiment, HBr and O of the present invention2Mixed gas volume ratio be 100:1.
Above-mentioned technical proposal has the following advantages that or beneficial effect：
(1) because the etching mode that the present invention uses is that dielectric layer the grid and the floating gate structure are synchronized
Lithographic method, the lithographic method can effectively reduce the loss of shallow trench isolation region, be beneficial to subsequent technique, and finally improve and partly lead
The Performance And Reliability of body device.This method is used simultaneously, technique is simple, saves the production time, improves production efficiency.
(2) because the synchronous etching is using the plasma etching industrial with anisotropic etching ability.Can be to figure
Shape accurately controls, and etching forming effect is good.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is the etch process flow figure of control gate in the prior art；
Fig. 2 (a) is the structural representation of step 1 of the present invention；
Fig. 2 (b) is structural representation of the present invention after step 2 is handled；
Fig. 2 (c) is structural representation of the present invention after step 3 is handled；
Fig. 2 (d) is structural representation of the present invention after step 4 is handled.
Embodiment
The present invention provides a kind of memory cell grid preparation method of flash memory, and can be applied to technology node is 45/40nm's
In technique；It can be applied in Flash technology platform.
The core concept of the present invention is the quarter by that will synchronize lithographic method to dielectric layer grid and floating gate structure
Etching method can effectively reduce the loss of shallow trench isolation region, be beneficial to subsequent technique, and finally improve the performance of semiconductor devices
And reliability.This method is used simultaneously, technique is simple, saves the production time, improves production efficiency.
The inventive method is described in detail below in conjunction with the accompanying drawings.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as limiting to the invention.
A kind of memory cell grid preparation method of flash memory, comprises the following steps：
Step 1, sequentially formed as Fig. 2 (a) is shown in a semiconductors coupling structure with fleet plough groove isolation structure 6
Gate dielectric layer 4, floating gate structure layer 3, dielectric layer 2 and control gate structure sheaf 1 between grid, and in the surface of control gate structure sheaf 1
Form patterning photoresist layer；
Step 2, as Fig. 2 (b) according to it is described patterning photoresist layer the control gate structure sheaf 1 is performed etching, with remove
The control gate structure sheaf 1 positioned at the top of floating gate structure layer 3 in the photoresist layer exposed region, and make the shallow trench
The control gate structure sheaf 1 of the top of isolation structure 6 has residual；
Step 3, if Fig. 2 (c) is dielectric layer 2 the control gate structure sheaf 1, the grid and the floating gate structure layer 3
Etching is synchronized, to remove the institute of the top of the fleet plough groove isolation structure 6 residual in the photoresist layer exposed region completely
Control gate structure sheaf 1 is stated, and removes the top of the floating gate structure layer 3 in the photoresist layer exposed region, described completely
Dielectric layer 2 between the grid of the both sides of floating gate structure layer 3, and remove completely the shallow trench in the photoresist layer exposed region every
From the gate dielectric layer 4 at the top of structure 6, and remove the certain thickness floating gate structure layer in the photoresist layer exposed region
3, and the floating gate structure layer 3 is had residual；
Step 4, Fig. 2 (d) uses high selectivity etching technics to as described in the residual in the photoresist layer exposed region
Floating gate structure layer 3 performs etching, to remove the floating gate structure layer 3 in the photoresist layer exposed region completely, and it is described shallow
The surface of groove isolation construction 6 is not etched.
Pass through above step：The present invention first one have fleet plough groove isolation structure semiconductors coupling structure on according to
Secondary formation gate dielectric layer, floating gate structure layer, dielectric layer and control gate structure sheaf between grid, and formed in control gate structure layer surface
Pattern photoresist layer；Then the etching of the control gate structure sheaf above floating gate structure layer in photoresist layer exposed region,
And the control gate structure sheaf above fleet plough groove isolation structure is set to have residual；Then dielectric layer grid and floating gate structure are carried out same
Step etching, and floating gate structure layer is had residual；Finally using high selectivity etching technics to residual in photoresist layer exposed region
The floating gate structure layer stayed performs etching, to remove the floating gate structure layer in removing photoresistance layer exposed region completely.Due to the present invention
The etching mode of use is to synchronize lithographic method to dielectric layer grid and floating gate structure, and the lithographic method can effectively subtract
The loss of few shallow trench isolation region, it is beneficial to subsequent technique, and finally improves the Performance And Reliability of semiconductor devices.Use simultaneously
This method, technique is simple, saves the production time, improves production efficiency.
As further preferred embodiment, the etch period of step 2 of the present invention is 2s-5s so that the shallow ridges
The remaining balance scope of the control gate structure sheaf 1 of the top of recess isolating structure 6 is
As further preferred embodiment, the etch period of step 3 of the present invention is 25s-35s, and etching temperature is
40 DEG C -60 DEG C so that the remaining balance scope of the floating gate structure layer 3 is
As further preferred embodiment, in the present invention in step 1, the material of the gate dielectric layer 4 is oxidation
Silicon, the material of the floating gate structure layer 3 are polysilicon, and the material of dielectric layer 2 is silica or silicon nitride or two between the grid
The mixed layer of silica silicon nitride silica, the material of the control gate structure sheaf 1 is polysilicon.
As further preferred embodiment, in the present invention in step 3, synchronous etching is carved using having anisotropy
The plasma etching industrial of erosion ability, it is good that forming effect can be etched to the accurate control of figure.
As further preferred embodiment, plasma etching industrial is to polysilicon, silica, silicon nitride in the present invention
Selection ratio is 1:1:1, polysilicon, silica, silicon nitride can be performed etching simultaneously, improve the degree of accuracy of etching.
As further preferred embodiment, the plasma source power of plasma etching industrial is 600W- in the present invention
900W, it is 80V-150V that bias, which sets scope, and etching air pressure range is 3-8MT, gas CF4, gas flow 100sccm.
As further preferred embodiment, the scope of the etch period of step 4 is 20s-30s in the present invention, etching speed
The scope of rate is
As further preferred embodiment, in the present invention in step 4, high selectivity etching technics is using HBr
With O2Mixed gas.Selection of the high selectivity etching technics to polysilicon and silica is compared for 100：1, the high selectivity
Etching technics can ensure that shallow trench isolation region will not be performed etching, and shallow trench isolation region will not be caused damage.
As further preferred embodiment, HBr and O in the present invention2Mixed gas volume ratio be 100:1.
Preferred embodiments of the present invention are these are only, not thereby limit embodiments of the present invention and protection domain, it is right
For those skilled in the art, it should can appreciate that and all be replaced with being equal made by description of the invention and diagramatic content
Change and obviously change resulting scheme, should be included in protection scope of the present invention.
Claims (9)
1. the memory cell grid preparation method of a kind of flash memory, it is characterised in that comprise the following steps：
Step 1, in sequentially forming gate dielectric layer (4) in the semiconductors coupling structure that one has fleet plough groove isolation structure (6), float
Moving grid structure sheaf (3), dielectric layer (2) and control gate structure sheaf (1) between grid, and formed in control gate structure sheaf (1) surface
Pattern photoresist layer；
Step 2, the control gate structure sheaf (1) is performed etching according to the patterning photoresist layer, to remove the photoresist layer
The control gate structure sheaf (1) above the floating gate structure layer (3) in exposed region, and make the shallow trench isolation junction
Control gate structure sheaf (1) above structure (6) has residual；
Step 3, dielectric layer (2) the control gate structure sheaf (1), the grid and the floating gate structure layer (3) are carried out same
Step etching, to remove the control of residual above the fleet plough groove isolation structure (6) in the photoresist layer exposed region completely
Grid structure sheaf (1) processed, and remove completely at the top of the floating gate structure layer (3) in the photoresist layer exposed region, be described
Dielectric layer (2) between the grid of floating gate structure layer (3) both sides, and the shallow ridges in the photoresist layer exposed region is removed completely
Gate dielectric layer (4) at the top of recess isolating structure (6), and remove the certain thickness floating in the photoresist layer exposed region
Grid structure sheaf (3), and the floating gate structure layer (3) is had residual；
Step 4, the floating gate structure layer using high selectivity etching technics to the residual in the photoresist layer exposed region
(3) perform etching, to remove the floating gate structure layer (3) in the photoresist layer exposed region completely, and the shallow trench is isolated
The surface of structure (6) is not etched；
Wherein, the etch period of the step 2 is 2s-5s so that the control gate knot above the fleet plough groove isolation structure (6)
The remaining balance scope of structure layer (1) is
A kind of 2. memory cell grid preparation method of flash memory according to claim 1, it is characterised in that the step 3
Etch period be 25s-35s, etching temperature is 40 DEG C -60 DEG C so that the remaining balance scope of the floating gate structure layer (3)
For
3. the memory cell grid preparation method of a kind of flash memory according to claim 1, it is characterised in that in the step
In one, the material of the gate dielectric layer (4) is silica, and the material of the floating gate structure layer (3) is polysilicon, between the grid
The material of dielectric layer (2) is silica or silicon nitride, and the material of the control gate structure sheaf (1) is polysilicon.
4. the memory cell grid preparation method of a kind of flash memory according to claim 3, it is characterised in that in the step
In rapid three, the synchronous etching is using the plasma etching industrial with anisotropic etching ability.
A kind of 5. memory cell grid preparation method of flash memory according to claim 4, it is characterised in that：The plasma
Selection of the etching technics to polysilicon, silica, silicon nitride is compared for 1:1:1.
A kind of 6. memory cell grid preparation method of flash memory according to claim 4, it is characterised in that：The plasma
The plasma source power of etching technics is 600W-900W, and it is 80V-150V that bias, which sets scope, and etching air pressure range is 3-8MT,
Gas is CF4, gas flow 100sccm.
A kind of 7. memory cell grid preparation method of flash memory according to claim 1, it is characterised in that：The step 4
The scope of etch period be 20s-30s, the scope of etch rate is
A kind of 8. memory cell grid preparation method of flash memory according to claim 3, it is characterised in that：In the step
In four, the high selectivity etching technics is using HBr and O2Mixed gas, the high selectivity etching technics is to polycrystalline
The selection of silicon and silica is compared for 100：1.
A kind of 9. memory cell grid preparation method of flash memory according to claim 8, it is characterised in that：The HBr and O2
Mixed gas volume ratio be 100:1.
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| CN113097211A (en) * | 2020-01-09 | 2021-07-09 | 联华电子股份有限公司 | Non-volatile memory element and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153469A (en) * | 1998-07-13 | 2000-11-28 | Samsung Electronics, Co., Ltd. | Method of fabricating cell of flash memory device |
| CN103077925A (en) * | 2011-10-25 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for memory |
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| US20030054608A1 (en) * | 2001-09-17 | 2003-03-20 | Vanguard International Semiconductor Corporation | Method for forming shallow trench isolation in semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153469A (en) * | 1998-07-13 | 2000-11-28 | Samsung Electronics, Co., Ltd. | Method of fabricating cell of flash memory device |
| CN103077925A (en) * | 2011-10-25 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for memory |
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