CN103094185A - Forming method for contact hole - Google Patents
Forming method for contact hole Download PDFInfo
- Publication number
- CN103094185A CN103094185A CN2011103378634A CN201110337863A CN103094185A CN 103094185 A CN103094185 A CN 103094185A CN 2011103378634 A CN2011103378634 A CN 2011103378634A CN 201110337863 A CN201110337863 A CN 201110337863A CN 103094185 A CN103094185 A CN 103094185A
- Authority
- CN
- China
- Prior art keywords
- contact hole
- inter
- etching
- level dielectric
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
The invention discloses a forming method for a contact hole. The forming method for the contact hole comprises that a substrate which is provided with a source region and grid electrodes is supplied; an inter-layer medium is formed on the substrate; corrosion of the inter-layer medium for the first time when the contact hole is formed is carried out, the inter-layer medium with the preset thickness is preserved and a first contact hole is formed after the corrosion for the first time; a protecting layer is formed on the inter-layer medium, and the protecting layer covers the bottom and the side wall of the first contact hole; the protecting layer is corroded; the corrosion of the preserved inter-layer medium with the preset thickness for the second time when the contact hole is formed, a second contact hole is formed after the corrosion for the second time, and the second contact hole is communicated with the first contact hole. By means of the forming method for the contact hole, phenomenon that corner loss appears on side parts of the source region and/or the grid electrodes can be effectively avoided so as to reduce the failure rate of the device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of formation method of contact hole.
Background technology
Fabrication of semiconductor device can be divided into FEOL and last part technology, FEOL mainly forms the corresponding devices such as transistor, electric capacity or resistance on substrate, last part technology mainly is connected the device that forms in FEOL by metal, namely main formation is metal interconnected.Wherein, when formation is metal interconnected in last part technology, at first need to form inter-level dielectric (ILD) on the substrate that is formed with the corresponding devices such as transistor, electric capacity or resistance, then form contact hole in ILD, form metal level afterwards on described ILD, described metal level is filled the contact hole in full ILD, thereby the active area that makes corresponding device on substrate and grid are connected with metal level on ILD by the interior metal of contact hole.
In recent years, the characteristic size of semiconductor device was more and more less, and this is more and more higher to the required precision in manufacture process.In the manufacturing process of 0.13 μ m～0.18 μ m; when forming contact hole in last part technology in ILD, often can be due to the contraposition in process window restriction, photoetching process deviation etc. in inaccurate or design process former thereby cause occurring bight loss (corner loss).With reference to figure 1, contact hole 2 formed in inter-level dielectric 1 and inter-level dielectric 1, that be connected with active area 4 has been shown in Fig. 1, over etching has appearred in the bight 3 of this contact hole 2 bottoms, and the bight 3 that is formed by over etching is positioned at shallow trench dielectric layer 5.Because described shallow trench dielectric layer 5 is used for isolation active area 4, therefore, when a bight 3 in described shallow trench dielectric layer 5 is etched and when forming contact hole, can makes source or leakage and substrate short circuit in active area 4 in serious situation, thereby make component failure.
Existing technique solves the bight loss when forming contact hole method has: before forming ILD on substrate, at first form one deck silicon oxynitride, form ILD afterwards on described silicon oxynitride, and then carry out the etching of contact hole.When etching ILD, described silicon oxynitride layer can be used as etching stop layer, therefore, can solve the bight that causes because ILD is inhomogeneous occurring and lose problem.But, after the complete ILD of etching, more described silicon oxynitride layer is carried out etching when forming contact hole, the problem of bight loss still can appear.
Therefore, the bight loss that produces when adopting the method that has now in technique to reduce to form contact hole, but can not eliminate the loss of described bight fully.
Summary of the invention
In view of this, the invention provides a kind of formation method of contact hole, the method can be eliminated the bight loss fully, and then improves the rate of finished products of device.
For achieving the above object, the invention provides following technical scheme:
A kind of formation method of contact hole, the method comprises:
Substrate is provided, has active area and grid in described substrate;
Form inter-level dielectric in described substrate;
Etching for the first time when described inter-level dielectric is formed contact hole keeps for the first time the inter-level dielectric of preset thickness, and has formed the first contact hole after etching for the first time after etching;
Form protective layer on described inter-level dielectric, described protective layer covers bottom and the sidewall of described the first contact hole;
Described protective layer is carried out etching;
Etching for the second time when the inter-level dielectric of the preset thickness of described reservation is formed contact hole has formed the second contact hole for the second time after etching, described the second contact hole is connected with described the first contact hole.
Preferably, in said method, before forming inter-level dielectric in described substrate, also comprise: form silicon oxynitride layer in described substrate;
After etching for the second time when the inter-level dielectric to the preset thickness of described reservation forms contact hole, also comprise: described silicon oxynitride layer is carried out etching, form the 3rd contact hole after etching, described the 3rd contact hole is connected with described the second contact hole.
Preferably, in said method, the etching for the first time when described inter-level dielectric is formed contact hole specifically comprises:
Preset Time is set;
Form the photoresist layer with contact hole pattern on described inter-level dielectric;
Take described photoresist layer with contact hole pattern as mask, described inter-level dielectric is carried out etching for the first time, and carry out for the first time that the time of etching is Preset Time.
Preferably, in said method, the thickness of described inter-level dielectric is
Preferably, in said method, described preset thickness is
Preferably, in said method, described protective layer is silicon nitride layer.
Preferably, in said method, described inter-level dielectric comprises: lower floor
Silicon dioxide and upper strata
Anti-reflecting layer.
Preferably, in said method, described substrate is silicon substrate.
Preferably, in said method, form inter-level dielectric and adopt chemical vapor deposition method in described substrate.
Preferably, in said method, described protective layer is carried out etching adopt dry etch process.
can find out from technique scheme, the formation method of contact hole provided by the present invention has kept the inter-level dielectric of preset thickness after inter-level dielectric being carried out etching for the first time, meanwhile formed the first contact hole, form protective layer afterwards on described inter-level dielectric, described protective layer covers bottom and the sidewall of described the first contact hole, follow-up when described protective layer is carried out etching, the protective layer that covers the first contact hole sidewall will can not be etched away, and keep partial protection layer on the sidewall of described the first contact hole that is:, etching for the second time when at last the inter-level dielectric of the preset thickness that keeps being formed contact hole, and formed the second contact hole, when carrying out for the second time etching, kept partial protection layer on sidewall due to the first contact hole, therefore, the partial protection layer of described reservation will protect the inter-level dielectric under it not to be etched away, thereby make the width of the second contact hole of final formation less than the width of described the first contact hole, be communicated with the first contact hole when the second contact hole when forming a contact hole, this contact hole bight the phenomenon of over etching can not occur, thereby avoided the phenomenon that lose in the bight occurring at active area and/or grid sidepiece, and then reduced the failure rate of device.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation that occurs loss phenomenon in bight in the forming process of contact hole common in prior art;
The schematic flow sheet of the formation method of a kind of contact hole that Fig. 2 provides for the embodiment of the present invention;
The cross-sectional view of device in the contact hole forming process that Fig. 3～Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment one
With reference to figure 2, the schematic flow sheet of the formation method of a kind of contact hole that Fig. 2 provides for the embodiment of the present invention, the method specifically comprises following several step:
Step S1: substrate is provided, has active area and grid in described substrate.
With reference to figure 3, substrate 100 has been shown in Fig. 3, substrate described in the embodiment of the present invention 100 is silicon substrate, in other embodiment, described substrate 100 can also be the semi-conducting materials such as germanium, indium phosphide or GaAs.Described substrate 100 generally comprises body layer and epitaxial loayer, in fabrication of semiconductor device, the carrier when techniques such as photoetching, etching or Implantation are carried out generally is epitaxial loayer, and this specification will no longer specifically be distinguished suprabasil body layer and epitaxial loayer, claim to carry out in substrate or in substrate without exception each processing step.
The substrate 100 that provides in this step has grid 104 and is positioned at the side wall 105 of grid 104 both sides on it; Have deep-well region 101 in substrate 100, have active area in deep-well region 101, described active area comprises source region 102 and drain region 103, and source region 102 and drain region 103 lay respectively at grid 104 both sides.Also has to isolate the shallow trench dielectric layer 106 of active device in described substrate 100.
Step S2: form inter-level dielectric in described substrate.
With reference to figure 4, adopt chemical gaseous phase depositing process to form inter-level dielectric 107 in substrate 100, inter-level dielectric described in the present embodiment 107 comprises that the very thin anti-reflecting layer of silicon dioxide and upper strata of lower floor (is about
), the thickness of described inter-level dielectric 107 is
In specific implementation process, at first form silicon dioxide in substrate, form anti-reflecting layer afterwards on described silicon dioxide, described anti-reflecting layer can be silicon oxynitride layer, and described anti-reflecting layer can serve as hard mask layer in following step S6.Do not specifically illustrate silicon dioxide and silicon oxynitride layer in Fig. 4, therefore, will be referred to as inter-level dielectric 107 in each step below.
Step S3: the etching for the first time when described inter-level dielectric is formed contact hole keeps for the first time the inter-level dielectric of preset thickness, and has formed the first contact hole after etching for the first time after etching.
Describe as an example of the contact hole that form to connect the drain region example in the embodiment of the present invention.
This step can comprise following several step:
Step S31: Preset Time is set.
Described in this step, Preset Time refers to: when inter-level dielectric was carried out etching, the time that etching is carried out, this time can be set on etching machine in advance.It is 50s that described Preset Time is set in this step, and the difference according to technological requirement in other embodiment can arrange different Preset Times.But this Preset Time is etched away required time fully less than inter-level dielectric.
Step S32: form the photoresist layer with drain region contact hole pattern on described inter-level dielectric.
At first spin coating photoresist layer on described inter-level dielectric, then adopt the mask plate with drain region contact hole pattern that described photoresist layer is exposed, and develops after exposure, formed the photoresist layer with drain region contact hole pattern on described inter-level dielectric.
Step S33: take described photoresist layer with drain region contact hole pattern as mask, described inter-level dielectric is carried out etching for the first time, and carry out for the first time that the time of etching is Preset Time.
With reference to figure 5, take described photoresist layer (not shown) with drain region contact hole pattern as mask, described inter-level dielectric 107 is carried out etching for the first time, and carry out for the first time that the time of etching is Preset Time set in step S31.Because described Preset Time is etched away required time fully less than inter-level dielectric 107, therefore, kept for the first time certain thickness inter-level dielectric 107 after etching (after the first etching completes, anti-reflecting layer and part silicon dioxide layer on inter-level dielectric 107 have been etched away, the certain thickness inter-level dielectric 107 that keeps is silicon dioxide), there is shown the thickness d of the inter-level dielectric 107 that remains.After inter-level dielectric 107 is carried out for the first time etching, formed contact hole is called the first contact hole 108 in embodiments of the present invention, and described in the present embodiment, the width a of the first contact hole 108 is the width of drain region contact hole pattern on photoresist layer.
Need to prove, according to the gross thickness of inter-level dielectric 107, described Preset Time and the etch rate in etching process for the first time, can calculate the thickness d of the inter-level dielectric 107 that keeps after etching for the first time, therefore, this thickness d also can be described as preset thickness.
What in the present embodiment, inter-level dielectric 107 is carried out that etching for the first time adopts is anisotropic dry etch process, below described etching for the second time be also dry etching.
Step S4: form protective layer on described inter-level dielectric, described protective layer covers bottom and the sidewall of described the first contact hole.
With reference to figure 6, adopt chemical gaseous phase depositing process to form protective layer 109 on described inter-level dielectric 107, described protective layer 109 covers bottom and the sidewall of described the first contact hole 108.Protective layer described in the present embodiment 109 is silicon nitride layer, and protective layer 109 described in other embodiment can also be other material, for example: polysilicon.The thickness of protective layer described in the present embodiment 109 is
Step S5: described protective layer is carried out etching.
With reference to figure 7; adopt dry etch process to carry out etching to the protective layer on inter-level dielectric 107; because the dry etching process belongs to anisotropic etching; can not be etched away (according to the spacer principle) therefore cover the protective layer 110 of the first contact hole 108 sidewalls; therefore; the result of described protective layer being carried out etching is: kept the protective layer 110 on the first contact hole 108 sidewalls, the protective layer at all the other positions all has been etched away.
Step S6: the etching for the second time the when inter-level dielectric of the preset thickness of described reservation is formed contact hole, formed for the second time the second contact hole after etching, described the second contact hole is connected with described the first contact hole.
Still describe as an example of the contact hole that form to connect the drain region example in this step.
With reference to figure 8, the anti-reflecting layer in the inter-level dielectric 107 is as hard mask, and the inter-level dielectric 107 that is d to the preset thickness of described reservation carries out etching for the second time.After the preset thickness of the described reservation inter-level dielectric 107 that is d is carried out for the second time etching, formed the second contact hole 111, and described the second contact hole 111 is connected with the first contact hole 108.
When the inter-level dielectric 107 that is d of the preset thickness to described reservation carries out for the second time etching; owing to having protective layer 110 on the first contact hole 108 sidewalls; the existence of described protective layer 110 can protect the inter-level dielectric 112 under it to avoid etching; therefore; after etching, the width b of formed the second contact hole 111 is less than the width a of described the first contact hole 108 for the second time, and both differences are 2 times (supposing that protective layer 110 thickness on the first contact hole 108 both sides sidewalls are identical) of protective layer 110 thickness on the first contact hole 108 sidewalls.
By controlling the thickness of formed protective layer in step S4, can control the thickness of protective layer 110 on the first contact hole 108 sidewalls, and then can control the width b of the second contact hole 111.
Described the second contact hole 111 is connected with the first contact hole 108 and has jointly consisted of the contact hole that is connected with drain region 103, be the second contact hole 111 due to what directly be connected with drain region 103, therefore, the width b of described the second contact hole 111 is the size (CD) of the contact hole that is connected with drain region 103, therefore adopt method provided by the present invention, when forming with contact hole that drain region 103 is connected, can effectively reduce the size of described contact hole.
And; when carrying out for the second time etching due to the inter-level dielectric 107 that in the preset thickness to described reservation is d; in etching technics plasma used can corresponding the first contact hole 108 sidewalls of etching on inter-level dielectric 112 under protective layer 110; therefore; final when forming with contact hole that drain region 103 is connected, the bight also just can not occur and lose phenomenon.Even etch period is a little longer again, the zone of over etching also is positioned at drain region 103, and can not be positioned at shallow trench dielectric layer 106, thereby has avoided the short circuit of drain region 103 with substrate 100, has avoided the generation of component failure phenomenon.
The above describes the forming process of the contact hole that is connected with the drain region in detail, for the forming process of the contact hole that is connected with the source region and the contact hole that is connected with grid similarly, no longer is described.
as from the foregoing, the formation method of contact hole provided by the present invention, the etching that inter-level dielectric is formed contact hole is carried out (being called for short respectively etching and etching for the first time for the second time) at twice, and formed protective layer in the twice etching process on inter-level dielectric, and described protective layer has been carried out etching, the result of described protective layer being carried out etching is: kept partial protection layer (spacer principle) on the sidewall of the first contact hole that forms after etching for the first time, and then follow-up when carrying out for the second time etching, described protective layer can protect the inter-level dielectric under it to avoid etching, therefore, for the second time after etching the width of formed the second contact hole less than the width of the first contact hole, this has reduced the size of contact hole on the one hand, can avoid on the other hand forming the bight loss in the both sides of active area or grid.For forming the contact hole that is connected with active area, can avoid forming the bight loss in the shallow trench dielectric layer, and then can avoid the short circuit of source/leakage and substrate, reduced the risk of component failure.
Embodiment two
The present embodiment has increased again two steps on the basis of embodiment one, as follows respectively:
Before step S2, can increase in embodiment one: form silicon oxynitride layer in described substrate; After step S6, can increase in embodiment one: described silicon oxynitride layer is carried out etching, form the 3rd contact hole after etching, described the 3rd contact hole is connected with described the second contact hole.
In the present embodiment before forming inter-level dielectric in substrate, at first formed silicon oxynitride layer in substrate, then after the etching for the second time when the inter-level dielectric to the preset thickness of described reservation forms contact hole, described silicon oxynitride layer is carried out etching, the etching result is to have formed the 3rd contact hole, described the 3rd contact hole is connected with described the second contact hole, thereby has jointly consisted of by described the first contact hole, described the second contact hole and the 3rd contact hole the contact hole that is connected with source region or grid.
At first formed silicon oxynitride layer in the present embodiment before forming inter-level dielectric, this silicon oxynitride layer can be as stop-layer in inter-level dielectric being carried out the process of etching for the second time, thereby phenomenon is lost in the bight that can avoid producing because inter-level dielectric is inhomogeneous, therefore, can avoid better the generation of loss phenomenon in bight in the contact hole forming process, reduce the failure rate of device.
The mode that embodiment of the present invention employing is gone forward one by one is described the formation method of contact hole, and each embodiment all has its emphasis, relevant, similarity reference mutually.
Need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operating space, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make the process, method, article or the equipment that comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, realization in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. the formation method of a contact hole, is characterized in that, comprising:
Substrate is provided, has active area and grid in described substrate;
Form inter-level dielectric in described substrate;
Etching for the first time when described inter-level dielectric is formed contact hole keeps for the first time the inter-level dielectric of preset thickness, and has formed the first contact hole after etching for the first time after etching;
Form protective layer on described inter-level dielectric, described protective layer covers bottom and the sidewall of described the first contact hole;
Described protective layer is carried out etching;
Etching for the second time when the inter-level dielectric of the preset thickness of described reservation is formed contact hole has formed the second contact hole for the second time after etching, described the second contact hole is connected with described the first contact hole.
2. method according to claim 1, is characterized in that, before forming inter-level dielectric in described substrate, also comprises: form silicon oxynitride layer in described substrate;
After etching for the second time when the inter-level dielectric to the preset thickness of described reservation forms contact hole, also comprise: described silicon oxynitride layer is carried out etching, form the 3rd contact hole after etching, described the 3rd contact hole is connected with described the second contact hole.
3. method according to claim 2, is characterized in that, the etching for the first time when described inter-level dielectric is formed contact hole specifically comprises:
Preset Time is set;
Form the photoresist layer with contact hole pattern on described inter-level dielectric;
Take described photoresist layer with contact hole pattern as mask, described inter-level dielectric is carried out etching for the first time, and carry out for the first time that the time of etching is Preset Time.
4. method according to claim 1, is characterized in that, the thickness of described inter-level dielectric is
5. method according to claim 1, is characterized in that, described preset thickness is
6. method according to claim 1, is characterized in that, described protective layer is silicon nitride layer.
7. method according to claim 4, is characterized in that, described inter-level dielectric comprises: lower floor
Silicon dioxide and upper strata
Anti-reflecting layer.
8. according to claim 1～7 described methods of any one, is characterized in that, described substrate is silicon substrate.
9. according to claim 1～7 described methods of any one, is characterized in that, forms inter-level dielectric and adopt chemical vapor deposition method in described substrate.
10. according to claim 1～7 described methods of any one, is characterized in that, described protective layer carried out etching adopt dry etch process.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103378634A CN103094185A (en) | 2011-10-31 | 2011-10-31 | Forming method for contact hole |
| PCT/CN2012/083049 WO2013064014A1 (en) | 2011-10-31 | 2012-10-17 | Method for forming contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103378634A CN103094185A (en) | 2011-10-31 | 2011-10-31 | Forming method for contact hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103094185A true CN103094185A (en) | 2013-05-08 |
Family
ID=48191298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103378634A Pending CN103094185A (en) | 2011-10-31 | 2011-10-31 | Forming method for contact hole |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103094185A (en) |
| WO (1) | WO2013064014A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107482010A (en) * | 2016-06-07 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN108400127A (en) * | 2018-03-07 | 2018-08-14 | 云谷（固安）科技有限公司 | The method for manufacturing capacitor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071812A (en) * | 1998-10-19 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes |
| US6803307B1 (en) * | 2003-06-27 | 2004-10-12 | Macronix International Co., Ltd. | Method of avoiding enlargement of top critical dimension in contact holes using spacers |
| CN101202245A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | System and method for etching |
| CN101355051A (en) * | 2007-07-25 | 2009-01-28 | 东部高科股份有限公司 | Semiconductor device having a copper metal line and method of forming the same |
| US20090267237A1 (en) * | 2005-12-28 | 2009-10-29 | Chee-Hong Choi | Method for manufacturing a semiconductor device |
| CN101764081A (en) * | 2008-12-25 | 2010-06-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing connecting hole |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475811B1 (en) * | 2001-04-27 | 2002-11-05 | Advanced Micro Devices, Inc. | System for and method of using bacteria to aid in contact hole printing |
| CN101295643B (en) * | 2007-04-24 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | Through hole etching method and through hole mask |
-
2011
- 2011-10-31 CN CN2011103378634A patent/CN103094185A/en active Pending
-
2012
- 2012-10-17 WO PCT/CN2012/083049 patent/WO2013064014A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071812A (en) * | 1998-10-19 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes |
| US6803307B1 (en) * | 2003-06-27 | 2004-10-12 | Macronix International Co., Ltd. | Method of avoiding enlargement of top critical dimension in contact holes using spacers |
| US20090267237A1 (en) * | 2005-12-28 | 2009-10-29 | Chee-Hong Choi | Method for manufacturing a semiconductor device |
| CN101202245A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | System and method for etching |
| CN101355051A (en) * | 2007-07-25 | 2009-01-28 | 东部高科股份有限公司 | Semiconductor device having a copper metal line and method of forming the same |
| CN101764081A (en) * | 2008-12-25 | 2010-06-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing connecting hole |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107482010A (en) * | 2016-06-07 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107482010B (en) * | 2016-06-07 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108400127A (en) * | 2018-03-07 | 2018-08-14 | 云谷（固安）科技有限公司 | The method for manufacturing capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013064014A1 (en) | 2013-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9478462B1 (en) | SAV using selective SAQP/SADP | |
| KR20130119213A (en) | Field effect transistor | |
| KR100983693B1 (en) | Method of fabricating vertical transistor in high integrated semiconductor apparatus | |
| US8927386B2 (en) | Method for manufacturing deep-trench super PN junctions | |
| US20190164845A1 (en) | Semiconductor device and manufacturing method therefor | |
| TWI713147B (en) | Method for manufacturing semiconductor device | |
| CN102347212B (en) | Method of forming a layer on a semiconductor substrate having a plurality of trenches | |
| CN104465386A (en) | Method for forming semiconductor structure | |
| CN101673701A (en) | Method for forming shallow trench isolation structure and shallow trench isolation structure | |
| CN107017203A (en) | The manufacture method of semiconductor element | |
| US9768175B2 (en) | Semiconductor devices comprising gate structure sidewalls having different angles | |
| US10224235B2 (en) | Systems and methods for creating airgap seals using atomic layer deposition and high density plasma chemical vapor deposition | |
| CN102254867B (en) | Flash memory manufacturing method | |
| US9214392B1 (en) | Method of forming contact hole and semiconductor structure with contact plug | |
| CN103094185A (en) | Forming method for contact hole | |
| CN105702709A (en) | A manufacturing method for a groove type super junction | |
| CN102931089B (en) | LDMOS device and manufacture method thereof | |
| CN104979173A (en) | Semiconductor structure and forming method thereof | |
| CN106486364B (en) | The forming method of three-dimensional transistor | |
| US8900665B2 (en) | Method of forming hardmask layer with alternating nanolayers | |
| CN104851834A (en) | Semiconductor device preparation method | |
| CN108630549A (en) | Semiconductor devices and forming method thereof | |
| US10573725B1 (en) | Semiconductor structure and manufacturing method thereof | |
| CN103531476A (en) | Manufacturing method for semiconductor device | |
| CN102881625B (en) | Formation methods for isolation structure and semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130508 |