CN104157553A - Double patterning forming method - Google Patents
Double patterning forming method Download PDFInfo
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- CN104157553A CN104157553A CN201410403328.8A CN201410403328A CN104157553A CN 104157553 A CN104157553 A CN 104157553A CN 201410403328 A CN201410403328 A CN 201410403328A CN 104157553 A CN104157553 A CN 104157553A
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- layer
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- photoetching
- formation method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a double patterning forming method. The method comprises steps: step 1, a to-be-etched layer, a hard mask layer and a first photoresist layer are sequentially arranged on the surface of a wafer substrate, and a first photoresist pattern of the pattern photoresist layer is formed through first photoetching ; step 2, a protective film is grown so as to cover the first photoresist pattern and the exposed hard mask layer; step 3, a second photoresist layer is arranged on the protective film and second photoetching is carried out on the second photoresist layer so as to form a second photoresist pattern on the protective film; and step 4, dry etching is executed, the first photoresist pattern and the second photoresist pattern are transferred to the to-be-etched layer so as to obtain the pattern of the to-be-etched layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of Dual graphing formation method.
Background technology
Under driving at semiconductor technology in Moore's Law, stride forward towards less process node constantly.Along with the continuous progress of semiconductor technology, the function of device is gradually become strong, but semiconductor manufacture difficulty also grows with each passing day.And photoetching technique is production technology the most key in semiconductor fabrication process, along with semiconductor technology node enters into 45 nanometers, 32 nanometers, 22,16 even lower nanometers.The step that continues to extend forward when Moore's Law is irreversible time, Dual graphing technology becomes the optimal selection of industry undoubtedly, Dual graphing technology only need to be carried out very little change to existing photoetching infrastructure, just can effectively fill up 45 nanometers to the even more photoetching technique blank of minor node of 32 nanometers.
A set of highdensity circuitous pattern is resolved into the figure that two covers are discrete, density is lower by the principle of Dual graphing technology, then they is prepared on wafer.The simplification of typical Dual graphing technological process comprises photoetching-etching-photoetching-etching (LELE).
LELE technique is a kind of well Dual graphing formation method, but technological process more complicated, and cost is high.In order to reduce process costs, someone has proposed the Double-patterning method of LLE.This technique is to form after pattern in photoetching for the first time, by a kind of special chemical substance to photoresist modifying surface.(for example can reduce a lot of technique owing to reducing by an etch step, additional hard mask and the deposition process of etching barrier layer), the LLE Dual graphing of realizing is by this way compared LELE Dual graphing or significant (can reduce etch step one time, and the step such as the thin film deposition of associated).But in actual process, said method has still increased some additional steps, wherein need before photoetching for the second time, increase modified material covering-baking-modified material and remove three technological processes.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of Dual graphing formation method that can realize the simplification of technological process and the reduction of cost is provided.
In order to realize above-mentioned technical purpose, according to the present invention, a kind of Dual graphing formation method is provided, comprise: first step, arrange successively layer to be etched, hard mask layer and the first photoresist layer on wafer substrate surface, and form the first photoetching agent pattern of pattern photoresist layer by photoetching for the first time; Second step, the hard mask layer of growth protecting film to cover the first photoetching agent pattern and to come out; Third step, arranges the second photoresist layer at diaphragm, and the second photoresist layer is carried out to photoetching for the second time to form the second photoetching agent pattern on diaphragm; The 4th step, carries out dry etching, the first photoetching agent pattern and the second photoetching agent pattern is transferred to layer to be etched, to obtain the pattern of layer to be etched.
Preferably, the pattern of layer to be etched comprises first pattern corresponding with the first photoetching agent pattern and second pattern corresponding with the second photoetching agent pattern.
Preferably, described layer to be etched is the polysilicon layer that is used to form polysilicon gate.
Preferably, second step utilizes the mode growth protecting film of ald.
Preferably, described diaphragm is silica and/or silicon nitride.
Preferably, second step utilizes diaphragm described in the plasma-enhanced ald of technological temperature below 100 DEG C.
Preferably, the thickness of diaphragm is 10-30A.
Preferably, the size of the first photoetching agent pattern equals final desired size and deducts twice diaphragm thickness.
In the present invention, after photoengraving pattern for the first time forms, do not need with surface modification material, the optical cement on wafer to be processed, but directly for example, with the mode of the ald very thin diaphragm of one deck of growing, silicon oxide film.Then enter photoetching process for the second time, due to the existence of silica diaphragm, the optical cement pattern forming after photoetching for the first time can't contact with the photoresist of the coating of photoetching for the second time, does not also just have the interference of dissolving each other between photoresist.The technical method proposing by the present invention, can realize LLE mode double-pattern metallization processes equally.And flow process is more simple, cost is also lower.
Brief description of the drawings
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its advantage of following and feature, wherein:
Fig. 1 to Fig. 4 schematically shows each step of Dual graphing formation method according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 to Fig. 4 schematically shows each step of Dual graphing formation method according to the preferred embodiment of the invention.
Specifically, as shown in Figures 1 to 4, Dual graphing formation method comprises according to the preferred embodiment of the invention:
First step, arrange successively layer to be etched 20 (being for example used to form the polysilicon layer of polysilicon gate), hard mask layer 30 and the first photoresist layer on wafer substrate 10 surfaces, and form the first photoetching agent pattern 40 of pattern photoresist layer by photoetching for the first time; As shown in Figure 1.
Second step, utilizes the mode growth protecting film 50 (for example silica, silicon nitride etc.) of ALD (ald, Step Coverage power can reach 100%) to cover the first photoetching agent pattern 40 and the hard mask layer 30 coming out; As shown in Figure 2.
In second step; because photoetching agent pattern can not be high temperature resistant; in order to prevent that photoresist from deforming in diaphragm deposition process, can select PEALD (plasma-enhanced ald) the silicon oxide film depositing operation of technological temperature below 100 DEG C.
In second step, preferably, the thickness of diaphragm 50 is 10-30A.
In second step, the thickness of diaphragm 50 can affect the characteristic size of follow-up structure, and characteristic size design when photoetching for the first time need to be taken this factor into account (exactly the size of photoetching agent pattern being designed smallerly accordingly in brief); Particularly, the size of the first photoetching agent pattern 40 equals final desired size and deducts twice diaphragm 50 thickness.
Third step, arranges the second photoresist layer at diaphragm 50, and the second photoresist layer is carried out to photoetching for the second time to form the second photoetching agent pattern 60 on diaphragm 50.In this step, the first photoetching agent pattern 40 forming due to photoetching for the first time has had the protection of diaphragm 50, so can not affected by photoetching process for the second time; So the structure obtaining as shown in Figure 3.
On the second photoetching agent pattern 60 due to without covered with protective film 50 again, so the size of the second photoetching agent pattern 60 can equal final desired size.
The 4th step, carries out dry etching, the first photoetching agent pattern 40 and the second photoetching agent pattern 60 is transferred to layer 20 to be etched, to obtain the pattern of needed layer 20 to be etched; As shown in Figure 4, the pattern of needed layer 20 to be etched comprises first pattern 21 corresponding with the first photoetching agent pattern 40 and second pattern 22 corresponding with the second photoetching agent pattern 60.
In the present invention, after photoengraving pattern for the first time forms, do not need with surface modification material, the optical cement on wafer to be processed, but directly for example, with the mode of the ald very thin diaphragm of one deck of growing, silicon oxide film.Then enter photoetching process for the second time, due to the existence of silica diaphragm, the optical cement pattern forming after photoetching for the first time can't contact with the photoresist of the coating of photoetching for the second time, does not also just have the interference of dissolving each other between photoresist.The technical method proposing by the present invention, can realize LLE mode double-pattern metallization processes equally.And flow process is more simple, cost is also lower.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as term " first " in specification, " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., instead of for representing logical relation or the ordinal relation etc. between each assembly, element, step.
Be understandable that, although the present invention discloses as above with preferred embodiment, but above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. a Dual graphing formation method, is characterized in that comprising:
First step, arranges layer to be etched, hard mask layer and the first photoresist layer successively on wafer substrate surface, and forms the first photoetching agent pattern of pattern photoresist layer by photoetching for the first time;
Second step, the hard mask layer of growth protecting film to cover the first photoetching agent pattern and to come out;
Third step, arranges the second photoresist layer at diaphragm, and the second photoresist layer is carried out to photoetching for the second time to form the second photoetching agent pattern on diaphragm;
The 4th step, carries out dry etching, the first photoetching agent pattern and the second photoetching agent pattern is transferred to layer to be etched, to obtain the pattern of layer to be etched.
2. Dual graphing formation method according to claim 1, is characterized in that, the pattern of layer to be etched comprises first pattern corresponding with the first photoetching agent pattern and second pattern corresponding with the second photoetching agent pattern.
3. Dual graphing formation method according to claim 1 and 2, is characterized in that, described layer to be etched is the polysilicon layer that is used to form polysilicon gate.
4. Dual graphing formation method according to claim 1 and 2, is characterized in that, second step utilizes the mode growth protecting film of ald.
5. Dual graphing formation method according to claim 1 and 2, is characterized in that, described diaphragm is silica and/or silicon nitride.
6. Dual graphing formation method according to claim 1 and 2, is characterized in that, second step utilizes diaphragm described in the plasma-enhanced ald of technological temperature below 100 DEG C.
7. Dual graphing formation method according to claim 1 and 2, is characterized in that, the thickness of diaphragm is 10-30A.
8. Dual graphing formation method according to claim 1 and 2, is characterized in that, the size of the first photoetching agent pattern equals final desired size and deducts twice diaphragm thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410403328.8A CN104157553A (en) | 2014-08-15 | 2014-08-15 | Double patterning forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410403328.8A CN104157553A (en) | 2014-08-15 | 2014-08-15 | Double patterning forming method |
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| CN104157553A true CN104157553A (en) | 2014-11-19 |
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| CN201410403328.8A Pending CN104157553A (en) | 2014-08-15 | 2014-08-15 | Double patterning forming method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116685A (en) * | 2015-09-24 | 2015-12-02 | 京东方科技集团股份有限公司 | Making method of photoresist pattern, color filter and display device |
| CN109411334A (en) * | 2017-08-17 | 2019-03-01 | 南亚科技股份有限公司 | The fine line pattern forming method of semiconductor element |
| CN114038739A (en) * | 2021-10-27 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method of polycrystalline silicon |
-
2014
- 2014-08-15 CN CN201410403328.8A patent/CN104157553A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116685A (en) * | 2015-09-24 | 2015-12-02 | 京东方科技集团股份有限公司 | Making method of photoresist pattern, color filter and display device |
| CN105116685B (en) * | 2015-09-24 | 2019-10-01 | 京东方科技集团股份有限公司 | A kind of production method of photoetching agent pattern, colored filter and display device |
| CN109411334A (en) * | 2017-08-17 | 2019-03-01 | 南亚科技股份有限公司 | The fine line pattern forming method of semiconductor element |
| CN114038739A (en) * | 2021-10-27 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method of polycrystalline silicon |
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Application publication date: 20141119 |