CN111725137B - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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CN111725137B
CN111725137B CN201910212132.3A CN201910212132A CN111725137B CN 111725137 B CN111725137 B CN 111725137B CN 201910212132 A CN201910212132 A CN 201910212132A CN 111725137 B CN111725137 B CN 111725137B
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layer
forming
fin
semiconductor substrate
etching
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CN111725137A (en
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纪世良
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The embodiment of the invention provides a method for forming a semiconductor device. According to the embodiment of the invention, the second shallow trench isolation structure is formed by etching the scheduled fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.

Description

Method for forming semiconductor device
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device.
Background
With the continued development of integrated circuit fabrication processes, the feature sizes of existing integrated circuits are continually decreasing.
However, defects occur in the existing semiconductor devices, and the yield of the semiconductor devices is to be improved.
Disclosure of Invention
In view of this, an embodiment of the present invention provides a method for forming a semiconductor device, including:
providing a semiconductor substrate, wherein a plurality of fin parts are formed on the semiconductor substrate, and the area between the adjacent fin parts is a first interval area or a second interval area;
forming a stop layer covering the semiconductor substrate and the fin portion;
forming a dielectric layer covering the stop layer;
etching the semiconductor substrate in the first interval area to form a first shallow trench isolation structure;
and etching at least one fin part and the semiconductor substrate below at least one fin part between adjacent first shallow trench isolation structures to form a second shallow trench isolation structure.
Further, the dielectric layer is made of silicon oxide, and the stop layer comprises a silicon layer.
Further, the stop layer also includes a silicon oxide layer located below the silicon layer.
Further, the first pitch region has a size greater than a size of the second pitch region.
Further, before the etching the semiconductor substrate of the first pitch region, the method further comprises:
and etching the dielectric layer of the first interval area.
Further, after the etching of the semiconductor substrate of the first pitch region, the method further comprises:
and removing the dielectric layer by adopting a wet etching process.
Further, after the dielectric layer is removed by adopting the wet etching process, the method further comprises:
oxidizing the silicon layer in the stop layer.
Further, after the oxidizing the stop layer, the method further comprises:
and removing the stop layer by adopting a wet etching process.
Further, before the etching the predetermined fin portion and the semiconductor substrate under the fin portion, the method further includes:
forming a protective layer covering the fin part;
and forming a mask layer covering the protective layer, wherein the mask layer is provided with an opening above the scheduled fin part.
Further, after the etching the predetermined fin portion and the semiconductor substrate under the fin portion, the method further includes:
removing the mask layer by adopting a stripping process;
and removing the protective layer by adopting a wet etching process.
Further, after the protective layer is removed by adopting a wet etching process, the method further comprises:
and removing the stop layer by adopting a wet etching process.
According to the embodiment of the invention, the second shallow trench isolation structure is formed by etching the scheduled fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of one memory cell of an SRAM device;
FIG. 2 is a top view of the structure of one memory cell of the SRAM device;
FIGS. 3 and 4 are schematic cross-sectional views of fins of an SRAM;
fig. 5 to 8 are schematic views showing the structures of the steps of the method for forming the semiconductor device of the comparative example;
fig. 9 is a schematic view of a structure having defects formed by the method of forming a semiconductor device of the comparative example;
fig. 10 to 11 are schematic views showing the structure of each step of a method for forming a semiconductor device of another comparative example;
fig. 12 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 13 to 24 are schematic views showing the structure of each step of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, unless otherwise indicated, "multiple layers" means two or more layers.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Spatially relative terms, such as "under …," "under," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below" is intended to encompass both an orientation of above and below. The device may take other orientations (rotated 90 degrees or at other orientations), and the spatial relationship descriptors used herein interpreted accordingly.
A Static Random-Access Memory (SRAM) is one type of Random Access Memory. Taking SRAM as an example, a circuit diagram of one memory cell of the SRAM is shown in fig. 1, and the one memory cell of the SRAM includes six field effect transistors PU1, PU2, PD1, PD2, PG1, and PG 2. Fig. 2 is a top view of the structure of one memory cell of the SRAM. As shown in fig. 2, the SRAM includes a fin 11 and a gate structure 16. In the process of forming the structure shown in fig. 2, a plurality of fins with the same interval are formed first, and since different types of semiconductor structures need to be formed, the fins of a partial region need to be etched. Fig. 3 and 4 are schematic cross-sectional views of fins of an SRAM. During formation of the structure shown in fig. 3, the fin of region 1 is etched. In the process of forming the structure shown in fig. 4, the fin portion of the region 1 and the fin portion of the region 2 need to be etched, and the semiconductor substrate of the region 2 needs to be etched, so that a shallow trench isolation structure is formed. In a subsequent process, a patterned gate structure is formed on the fin portion, so that different transistors PU1, PU2, PD1, PD2, PG1, PG2, and the like are formed on the semiconductor substrate to form a memory cell of the SRAM having the circuit structure shown in fig. 1. However, due to the ever decreasing feature sizes of semiconductor devices, existing devices are unable to manufacture satisfactory fin pitches in smaller node process flows. Meanwhile, the size of the shallow trench isolation region cannot reach the target size. The existing production process cannot ensure the performance of the semiconductor device.
In one comparative example, a method of forming a semiconductor device includes the steps of:
step S1, etching a preset fin portion.
And S2, forming an oxide layer covering the fin part.
Step S3, etching the preset area to form a shallow trench isolation structure (Shallow Trench Isolation, STI).
In step S1, a predetermined fin 11 is etched.
Specifically, as shown in fig. 5, a dielectric layer 12 and a photoresist layer 13 are respectively formed above the fin 11. The photoresist layer 13 has an opening above the predetermined fin 11. As shown in fig. 6, the opening region of the photoresist layer is etched to remove the predetermined fin portion.
And removing the photoresist layer and the dielectric layer after removing the scheduled fin parts.
In step S2, an oxide layer 14 is formed to cover the fin 11.
Specifically, as shown in fig. 7, an oxide layer 14 is formed to cover the fin 11.
In step S3, a predetermined region is etched to form a shallow trench isolation structure 15.
Specifically, as shown in fig. 8, a predetermined region is etched to form a shallow trench isolation structure 15.
However, this method may result in defects, such as region 3 in fig. 9, and the profile of the shallow trench isolation structure is irregular. Further, after etching the predetermined fin portion 11, silicon remains, and the etching depth may be insufficient. These defects all affect the yield of semiconductor devices.
The defect is generated mainly because the etching of the fin part and the formation of the shallow trench isolation structure below the fin part are formed in two steps, so that the defect is easier to form.
In another comparative example, a method of forming a semiconductor device includes the steps of:
and S4, forming a photoresist layer.
And S5, etching the preset area to form the shallow trench isolation structure.
As shown in fig. 10, in step S4, a photoresist layer 21 is formed.
Specifically, a dielectric layer 14 is covered above the fin portion 11 of the semiconductor substrate, and a mask layer is formed on the dielectric layer, where the mask layer has an opening in a predetermined area.
As shown in fig. 11, in step S5, a predetermined region is etched to form a shallow trench isolation structure 15.
It should be understood that in this embodiment, 4 fins are spaced between two shallow trench isolation structures, and in other implementations, 3 fins may be spaced between two shallow trench isolation structures, which is not limited herein.
In this comparative example, due to the reduction of the fin pitch, the adjacent predetermined regions are too close to each other, resulting in no Process Window (PW) and no photolithographic condition can be achieved. The two mask plates are required to be overlapped to realize etching, so that etching deviation can occur to influence the performance of the semiconductor device.
In view of this, the embodiment of the invention provides a method for forming a semiconductor device, which can solve the defects in the process of forming the semiconductor device in the comparative example and improve the yield of the semiconductor device. The embodiment of the present invention is described by taking the formation of SRAM as an example, and it should be understood that the method described in the embodiment of the present invention may also be used to form other semiconductor devices.
Fig. 12 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention. As shown in fig. 12, the method for forming a semiconductor device according to an embodiment of the present invention includes the steps of:
step S100, a semiconductor substrate is provided. The semiconductor substrate is provided with a plurality of fin parts, and the area between every two adjacent fin parts is a first interval area or a second interval area.
And step 200, forming a stop layer covering the semiconductor substrate and the fin portion.
And step S300, forming a dielectric layer covering the stop layer.
Step S400, etching the semiconductor substrate in the first interval area. Forming a first shallow trench isolation structure.
And S500, etching at least one fin part and the semiconductor substrate below at least one fin part between adjacent first shallow trench isolation structures to form a second shallow trench isolation structure.
Optionally, before step S400, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
step S400a, etching the dielectric layer in the first pitch area.
Optionally, after step S400, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and step 400b, removing the dielectric layer by adopting a wet etching process.
Optionally, before step S500 or after step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and step S500a, oxidizing the silicon layer in the stop layer.
Optionally, before step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and step S500b, forming a protective layer covering the fin part.
And step S500c, forming a mask layer covering the protective layer, wherein openings are formed above the scheduled fin parts of the mask layer.
Optionally, after step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and S500d, removing the mask layer by adopting a stripping process.
And step S500e, removing the protective layer by adopting a wet etching process.
And S500f, removing the stop layer by adopting a wet etching process.
As shown in fig. 13, in step S100, the semiconductor substrate 10 is provided. The semiconductor substrate is formed with a plurality of fins 101, and the area between adjacent fins 101 is a first pitch area 102 or a second pitch area 103. Wherein the size of the first pitch area 102 is larger than the size of the second pitch area 103.
Optionally, an isolation layer (not shown) is further formed above the fin 101.
The semiconductor substrate 10 in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. Preferably, the semiconductor substrate 10 is a silicon single crystal substrate. A plurality of structures such as an epitaxial interface layer or a strain layer may be formed on the surface of the semiconductor substrate 10 to improve the electrical performance of the semiconductor device.
As shown in fig. 14, in step S200, a stop layer 20 is formed to cover the semiconductor substrate 10 and the fin 101.
Specifically, the stop layer 20 includes a silicon layer. The stop layer 20 also includes a silicon oxide layer located below the silicon layer. The thickness of the stop layer 20 is thinner, and the thickness of the two stop layers 20 is smaller than the interval between the fin portions 101. Alternatively, the thickness of the silicon oxide layer in the stop layer 20 is about 100 angstroms. The silicon oxide layer may be formed using an atomic layer deposition process.
The stop layer 20 is used for protecting the fin 101, so as to avoid damaging the fin 101 in a subsequent etching process. The stop layer 20 includes a silicon layer and a silicon oxide layer, which have different etching rates under the same etching conditions, thereby better protecting the fin 101.
As shown in fig. 15, in step S300, a dielectric layer 30 is formed to cover the stop layer 20.
The dielectric layer 30 is used to fill up the gaps of the fin portion to form a flat surface, so that a mask is formed over the fin portion.
Specifically, the material of the dielectric layer 30 may be silicon oxide (SiO 2 ) Silicon nitride (Si) 3 N 4 ) And insulating materials such as silicon oxynitride (SiON).
The dielectric layer 30 may be formed by any technique known to those skilled in the art, preferably by chemical vapor deposition (Chemical Vapor Deposition, CVD), such as low temperature chemical vapor deposition (Low Temperature Chemical Vapor Deposition, LTCVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), rapid thermal chemical vapor deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD), atomic layer deposition (Atomics Layer Deposition, ALD) process, ion-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), and the like. An atomic layer deposition process is preferably employed to form dense silicon oxide.
As shown in fig. 16, in step S400a, the dielectric layer 30 of the first pitch region 102 is etched.
Specifically, the dielectric layer 30 of the first pitch region 102 is removed. A wet etch process may be used to remove the dielectric layer 30.
In an alternative implementation, two different etching methods may be used to etch the dielectric layer 30 of the first pitch region 102 and the stop layer 20 of the first pitch region sequentially. To expose the semiconductor substrate 10 in the first pitch region.
As shown in fig. 17, in step S400, the semiconductor substrate 10 of the first pitch region 102 is etched. A first shallow trench isolation structure 104 is formed.
Specifically, the first pitch region 102 is etched to form a first shallow trench isolation structure 104.
In this step, a specific etching method may be employed such that the etching rate of the semiconductor substrate is greater than the etching rate of the dielectric layer. Thus, the semiconductor substrate 10 in the first pitch region 102 can be etched using the dielectric layer 30 and the stop layer 20 as masks, and the first shallow trench isolation structure 104 can be formed in the first pitch region 102.
As shown in fig. 18, in step S400b, the dielectric layer 30 is removed by a wet etching process.
In this step, all of the dielectric layer 30 is removed and the cross-section of the semiconductor structure after removal is shown in fig. 18.
In this step, the stop layer includes a silicon layer, and the etching process for removing the dielectric layer 30 does not etch or does not etch the silicon layer less, so that the stop layer can function to protect the fin portion and the semiconductor substrate.
As shown in fig. 19, in step S500a, the silicon layer in the stop layer 20 is oxidized.
Specifically, the silicon layer in the stop layer 20 may be oxidized by a thermal oxidation method. A new stop layer 20' of silicon oxide is formed.
As shown in fig. 20, in step S500b, a protection layer 40 is formed to cover the fin 11.
The protection layer 40 is used to fill the gaps of the fin 11, so as to form a flat plane above the fin, so that a mask pattern can be formed on the protection layer 40.
Specifically, the material of the protective layer 40 may be an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.
In an alternative implementation, the material of the protective layer 40 is silicon oxide.
Specifically, the method for forming the protective layer 40 may employ any technique known to those skilled in the art, preferably a chemical vapor deposition method, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.
In step S500c, a mask layer 50 is formed to cover the protection layer 40, the mask layer 50 having an opening above the predetermined fin 101.
Specifically, the mask layer 50 is formed by coating a photoresist on the protective layer 40, and curing the photoresist by using a photolithography process to form the mask layer 50 having a predetermined pattern.
As shown in fig. 21, in step S500, at least one of the fins 101 and the semiconductor substrate 10 under at least one of the fins 101 between adjacent first shallow trench isolation structures 104 are etched to form a second shallow trench isolation structure 105.
Specifically, an etching method capable of etching the dielectric layer, the stop layer and the fin portion at substantially the same etching rate may be selected. Such as plasma etching. In particular, CF may be employed 4 /H 2 Or CHF 3 As a plasma etching process of the etching gas, a predetermined fin 101 and the semiconductor substrate 10 under the fin 101 are etched.
In this embodiment, the etching of the fin 101 and the semiconductor substrate under the fin 101 is completed in one step, so that various defects in the comparative example can be avoided.
It should be understood that in the embodiment of the present invention, one fin portion between two adjacent first shallow trench isolation structures is etched, and in other embodiments, other portions of the fin portion may be etched according to the needs of different devices, or two adjacent fin portions between two adjacent first shallow trench isolation structures may be etched and removed at the same time.
As shown in fig. 22, in step S500d, the mask layer 50 is removed by a lift-off process.
Specifically, the mask layer 50 is removed mainly by two methods, first, oxygen (O 2 ) Carrying out dry etching, and carrying out chemical reaction between oxygen and the photoresist to remove the photoresist; second, wet stripping methods, e.g., sulfuric acid (H 2 SO 4 ) And hydrogen peroxide (H) 2 O 2 ) The photoresist may be removed.
As shown in fig. 23, in step S500e, the protective layer 40 is removed by a wet etching process.
As shown in fig. 24, in step S500f, the stop layer 20' is removed by a wet etching process.
Alternatively, when the material of the protective layer 40 and the material of the stop layer 20 'are both silicon oxide, the stop layer 20' and the protective layer 40 may be removed in the same wet etching process. Therefore, the process flow can be reduced, and the efficiency can be improved.
In another alternative implementation manner, the method for forming the semiconductor device according to the embodiment of the invention includes the following steps:
step S100, a semiconductor substrate is provided. The semiconductor substrate is provided with a plurality of fin parts, and the area between every two adjacent fin parts is a first interval area or a second interval area.
And step 200, forming a stop layer covering the semiconductor substrate and the fin portion.
And step S300, forming a dielectric layer covering the stop layer.
Step S400a, etching the dielectric layer in the first pitch area.
Step S400, etching the semiconductor substrate in the first interval area. Forming a first shallow trench isolation structure.
And step 400b, removing the dielectric layer by adopting a wet etching process.
And step S500b, forming a protective layer covering the fin part.
And step S500c, forming a mask layer covering the protective layer, wherein openings are formed above the scheduled fin parts of the mask layer.
And S500, etching at least one fin part and the semiconductor substrate below at least one fin part between adjacent first shallow trench isolation structures to form a second shallow trench isolation structure.
And S500d, removing the mask layer by adopting a stripping process.
And step S500e, removing the protective layer by adopting a wet etching process.
And step S500a, oxidizing the silicon layer in the stop layer.
In this embodiment, the first shallow trench isolation structure is formed by two different etching processes of step S400a and step S400. It should be appreciated that in yet another alternative implementation, an etching method capable of etching the dielectric layer 30, the stop layer 20, and the semiconductor substrate at similar rates may be selected, and predetermined regions of the dielectric layer 30, the stop layer 20, and the semiconductor substrate 10 may be etched at step S400a and step S400. For example, a plasma etching method is used to remove the dielectric layer 30, the stop layer 20 and the semiconductor substrate 10 in a predetermined region.
In the subsequent process, masks with different shapes are adopted to etch the structure, and a grid structure, a source region, a drain region, a metal interconnection structure and the like are formed, so that a complete semiconductor device is obtained. The stop layer may be removed during a subsequent etching process.
According to the embodiment of the invention, the second shallow trench isolation structure is formed by etching the scheduled fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein a plurality of fin parts are formed on the semiconductor substrate, and the area between the adjacent fin parts is a first interval area or a second interval area;
forming a stop layer covering the semiconductor substrate and the fin portion, wherein the stop layer comprises a silicon layer;
forming a dielectric layer covering the stop layer;
etching the semiconductor substrate in the first interval area to form a first shallow trench isolation structure;
oxidizing the silicon layer in the stop layer to form a new stop layer made of silicon oxide;
and etching at least one fin part and the semiconductor substrate below at least one fin part between adjacent first shallow trench isolation structures to form a second shallow trench isolation structure.
2. The method of claim 1, wherein the dielectric layer is silicon oxide.
3. The method of forming of claim 2, wherein the stop layer further comprises a silicon oxide layer located below the silicon layer.
4. The method of forming of claim 1, wherein the first pitch region has a size that is greater than a size of the second pitch region.
5. The method of forming of claim 1, wherein prior to said etching said semiconductor substrate of said first pitch region, said method further comprises:
and etching the dielectric layer of the first interval area.
6. The method of forming of claim 1, wherein after said etching said semiconductor substrate of said first pitch region, said method further comprises:
and removing the dielectric layer by adopting a wet etching process.
7. The method of forming of claim 1, wherein after the oxidizing the stop layer, the method further comprises:
and removing the stop layer by adopting a wet etching process.
8. The method of forming of claim 1, wherein prior to the etching the predetermined fin and the semiconductor substrate below the fin, the method further comprises:
forming a protective layer covering the fin part;
and forming a mask layer covering the protective layer, wherein the mask layer is provided with an opening above the scheduled fin part.
9. The method of forming of claim 8, wherein after the etching the predetermined fin and the semiconductor substrate under the fin, the method further comprises:
removing the mask layer by adopting a stripping process;
and removing the protective layer by adopting a wet etching process.
10. The method of forming of claim 9, wherein after removing the protective layer using a wet etching process, the method further comprises:
and removing the stop layer by adopting a wet etching process.
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