CN111725137B - Method for forming semiconductor device - Google Patents

Abstract

The embodiment of the invention provides a method for forming a semiconductor device. According to the embodiment of the invention, the second shallow trench isolation structure is formed by etching the scheduled fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.

Description

A method of forming a semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device.

Background technique

With the continuous development of the manufacturing process of integrated circuits, the feature size of existing integrated circuits is continuously reduced.

However, defects may occur in existing semiconductor devices, and the yield of semiconductor devices needs to be improved.

Contents of the invention

In view of this, an embodiment of the present invention provides a method for forming a semiconductor device, the method comprising:

A semiconductor substrate is provided, and a plurality of fins are formed on the semiconductor substrate, and the area between adjacent fins is a first pitch area or a second pitch area;

forming a stop layer overlying the semiconductor substrate and the fin;

forming a dielectric layer covering the stop layer;

Etching the semiconductor substrate in the first pitch region to form a first shallow trench isolation structure;

Etching at least one of the fins between adjacent first shallow trench isolation structures and the semiconductor substrate under at least one of the fins to form a second shallow trench isolation structure.

Further, the material of the dielectric layer is silicon oxide, and the stop layer includes a silicon layer.

Further, the stop layer further includes a silicon oxide layer under the silicon layer.

Further, the size of the first spacing area is larger than the size of the second spacing area.

Further, before etching the semiconductor substrate in the first pitch region, the method further includes:

Etching the dielectric layer in the first distance region.

Further, after the etching of the semiconductor substrate in the first pitch region, the method further includes:

The dielectric layer is removed by wet etching process.

Further, after removing the dielectric layer by using a wet etching process, the method further includes:

Oxidizing the silicon layer in the stop layer.

Further, after the oxidation of the stop layer, the method further includes:

The stop layer is removed by a wet etching process.

Further, before etching the predetermined fin and the semiconductor substrate below the fin, the method further includes:

forming a protective layer covering the fin;

A mask layer is formed covering the protection layer, the mask layer having openings above predetermined fins.

Further, after etching the predetermined fin and the semiconductor substrate below the fin, the method further includes:

removing the mask layer by a lift-off process;

The protective layer is removed by wet etching process.

Further, after the protective layer is removed by a wet etching process, the method further includes:

The stop layer is removed by a wet etching process.

In the embodiment of the present invention, the second shallow trench isolation structure is formed by etching predetermined fins and the semiconductor substrate below the fins. The formation of defects in the semiconductor device can be avoided, and the yield rate of the semiconductor device can be improved.

Description of drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:

Fig. 1 is the circuit diagram of a storage unit of SRAM device;

Fig. 2 is the top view of the structure of a memory unit of SRAM device;

3 and 4 are schematic cross-sectional views of the fins of the SRAM;

5-8 are structural schematic diagrams of each step of a method for forming a semiconductor device of a comparative example;

9 is a schematic diagram of a structure with defects formed by a method for forming a semiconductor device of a comparative example;

10-11 are schematic structural diagrams of each step of a method for forming a semiconductor device of another comparative example;

12 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

13-24 are schematic structural diagrams of each step of the method for forming a semiconductor device according to an embodiment of the present invention.

Detailed ways

The present invention is described below based on examples, but the present invention is not limited to these examples. In the following detailed description of the invention, some specific details are set forth in detail. The present invention can be fully understood by those skilled in the art without the description of these detailed parts. In order not to obscure the essence of the present invention, well-known methods, procedures, procedures, components and circuits have not been described in detail.

Additionally, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires, throughout the specification and claims, "comprises", "comprises" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive meaning; that is, "including but not limited to" meaning. In the description of the present invention, unless otherwise specified, "multilayer" means two or more layers.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. Spatial terms such as "under", "below", "below", "above", "on" may be used herein for the convenience of description to describe an element as shown in the accompanying drawings or the relationship between a feature and another element or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A static random-access memory (Static Random-Access Memory, SRAM) is a type of random-access memory. Taking SRAM as an example, a circuit diagram of a storage unit of the SRAM is shown in FIG. 1 , and a storage unit of the SRAM includes six field effect transistors PU1, PU2, PD1, PD2, PG1 and PG2. FIG. 2 is a top view of the structure of a memory cell of the SRAM. As shown in FIG. 2 , the SRAM includes a fin 11 and a gate structure 16 . In the process of forming the structure shown in FIG. 2 , a plurality of fins at the same intervals are first formed, and because different types of semiconductor structures need to be formed, the fins in some regions need to be etched. 3 and 4 are schematic cross-sectional views of the fins of the SRAM. During the formation of the structure as shown in FIG. 3 , the fins of region 1 are etched. In the process of forming the structure shown in FIG. 4 , it is necessary to etch the fins in the region 1 and the fins in the region 2 , and etch the semiconductor substrate in the region 2 to form a shallow trench isolation structure. In the subsequent process, a patterned gate structure is formed on the fin, thereby forming different transistors such as PU1, PU2, PD1, PD2, PG1, and PG2 on the semiconductor substrate, so as to form the The storage unit of the SRAM showing the circuit structure. However, due to the continuous reduction of the feature size of semiconductor devices, the existing equipment cannot manufacture fin pitches that meet the requirements in the process of smaller nodes. At the same time, the size of the shallow trench isolation region cannot reach the target size. Existing production processes cannot ensure the performance of semiconductor devices.

In a comparative example, a method for forming a semiconductor device includes the following steps:

Step S1, etching predetermined fins.

Step S2 , forming an oxide layer covering the fins.

Step S3 , etching a predetermined area to form a shallow trench isolation structure (Shallow Trench Isolation, STI).

In step S1, predetermined fins 11 are etched.

Specifically, as shown in FIG. 5 , a dielectric layer 12 and a photoresist layer 13 are respectively formed above the fins 11 . The photoresist layer 13 has an opening above the predetermined fin 11 . As shown in FIG. 6 , the opening area of the photoresist layer is etched to remove predetermined fins.

After the predetermined fins are removed, the photoresist layer and the dielectric layer are removed.

In step S2 , an oxide layer 14 covering the fin portion 11 is formed.

Specifically, as shown in FIG. 7 , an oxide layer 14 covering the fin portion 11 is formed.

In step S3 , a predetermined area is etched to form a shallow trench isolation structure 15 .

Specifically, as shown in FIG. 8 , a predetermined area is etched to form a shallow trench isolation structure 15 .

However, using this method will form defects as shown in area 3 in FIG. 9 , and the contour of the shallow trench isolation structure is irregular. In addition, after the predetermined fin portion 11 is etched, silicon remains and the etching depth is insufficient. These defects all affect the yield of semiconductor devices.

The main reason for the defects is that the etching of the fin and the formation of the shallow trench isolation structure under the fin are formed in two steps, which makes it easier to form defects.

In another comparative example, a method for forming a semiconductor device includes the following steps:

Step S4, forming a photoresist layer.

Step S5 , etching a predetermined area to form a shallow trench isolation structure.

As shown in FIG. 10 , in step S4 , a photoresist layer 21 is formed.

Specifically, a dielectric layer 14 is covered above the fin portion 11 of the semiconductor substrate, and a mask layer is formed on the dielectric layer, and the mask layer has an opening in a predetermined area.

As shown in FIG. 11 , in step S5 , a predetermined area is etched to form a shallow trench isolation structure 15 .

It should be understood that, in this embodiment, there are 4 fins between the two shallow trench isolation structures. In other implementations, there may be 3 fins between the two shallow trench isolation structures. Do limit.

In this comparative example, due to the narrowing of the pitch of the fins, the distance between the adjacent predetermined regions is too close, resulting in no process window (Process Window, PW), and the photolithography conditions cannot be achieved. It is necessary to overlap two mask plates to achieve etching, which will cause etching deviation and affect the performance of semiconductor devices.

In view of this, an embodiment of the present invention provides a method for forming a semiconductor device, which can solve the defects in the process of forming the semiconductor device in the comparative example, and improve the yield of the semiconductor device. The embodiment of the present invention is described by taking the formation of an SRAM as an example. It should be understood that the method described in the embodiment of the present invention can also be used to form other semiconductor devices.

FIG. 12 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention. As shown in FIG. 12, the method for forming a semiconductor device according to the embodiment of the present invention includes the following steps:

Step S100, providing a semiconductor substrate. Wherein, a plurality of fins are formed on the semiconductor substrate, and a region between adjacent fins is a first pitch region or a second pitch region.

Step S200, forming a stop layer covering the semiconductor substrate and the fins.

Step S300, forming a dielectric layer covering the stop layer.

Step S400, etching the semiconductor substrate in the first pitch region. A first shallow trench isolation structure is formed.

Step S500 , etching at least one of the fins between adjacent first STI structures and the semiconductor substrate under at least one of the fins to form a second STI structure.

Optionally, before step S400, the method for forming a semiconductor device according to the embodiment of the present invention further includes:

Step S400a, etching the dielectric layer in the first distance region.

Optionally, after step S400, the method for forming a semiconductor device according to the embodiment of the present invention further includes:

Step S400b, using a wet etching process to remove the dielectric layer.

Optionally, before step S500 or after step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:

Step S500a, oxidizing the silicon layer in the stop layer.

Optionally, before step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:

Step S500b, forming a protective layer covering the fins.

Step S500c, forming a mask layer covering the protective layer, and the mask layer has an opening above a predetermined fin.

Optionally, after step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:

Step S500d, removing the mask layer by using a stripping process.

Step S500e, using a wet etching process to remove the protection layer.

Step S500f, using a wet etching process to remove the stop layer.

As shown in FIG. 13 , in step S100 , a semiconductor substrate 10 is provided. Wherein, a plurality of fins 101 are formed on the semiconductor substrate, and a region between adjacent fins 101 is a first pitch region 102 or a second pitch region 103 . Wherein, the size of the first distance region 102 is greater than the size of the second distance region 103 .

Optionally, an isolation layer (not shown in the figure) is further formed above the fin portion 101 .

The semiconductor substrate 10 in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), an insulator Germanium-on-GeOI (GeOI), silicon-on-epitaxial layer structure substrates or compound semiconductor substrates. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium. Preferably, the semiconductor substrate 10 is a silicon single crystal substrate. Several structures such as epitaxial interface layers or strain layers can also be formed on the surface of the semiconductor substrate 10 to improve the electrical performance of the semiconductor device.

As shown in FIG. 14 , in step S200 , a stop layer 20 covering the semiconductor substrate 10 and the fins 101 is formed.

Specifically, the stop layer 20 includes a silicon layer. The stop layer 20 also includes a silicon oxide layer under the silicon layer. The thickness of the stop layer 20 is relatively thin, and the thickness of the two stop layers 20 is smaller than the distance between the fins 101 . Optionally, the thickness of the silicon oxide layer in the stop layer 20 is about 100 angstroms. The silicon oxide layer can be formed by an atomic layer deposition process.

The stop layer 20 is used to protect the fin portion 101 and prevent the fin portion 101 from being damaged in a subsequent etching process. The stop layer 20 includes a silicon layer and a silicon oxide layer, and the silicon layer and the silicon oxide layer have different etching rates under the same etching conditions, thereby better protecting the fins 101 .

As shown in FIG. 15 , in step S300 , a dielectric layer 30 covering the stop layer 20 is formed.

The dielectric layer 30 is used to fill up the gaps of the fins to form a flat surface, which is convenient for forming a mask above the fins.

Specifically, the material of the dielectric layer 30 may be insulating materials such as silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) and silicon oxynitride (SiON).

The formation method of the dielectric layer 30 can be any technique known to those skilled in the art, preferably by chemical vapor deposition (Chemical Vapor Deposition, CVD), such as low temperature chemical vapor deposition (LowTemperature Chemical Vapor Deposition, LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Atomic Layer Deposition (Atomics Layer Deposition, ALD) process, Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical Vapor Deposition) Deposition, PECVD) and so on. Preferably an atomic layer deposition process is used to form dense silicon oxide.

As shown in FIG. 16 , in step S400a, the dielectric layer 30 of the first distance region 102 is etched.

Specifically, the dielectric layer 30 in the first distance region 102 is removed. The dielectric layer 30 can be removed by a wet etching process.

In an optional implementation manner, two different etching methods may be used to etch the dielectric layer 30 in the first spacing region 102 and the stop layer 20 in the first spacing region successively. to expose the semiconductor substrate 10 in the first pitch region.

As shown in FIG. 17 , in step S400 , the semiconductor substrate 10 in the first spacing region 102 is etched. A first shallow trench isolation structure 104 is formed.

Specifically, the first spacing region 102 is etched to form a first shallow trench isolation structure 104 .

In this step, a specific etching method may be used so that the etching rate of the semiconductor substrate is greater than the etching rate of the dielectric layer. Thus, the semiconductor substrate 10 in the first spacing region 102 can be etched using the dielectric layer 30 and the stop layer 20 as a mask, and the first shallow trench isolation structure 104 can be formed in the first spacing region 102 .

As shown in FIG. 18 , in step S400b, the dielectric layer 30 is removed by a wet etching process.

In this step, all the dielectric layers 30 are removed, and the cross section of the removed semiconductor structure is shown in FIG. 18 .

In this step, the stop layer includes a silicon layer, and the etching process for removing the dielectric layer 30 will not etch or less etch the silicon layer, so the stop layer can protect the fins and the semiconductor substrate. The role of the bottom.

As shown in FIG. 19 , in step S500a, the silicon layer in the stop layer 20 is oxidized.

Specifically, the silicon layer in the stop layer 20 may be oxidized by heating and oxidation. A new stop layer 20' of silicon oxide is formed.

As shown in FIG. 20 , in step S500b, a protective layer 40 covering the fin portion 11 is formed.

The protection layer 40 is used to fill the gaps of the fins 11 to form a flat surface above the fins, which is convenient for subsequent formation of a mask pattern on the protection layer 40 .

Specifically, the material of the protection layer 40 may be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

In an optional implementation manner, the material of the protective layer 40 is silicon oxide.

Specifically, the protective layer 40 can be formed using any technique known to those skilled in the art, preferably chemical vapor deposition, such as low-temperature chemical vapor deposition, low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma-enhanced chemical vapor deposition, etc.

In step S500c, a mask layer 50 covering the protection layer 40 is formed, and the mask layer 50 has openings above the predetermined fins 101 .

Specifically, the mask layer 50 is formed by coating a photoresist on the protection layer 40 and curing the photoresist by photolithography to form the mask layer 50 with a predetermined pattern.

As shown in FIG. 21 , in step S500, at least one of the fins 101 between adjacent first shallow trench isolation structures 104 and the semiconductor substrate 10 below at least one of the fins 101 are etched, A second shallow trench isolation structure 105 is formed.

Specifically, an etching method capable of substantially the same etching rate for the dielectric layer, the stop layer, and the fin portion may be selected. For example, plasma etching. Specifically, a predetermined fin portion 101 and the semiconductor substrate 10 below the fin portion 101 may be etched by using a plasma etching process of CF ₄ /H ₂ or CHF ₃ as an etching gas.

In this embodiment, the etching of the fin portion 101 and the semiconductor substrate below the fin portion 101 is completed in one step, which can avoid various defects in the comparative example.

It should be understood that, in the embodiment of the present invention, one fin between adjacent first shallow trench isolation structures is etched, and in other implementation manners, other fins may also be etched according to the needs of different devices. , or two adjacent fins between adjacent first shallow trench isolation structures can also be etched and removed at the same time.

As shown in FIG. 22 , in step S500d, the mask layer 50 is removed by a stripping process.

Specifically, two methods are mainly used to remove the mask layer 50. First, oxygen (O ₂ ) is used for dry etching, and the oxygen reacts with the photoresist to remove the photoresist; The photoresist can be removed by using a wet stripping method, for example, using a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ).

As shown in FIG. 23 , in step S500e, the protective layer 40 is removed by wet etching.

As shown in FIG. 24, in step S500f, the stop layer 20' is removed by wet etching process.

Optionally, when the material of the protection layer 40 and the material of the stop layer 20' are both silicon oxide, the stop layer 20' and the protection layer 40 can be removed in the same wet etching process. Therefore, the process flow can be reduced and the efficiency can be improved.

In another optional implementation manner, the method for forming a semiconductor device according to the embodiment of the present invention includes the following steps:

Step S100, providing a semiconductor substrate. Wherein, a plurality of fins are formed on the semiconductor substrate, and a region between adjacent fins is a first pitch region or a second pitch region.

Step S200, forming a stop layer covering the semiconductor substrate and the fins.

Step S300, forming a dielectric layer covering the stop layer.

Step S400a, etching the dielectric layer in the first distance region.

Step S400, etching the semiconductor substrate in the first pitch region. A first shallow trench isolation structure is formed.

Step S400b, using a wet etching process to remove the dielectric layer.

Step S500b, forming a protective layer covering the fins.

Step S500c, forming a mask layer covering the protective layer, and the mask layer has an opening above a predetermined fin.

Step S500 , etching at least one of the fins between adjacent first STI structures and the semiconductor substrate under at least one of the fins to form a second STI structure.

Step S500d, removing the mask layer by using a stripping process.

Step S500e, using a wet etching process to remove the protection layer.

Step S500a, oxidizing the silicon layer in the stop layer.

In this embodiment, the first shallow trench isolation structure is formed by two different etching processes of step S400a and step S400. It should be understood that, in yet another optional implementation manner, an etching method capable of etching the dielectric layer 30, the stop layer 20, and the semiconductor substrate at similar etching rates may be selected, and the dielectric layer 30, A predetermined area of the stopper layer 20 and the semiconductor substrate 10 is etched. For example, the dielectric layer 30 , the stop layer 20 and the semiconductor substrate 10 in predetermined regions are removed by using a plasma etching method.

In the subsequent process, masks of different shapes are used to etch the structure, and gate structures, source regions, drain regions, and metal interconnection structures are formed to obtain a complete semiconductor device. The stop layer can be removed in a subsequent etching process.

In the embodiment of the present invention, the second shallow trench isolation structure is formed by etching predetermined fins and the semiconductor substrate below the fins. The formation of defects in the semiconductor device can be avoided, and the yield rate of the semiconductor device can be improved.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. A method for forming a semiconductor device, comprising: A semiconductor substrate is provided, and a plurality of fins are formed on the semiconductor substrate, and the area between adjacent fins is a first pitch area or a second pitch area; forming a stop layer overlying the semiconductor substrate and the fin, the stop layer comprising a silicon layer; forming a dielectric layer covering the stop layer; Etching the semiconductor substrate in the first pitch region to form a first shallow trench isolation structure; Oxidizing the silicon layer in the stop layer to form a new stop layer made of silicon oxide; Etching at least one of the fins between adjacent first shallow trench isolation structures and the semiconductor substrate under at least one of the fins to form a second shallow trench isolation structure. 2. The forming method according to claim 1, wherein the material of the dielectric layer is silicon oxide. 3. The forming method according to claim 2, wherein the stop layer further comprises a silicon oxide layer under the silicon layer. 4 . The forming method according to claim 1 , wherein a size of the first spacing region is larger than a size of the second spacing region. 5. The forming method according to claim 1, wherein before the etching of the semiconductor substrate in the first pitch region, the method further comprises: Etching the dielectric layer in the first distance region. 6. The forming method according to claim 1, characterized in that, after the etching of the semiconductor substrate in the first pitch region, the method further comprises: The dielectric layer is removed by using a wet etching process. 7. The forming method according to claim 1, characterized in that, after the oxidation of the stop layer, the method further comprises: The stop layer is removed by a wet etching process. 8 . The forming method according to claim 1 , wherein before etching the predetermined fin and the semiconductor substrate below the fin, the method further comprises: forming a protective layer covering the fin; A mask layer is formed covering the protection layer, the mask layer having openings above predetermined fins. 9. The forming method according to claim 8, characterized in that, after etching the predetermined fin and the semiconductor substrate below the fin, the method further comprises: removing the mask layer by a lift-off process; The protection layer is removed by using a wet etching process. 10. The forming method according to claim 9, characterized in that, after the protective layer is removed by a wet etching process, the method further comprises: The stop layer is removed by a wet etching process.

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