CN111725137A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN111725137A CN111725137A CN201910212132.3A CN201910212132A CN111725137A CN 111725137 A CN111725137 A CN 111725137A CN 201910212132 A CN201910212132 A CN 201910212132A CN 111725137 A CN111725137 A CN 111725137A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Abstract
The embodiment of the invention provides a method for forming a semiconductor device. In the embodiment of the invention, the second shallow trench isolation structure is formed by etching the preset fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
As the manufacturing process of integrated circuits continues to evolve, the feature sizes of existing integrated circuits continue to decrease.
However, defects may occur in the conventional semiconductor device, and the yield of the semiconductor device may be improved.
Disclosure of Invention
In view of this, an embodiment of the present invention provides a method for forming a semiconductor device, including:
providing a semiconductor substrate, wherein a plurality of fin parts are formed on the semiconductor substrate, and the area between every two adjacent fin parts is a first interval area or a second interval area;
forming a stop layer covering the semiconductor substrate and the fin part;
forming a dielectric layer covering the stop layer;
etching the semiconductor substrate in the first interval area to form a first shallow trench isolation structure;
and etching at least one fin part between the adjacent first shallow trench isolation structures and the semiconductor substrate below at least one fin part to form a second shallow trench isolation structure.
Further, the dielectric layer is made of silicon oxide, and the stop layer comprises a silicon layer.
Further, the stop layer further includes a silicon oxide layer located below the silicon layer.
Further, the size of the first pitch region is larger than the size of the second pitch region.
Further, before the etching the semiconductor substrate of the first pitch region, the method further comprises:
and etching the dielectric layer in the first interval area.
Further, after the etching the semiconductor substrate of the first pitch region, the method further includes:
and removing the dielectric layer by adopting a wet etching process.
Further, after the dielectric layer is removed by using the wet etching process, the method further includes:
oxidizing the silicon layer in the stop layer.
Further, after the oxidizing the stop layer, the method further comprises:
and removing the stop layer by adopting a wet etching process.
Further, before the etching the predetermined fin portion and the semiconductor substrate below the fin portion, the method further includes:
forming a protective layer covering the fin part;
and forming a mask layer covering the protective layer, wherein the mask layer is provided with an opening above the preset fin part.
Further, after the etching the predetermined fin portion and the semiconductor substrate below the fin portion, the method further includes:
removing the mask layer by adopting a stripping process;
and removing the protective layer by adopting a wet etching process.
Further, after the protective layer is removed by using a wet etching process, the method further includes:
and removing the stop layer by adopting a wet etching process.
In the embodiment of the invention, the second shallow trench isolation structure is formed by etching the preset fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of one memory cell of an SRAM device;
FIG. 2 is a top view of the structure of one memory cell of an SRAM device;
FIGS. 3 and 4 are cross-sectional schematic views of a fin of an SRAM;
FIGS. 5 to 8 are schematic structural views of respective steps of a method of forming a semiconductor device of a comparative example;
fig. 9 is a schematic view of a structure having defects formed by the method of forming a semiconductor device of the comparative example;
fig. 10 to 11 are schematic structural views of respective steps of a method of forming a semiconductor device of another comparative example;
fig. 12 is a flowchart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 13 to 24 are schematic structural views of respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, "multi-layer" means two or more layers unless otherwise specified.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Spatial relationship terms such as "below …", "below", "lower", "above …", "above", and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.
Static Random-Access Memory (SRAM) is one type of Random Access Memory. Taking SRAM as an example, a circuit diagram of one memory cell of SRAM is shown in fig. 1, and one memory cell of SRAM includes six field effect transistors of PU1, PU2, PD1, PD2, PG1, and PG 2. FIG. 2 is a top view of the structure of one memory cell of the SRAM. As shown in fig. 2, the SRAM includes a fin 11 and a gate structure 16. In the process of forming the structure shown in fig. 2, a plurality of fin portions with the same interval are formed first, and since different types of semiconductor structures need to be formed, the fin portions in a partial region need to be etched. Fig. 3 and 4 are cross-sectional views of fins of an SRAM. During the formation of the structure shown in fig. 3, the fin portion of region 1 is etched. In the process of forming the structure shown in fig. 4, the fin portion of the region 1 and the fin portion of the region 2 need to be etched, and the semiconductor substrate of the region 2 needs to be etched, so as to form a shallow trench isolation structure. In the subsequent process, a patterned gate structure is formed on the fin portion, so that different transistors such as PU1, PU2, PD1, PD2, PG1, and PG2 are formed on the semiconductor substrate to form a memory cell of the SRAM having the circuit structure shown in fig. 1. However, due to the ever decreasing feature sizes of semiconductor devices, existing equipment is unable to produce a fin pitch that meets the requirements in smaller node fabrication processes. Meanwhile, the size of the shallow trench isolation region cannot reach the target size. The performance of the semiconductor device cannot be ensured by the existing production process.
In one comparative example, a method of forming a semiconductor device includes the steps of:
and step S1, etching the preset fin part.
In step S2, an oxide layer is formed to cover the fin portion.
Step S3, etching the predetermined region to form a Shallow Trench Isolation (STI).
In step S1, a predetermined fin 11 is etched.
Specifically, as shown in fig. 5, a dielectric layer 12 and a photoresist layer 13 are respectively formed above the fin portion 11. The photoresist layer 13 has an opening above the predetermined fin portion 11. As shown in fig. 6, the opening region of the photoresist layer is etched to remove the predetermined fin portion.
And after removing the preset fin part, removing the photoresist layer and the dielectric layer.
In step S2, an oxide layer 14 is formed to cover the fin 11.
Specifically, as shown in fig. 7, an oxide layer 14 is formed to cover the fin 11.
In step S3, a predetermined region is etched to form a shallow trench isolation structure 15.
Specifically, as shown in fig. 8, a predetermined region is etched to form a shallow trench isolation structure 15.
However, this method may form a defect as shown in the region 3 in fig. 9, and the profile of the shallow trench isolation structure is irregular. In addition, after etching the predetermined fin portion 11, silicon remains and the etching depth is insufficient. These defects can affect the yield of the semiconductor device.
The defect is generated mainly because the fin portion is etched and the shallow trench isolation structure below the fin portion is formed in two steps, so that the defect is easily formed.
In another comparative example, a method of forming a semiconductor device includes the steps of:
and step S4, forming a photoresist layer.
Step S5, etching the predetermined region to form a shallow trench isolation structure.
As shown in fig. 10, in step S4, a photoresist layer 21 is formed.
Specifically, a dielectric layer 14 covers the fin portion 11 of the semiconductor substrate, and a mask layer is formed on the dielectric layer and has an opening in a predetermined region.
As shown in fig. 11, in step S5, a predetermined region is etched to form a shallow trench isolation structure 15.
It should be understood that, in the present embodiment, 4 fins are spaced between two sti structures, and in other implementations, 3 fins may be spaced between two sti structures, which is not limited herein.
In this comparative example, due to the reduction in fin pitch, the adjacent predetermined regions are too close to each other, resulting in failure to achieve the lithography condition without a Process Window (PW). The two mask plates are overlapped to realize etching, so that etching deviation occurs to influence the performance of the semiconductor device.
In view of this, embodiments of the present invention provide a method for forming a semiconductor device, which can solve the defects occurring in the process of forming the semiconductor device in the comparative example and improve the yield of the semiconductor device. The embodiments of the present invention are described with reference to forming an SRAM as an example, and it should be understood that the methods described in the embodiments of the present invention can also be used to form other semiconductor devices.
Fig. 12 is a flowchart of a method of forming a semiconductor device of an embodiment of the present invention. As shown in fig. 12, the method for forming a semiconductor device according to the embodiment of the present invention includes the steps of:
step S100, providing a semiconductor substrate. The semiconductor substrate is provided with a plurality of fin parts, and the area between the adjacent fin parts is a first interval area or a second interval area.
And step S200, forming a stop layer covering the semiconductor substrate and the fin portion.
And step S300, forming a dielectric layer covering the stop layer.
And S400, etching the semiconductor substrate in the first interval area. Forming a first shallow trench isolation structure.
Step S500, at least one fin portion between adjacent first shallow trench isolation structures and the semiconductor substrate below the fin portion are etched to form a second shallow trench isolation structure.
Optionally, before step S400, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
step S400a, etching the dielectric layer in the first interval area.
Optionally, after step S400, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and step S400b, removing the dielectric layer by adopting a wet etching process.
Optionally, before step S500 or after step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and step S500a, oxidizing the silicon layer in the stop layer.
Optionally, before step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
step S500b, forming a protection layer covering the fin portion.
Step S500c, forming a mask layer covering the protection layer, where an opening is formed above a predetermined fin portion of the mask layer.
Optionally, after step S500, the method for forming a semiconductor device according to the embodiment of the present invention further includes:
and step S500d, removing the mask layer by adopting a stripping process.
And step S500e, removing the protective layer by adopting a wet etching process.
And step S500f, removing the stop layer by adopting a wet etching process.
As shown in fig. 13, in step S100, a semiconductor substrate 10 is provided. A plurality of fin portions 101 are formed on the semiconductor substrate, and a region between adjacent fin portions 101 is a first pitch region 102 or a second pitch region 103. Wherein the size of the first pitch region 102 is larger than the size of the second pitch region 103.
Optionally, an isolation layer (not shown) is further formed above the fin 101.
The semiconductor substrate 10 in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. Preferably, the semiconductor substrate 10 is a silicon single crystal substrate. Structures such as a plurality of epitaxial interface layers or strain layers can be formed on the surface of the semiconductor substrate 10 to improve the electrical performance of the semiconductor device.
As shown in fig. 14, in step S200, a stop layer 20 is formed to cover the semiconductor substrate 10 and the fin 101.
In particular, the stop layer 20 comprises a silicon layer. The stop layer 20 also comprises a silicon oxide layer located below the silicon layer. The thickness of the stop layer 20 is smaller than the distance between the fins 101. Optionally, the thickness of the silicon oxide layer in the stop layer 20 is about 100 angstroms. The silicon oxide layer may be formed using an atomic layer deposition process.
The stop layer 20 is used to protect the fin 101 and prevent the fin 101 from being damaged in a subsequent etching process. The stop layer 20 includes a silicon layer and a silicon oxide layer, and the silicon layer and the silicon oxide layer have different etching rates under the same etching condition, so that the fin portion 101 can be better protected.
As shown in fig. 15, in step S300, a dielectric layer 30 is formed overlying the stop layer 20.
The dielectric layer 30 is used to fill and level the gap of the fin portion to form a flat surface, which is convenient for forming a mask over the fin portion.
Specifically, the material of the dielectric layer 30 may be silicon oxide (SiO)2) Silicon nitride (Si)3N4) And an insulating material such as silicon oxynitride (SiON).
The dielectric Layer 30 may be formed by any technique known to those skilled in the art, preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), etc. Preferably, an atomic layer deposition process is used to form the dense silicon oxide.
As shown in fig. 16, in step S400a, the dielectric layer 30 of the first pitch region 102 is etched.
Specifically, the dielectric layer 30 of the first pitch region 102 is removed. A wet etch process may be used to remove the dielectric layer 30.
In an alternative implementation, two different etching methods may be used to sequentially etch the dielectric layer 30 in the first pitch region 102 and the stop layer 20 in the first pitch region. To expose the semiconductor substrate 10 in the first pitch region.
As shown in fig. 17, in step S400, the semiconductor substrate 10 of the first pitch region 102 is etched. A first shallow trench isolation structure 104 is formed.
Specifically, the first pitch region 102 is etched to form a first shallow trench isolation structure 104.
In this step, a specific etching method may be adopted such that the etching rate for the semiconductor substrate is greater than the etching rate for the dielectric layer. Thus, the semiconductor substrate 10 in the first pitch region 102 may be etched using the dielectric layer 30 and the stop layer 20 as a mask, so as to form the first shallow trench isolation structure 104 in the first pitch region 102.
As shown in fig. 18, in step S400b, the dielectric layer 30 is removed by a wet etching process.
In this step, all of dielectric layer 30 is removed, and the cross-section of the semiconductor structure after removal is shown in FIG. 18.
In this step, the stop layer includes a silicon layer, and the etching process for removing the dielectric layer 30 does not etch or less etches the silicon layer, so that the stop layer can protect the fin portion and the semiconductor substrate.
As shown in fig. 19, in step S500a, the silicon layer in the stop layer 20 is oxidized.
Specifically, the silicon layer in the stop layer 20 may be oxidized by thermal oxidation. A new stop layer 20' of silicon oxide is formed.
As shown in fig. 20, in step S500b, a protection layer 40 is formed to cover the fin 11.
The protection layer 40 is used to fill the gap of the fin 11 to form a flat surface above the fin, which facilitates the subsequent formation of a mask pattern above the protection layer 40.
Specifically, the material of the protective layer 40 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
In an alternative implementation, the material of the protective layer 40 is silicon oxide.
Specifically, the protective layer 40 may be formed by any technique known to those skilled in the art, preferably by chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, and the like.
In step S500c, a mask layer 50 is formed to cover the protection layer 40, where the mask layer 50 has an opening above the predetermined fin 101.
Specifically, the mask layer 50 is formed by coating a photoresist on the protective layer 40, and curing the photoresist by a photolithography process to form the mask layer 50 having a predetermined pattern.
As shown in fig. 21, in step S500, at least one of the fins 101 between adjacent first shallow trench isolation structures 104 and the semiconductor substrate 10 under at least one of the fins 101 are etched to form a second shallow trench isolation structure 105.
Specifically, an etching method capable of substantially equalizing the etching rates of the dielectric layer, the stop layer, and the fin portion may be selected. Such as plasma etching. Specifically, CF can be employed4/H2Or CHF3As etching gasThe predetermined fin portion 101 and the semiconductor substrate 10 below the fin portion 101 are etched.
In the present embodiment, the etching of the fin 101 and the semiconductor substrate under the fin 101 is completed in one step, so that various defects occurring in the comparative example can be avoided.
It should be understood that, in the embodiment of the present invention, one fin portion between adjacent first shallow trench isolation structures is etched, in other embodiments, other portions of fin portions may also be etched according to the requirements of different devices, or two adjacent fin portions between adjacent first shallow trench isolation structures may also be simultaneously etched and removed.
As shown in fig. 22, in step S500d, the mask layer 50 is removed by a stripping process.
Specifically, two methods are mainly used to remove the mask layer 50, first, oxygen (O) is used2) Dry etching is carried out, oxygen and the photoresist generate chemical reaction, and the photoresist can be removed; second, wet stripping, e.g., using sulfuric acid (H), can also be used2SO4) And hydrogen peroxide (H)2O2) The mixed solution of (2) can remove the photoresist.
As shown in fig. 23, in step S500e, the protective layer 40 is removed by a wet etching process.
As shown in fig. 24, in step S500f, the stop layer 20' is removed by a wet etching process.
Alternatively, when the material of the protection layer 40 and the material of the stop layer 20 'are both silicon oxide, the stop layer 20' and the protection layer 40 may be removed in the same wet etching process. Therefore, the process flow can be reduced, and the efficiency can be improved.
In another alternative implementation manner, a method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:
step S100, providing a semiconductor substrate. The semiconductor substrate is provided with a plurality of fin parts, and the area between the adjacent fin parts is a first interval area or a second interval area.
And step S200, forming a stop layer covering the semiconductor substrate and the fin portion.
And step S300, forming a dielectric layer covering the stop layer.
Step S400a, etching the dielectric layer in the first interval area.
And S400, etching the semiconductor substrate in the first interval area. Forming a first shallow trench isolation structure.
And step S400b, removing the dielectric layer by adopting a wet etching process.
Step S500b, forming a protection layer covering the fin portion.
Step S500c, forming a mask layer covering the protection layer, where an opening is formed above a predetermined fin portion of the mask layer.
Step S500, at least one fin portion between adjacent first shallow trench isolation structures and the semiconductor substrate below the fin portion are etched to form a second shallow trench isolation structure.
And step S500d, removing the mask layer by adopting a stripping process.
And step S500e, removing the protective layer by adopting a wet etching process.
And step S500a, oxidizing the silicon layer in the stop layer.
In the present embodiment, the first shallow trench isolation structure is formed by two different etching processes of step S400a and step S400. It should be understood that in yet another alternative implementation, an etching method capable of etching dielectric layer 30, stop layer 20 and semiconductor substrate at similar rates may be selected to etch the dielectric layer 30, stop layer 20 and predetermined regions of semiconductor substrate 10 at steps S400a and S400. For example, the dielectric layer 30, the stop layer 20 and the semiconductor substrate 10 are removed in a predetermined region by plasma etching.
In the subsequent process, masks in different shapes are adopted to etch the structure, and a grid structure, a source region, a drain region, a metal interconnection structure and the like are formed, so that a complete semiconductor device is obtained. The stop layer may be removed during a subsequent etching process.
In the embodiment of the invention, the second shallow trench isolation structure is formed by etching the preset fin part and the semiconductor substrate below the fin part. The defect of the semiconductor device can be avoided, and the yield of the semiconductor device is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein a plurality of fin parts are formed on the semiconductor substrate, and the area between every two adjacent fin parts is a first interval area or a second interval area;
forming a stop layer covering the semiconductor substrate and the fin part;
forming a dielectric layer covering the stop layer;
etching the semiconductor substrate in the first interval area to form a first shallow trench isolation structure;
and etching at least one fin part between the adjacent first shallow trench isolation structures and the semiconductor substrate below at least one fin part to form a second shallow trench isolation structure.
2. The method of claim 1, wherein the dielectric layer is formed of silicon oxide and the stop layer comprises a silicon layer.
3. The method of claim 2, wherein the stop layer further comprises a silicon oxide layer underlying the silicon layer.
4. The method of forming as claimed in claim 1, wherein a size of the first pitch region is greater than a size of the second pitch region.
5. The method of forming of claim 1, wherein prior to said etching said semiconductor substrate of said first pitch region, said method further comprises:
and etching the dielectric layer in the first interval area.
6. The method of forming of claim 1, wherein after said etching the semiconductor substrate of the first pitch region, the method further comprises:
and removing the dielectric layer by adopting a wet etching process.
7. The method of claim 6, wherein after the removing the dielectric layer by a wet etching process, the method further comprises:
oxidizing the silicon layer in the stop layer.
8. The method of forming as claimed in claim 7, wherein after said oxidizing said stop layer, said method further comprises:
and removing the stop layer by adopting a wet etching process.
9. The method of forming in claim 1, wherein prior to said etching the predetermined fin and the semiconductor substrate below the fin, the method further comprises:
forming a protective layer covering the fin part;
and forming a mask layer covering the protective layer, wherein the mask layer is provided with an opening above the preset fin part.
10. The method of claim 8, wherein after said etching the predetermined fin and the semiconductor substrate below the fin, the method further comprises:
removing the mask layer by adopting a stripping process;
and removing the protective layer by adopting a wet etching process.
11. The method of forming as claimed in claim 10, wherein after removing the protective layer using a wet etch process, the method further comprises:
and removing the stop layer by adopting a wet etching process.
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