CN104752185B - The forming method of metal gates - Google Patents
The forming method of metal gates Download PDFInfo
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- CN104752185B CN104752185B CN201310754250.XA CN201310754250A CN104752185B CN 104752185 B CN104752185 B CN 104752185B CN 201310754250 A CN201310754250 A CN 201310754250A CN 104752185 B CN104752185 B CN 104752185B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 51
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- 239000010410 layer Substances 0.000 claims abstract description 311
- 239000011229 interlayer Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 51
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- 229920000642 polymer Polymers 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
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- 238000000227 grinding Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 4
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052794 bromium Inorganic materials 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000004215 Carbon black (E152) Substances 0.000 claims description 3
- 229930195733 hydrocarbon Natural products 0.000 claims description 3
- 150000002430 hydrocarbons Chemical class 0.000 claims description 3
- 208000027418 Wounds and injury Diseases 0.000 abstract description 6
- 208000014674 injury Diseases 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- 239000007789 gas Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
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- 239000010703 silicon Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical group F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
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- 238000007254 oxidation reaction Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 229910052593 corundum Inorganic materials 0.000 description 1
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- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of forming method of metal gates, including：Semiconductor substrate is provided, dummy grid is formed in substrate surface, forms interlayer dielectric layer on substrate, interlayer dielectric layer top is equal at the top of dummy grid；Utilize the first sacrificial layer being epitaxially-formed at the top of at least covering dummy grid；The second sacrificial layer is formed on interlayer dielectric layer, the second sacrificial layer top is equal at the top of the first sacrificial layer；The first sacrificial layer is removed, opening is formed in the second sacrificial layer, open bottom is exposed at the top of dummy grid；After removing the first sacrificial layer, dummy grid is removed, gate recess is formed in interlayer dielectric layer；The second sacrificial layer is removed, metal layer is filled in gate recess and forms metal gates.Method using the present invention can be good at protect interlayer dielectric layer removal dummy grid during it is injury-free; so that the depth of gate recess will not reduce; and then the height for the metal gates being subsequently formed is made not reduce, improve the performance for the device being subsequently formed.
Description
Technical field
The present invention relates to the forming methods of semiconductor applications more particularly to metal gates.
Background technology
With the continuous development of ic manufacturing technology, the characteristic size of MOS transistor is also less and less, brilliant in MOS
In the case of body pipe characteristic size constantly reduces, in order to reduce the parasitic capacitance of MOS transistor grid, device speed, metal are improved
Grid is introduced in MOS transistor.
Fig. 1 to Fig. 4 is the cross-sectional view of the forming method of metal gates in the prior art.
With reference to figure 1, Semiconductor substrate 100 is provided, dummy grid 101, the material of the dummy grid are formed on the substrate 100
Expect for polysilicon.Then, the silicon oxide layer 102 of covering substrate 100 and dummy grid 101, top and the puppet of silicon oxide layer 102 are formed
The top of grid 101 is equal.
With reference to figure 2, dummy grid 101 is removed using the method for dry etching（With reference to figure 1）, in the inside of silicon oxide layer 102
Form gate recess 103.
With reference to figure 3, layer of aluminum 104 ' is formed, the layer of aluminum 104 ' fills up gate recess 103 and covers silica
The top of layer 102.
With reference to figure 4, using the method for chemical mechanical grinding so that layer of aluminum 104 '（With reference to figure 3）Top and oxidation
The top of silicon layer 102 is equal, forms aluminium gate 104.
The metal gates performance formed using the method for the prior art is bad, and when serious, metal gates can not work normally.
The content of the invention
The present invention solves the problems, such as it is that the metal gates performance formed using the method for the prior art is bad, when serious, gold
Belonging to grid can not work normally.
To solve the above problems, the present invention provides a kind of forming method of metal gates, including：
Semiconductor substrate is provided, dummy grid is formed in the substrate surface, forms interlayer dielectric layer, the layer on substrate
Between it is equal with dummy grid top at the top of dielectric layer；
Using being epitaxially-formed the first sacrificial layer at least covered at the top of the dummy grid；
The second sacrificial layer, the second sacrificial layer top and phase at the top of first sacrificial layer are formed on interlayer dielectric layer
It is flat；
First sacrificial layer is removed, opening is formed in second sacrificial layer, the open bottom exposes the puppet
Top portions of gates；
After removing first sacrificial layer, the dummy grid is removed, gate recess is formed in the interlayer dielectric layer；
The second sacrificial layer is removed, metal layer is filled in the gate recess and forms metal gates.
Optionally, the method for the second sacrificial layer is formed on interlayer dielectric layer to be included：
The second sacrificial material layer is formed, covers the interlayer dielectric layer and the first sacrificial layer；
Removal is higher than the second sacrificial material layer at the top of the first sacrificial layer.
Optionally, the material of second sacrificial layer be amorphous carbon, first polymer or bottom anti-reflection layer, described first
Polymer includes carbon or one kind or their any combination in fluorine, bromine, chlorine element.
Optionally, the method for second sacrificial material layer is formed as deposition or is smeared；
Removal is chemical mechanical grinding or etching higher than the method for the second sacrificial material layer at the top of the first sacrificial layer.
Optionally, the method for the second sacrificial layer is removed as ashing.
Optionally, first sacrificial layer also covering part interlayer dielectric layer after removing the first sacrificial layer, removes the puppet
Before the step of grid, step is further included：It is formed in the opening sidewalls and sacrifices side wall；
After the step of removing the dummy grid, remove the second sacrificial layer the step of before, further include step：Described in removal
Sacrifice side wall.
Optionally, the forming method for sacrificing side wall includes：
It is formed and sacrifices spacer material layer, fill the opening and cover second sacrificial layer；
The sacrifice spacer material layer is etched, is formed in the opening sidewalls and sacrifices side wall.
Optionally, the material for sacrificing side wall is second polymer, and the second polymer is prepared by hydrocarbon gas.
Optionally, the method for sacrificing side wall is removed as ashing.
Optionally, the material identical of the material of first sacrificial layer and the dummy grid.
Optionally, the material of the dummy grid is polysilicon, and the material of first sacrificial layer is polysilicon.
Optionally, the method for removing the first sacrificial layer is wet etching or dry etching.
Optionally, after the step of substrate surface forms dummy grid, the step of interlayer dielectric layer is formed on substrate
Before rapid, further include：
Side wall is formed around the dummy gate.
Optionally, the material of the interlayer dielectric layer is silica.
Optionally, gate dielectric layer is further included between the substrate and the dummy grid, the gate recess bottom is exposed
The gate dielectric layer, the gate dielectric layer are high-k gate dielectric layer.
Optionally, gate dielectric layer is further included between the substrate and the dummy grid, the gate recess bottom is exposed
The gate dielectric layer, the gate dielectric layer is silicon oxide layer, and after removing the second sacrificial layer, gold is filled in the gate recess
Before the step of belonging to layer, further include：The silicon oxide layer is removed, forming high k grid in the bottom and side wall of the gate recess is situated between
Matter layer.
Compared with prior art, technical scheme has the following advantages：
The first sacrificial layer at least covered at the top of dummy grid is formed using the method for epitaxial growth, the first sacrificial layer can incite somebody to action
Dummy grid all covers, moreover, the position of the first sacrificial layer determines the position of the opening in the second sacrificial layer, so that the
Two sacrificial layers will accurately can expose at the top of dummy grid.At this point, the second sacrificial layer by the interlayer dielectric layer around dummy grid into
Row covering, so as to which during dummy grid is removed, the second sacrificial layer can protect interlayer dielectric layer, prevent inter-level dielectric
Layer is also etched into, and prevents the height of interlayer dielectric layer from reducing.This process is autoregistration process, and dummy grid is removed in etching
Before, the second sacrificial layer of formation can accurately expose dummy grid.Only expose dummy grid top with being formed on interlayer dielectric layer
The photoetching gluing method in portion is compared, and can avoid the problem that alignment precision is poor.Therefore can be very good to protect using self aligned method
It is injury-free during dummy grid is removed to protect interlayer dielectric layer, so that the depth of gate recess will not reduce, and then makes
The height for the metal gates being subsequently formed will not reduce.It ensure that the height of the metal gates subsequently formed in the gate recess
Degree improves the performance of metal gates.
Description of the drawings
Fig. 1 to Fig. 4 is the cross-sectional view of the forming method of metal gates in the prior art；
Fig. 5 to Figure 12 is the cross-sectional view of the forming method of the metal gates in the specific embodiment of the invention.
Specific embodiment
The metal gates performance formed using the method for the prior art is bad, and when serious, metal gates can not work normally
The reason for it is as follows：
With reference to figure 2, dummy grid 101 is removed using the method for etching（With reference to figure 1）When, even if silicon oxide layer 102 and pseudo- grid
Etching selection ratio between pole 101 differs greatly, and will also result in the loss of silicon oxide layer 102 so that the thickness of silicon oxide layer 102
Reduced, the depth of gate recess 103 is made also to be reduced accordingly.
With reference to figure 4, using the method for chemical mechanical grinding so that layer of aluminum 104 '（With reference to figure 3）Top and oxidation
It when the top of silicon layer 102 is equal, is limited by chemical grinding appointed condition, in order to ensure not in 102 remained on surface aluminium of silicon oxide layer
Material can grind some silicon oxide layers 102 more, so that the height of silicon oxide layer 102 continues to reduce, make follow-up shape accordingly
Into the height of aluminium gate 104 also further reduce.
If the height of aluminium gate 104 is too low, grid resistance value is influenced, and then influences the ability of grid control channel current,
Therefore, the performance of aluminium gate 104 is bad, when serious, can not work normally.
In order to avoid above-mentioned technical problem, inventor did following trial to solve the technical problem, the first attempts tool
Body is：With reference to figure 1, when forming silicon oxide layer 102, using the method for increasing by 102 thickness of silicon oxide layer, still, with reference to figure 2,
After gate recess 103 is formed, the depth of gate recess 103 can increase, so as to the filling layer of aluminum in gate recess 103
In 104 ' the step of, since the depth-to-width ratio of gate recess 103 is too big, so as to which the aluminum material being filled in gate recess 103 can be made
Layer 104 '（With reference to figure 3）Inside has gap, so as to influence the performance for the aluminium gate being subsequently formed.Therefore, silica is being formed
During layer 102, the method that increase by 102 thickness of silicon oxide layer may be employed does not apply to.
Second of trial be specially：With reference to figure 1 and Fig. 2, during etching removes dummy grid 101, in order to reduce oxygen
The loss of SiClx layer 102 can form patterned photoresist layer above silicon oxide layer 102（It is not shown）, the pattern
The photoresist covering silicon oxide layer 102 of change, while expose dummy grid 101.Then it is mask to pseudo- grid using patterned photoresist
Pole 101 performs etching, and gate recess 103 is formed in silicon oxide layer 102.This method also is difficult to reduce silicon oxide layer 102
Loss, the reason is as follows that：The CD sizes of dummy grid 101 are too small, along with the limitation of the alignment precision of photoetching process, it is difficult to by pattern
The photoresist of change just exposes dummy grid 101, at the same also can be more or less exposing silicon oxide layer 102, therefore, not by pattern
The silicon oxide layer 102 of the photoresist covering of change can also be etched, and then, form layer of aluminum 104 '（With reference to figure 3）During,
Layer of aluminum 104 ' can be also filled at the silicon oxide layer 102 being etched, it then, will using CMP process with reference to figure 4
During being removed higher than the layer of aluminum 104 ' on silicon oxide layer 102, filled to remove at the silicon oxide layer 102 being etched
Layer of aluminum 104 ', the whole height of silicon oxide layer 102 can be made significantly to decline, so that under the depth of gate recess 103
Drop, and then make to form the reduction of metal gates height.Therefore, the method for silicon oxide layer 102 is covered not using patterned photoresist
It is applicable in.
Therefore, in order to solve present invention the technical issues of, the present invention provides a kind of forming methods of metal gates, use
The metal gates that the method for the present invention is formed can improve the performance for the metal gates being subsequently formed.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
First, with reference to figure 5, step S11 is performed, Semiconductor substrate 200 is provided, pseudo- grid are formed on 200 surface of substrate
Pole 201, forms interlayer dielectric layer 204 on substrate, and 204 top of interlayer dielectric layer is equal with 201 top of dummy grid.
200 material of Semiconductor substrate can be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, carborundum lining
Bottom or its laminated construction or silicon on insulated substrate or diamond substrate or well known to a person skilled in the art other semiconductors
Material substrate.In the present embodiment, the Semiconductor substrate 200 is silicon substrate, wherein isolation structure is also formed with, the isolation junction
Structure can be fleet plough groove isolation structure or well known to a person skilled in the art other for device isolation or active area isolation every
From structure.
Gate dielectric layer is formed on 200 surface of substrate and covers the dummy grid material layer of the gate dielectric layer, in dummy grid
Patterned photoresist is formed in material layer, using patterned photoresist as template, etches dummy grid material layer and gate dielectric layer,
Form dummy grid 201, the gate dielectric layer between substrate 200 and dummy grid 201（It is not shown）.In the present embodiment, gate medium
Layer is high-k gate dielectric layer.The material of the high-k gate dielectric layer is HfO2、Al2O3、ZrO2, HfSiO, HfSiON, HfTaO and
HfZrO.In other embodiment, gate dielectric layer or silicon oxide layer.
In the present embodiment, side wall 202 is formed with around dummy grid 201.The material of side wall 202 can be silica, nitridation
The multilayer materials such as silicon or oxide-nitride-oxide.In other embodiment, side wall is not formed around dummy grid, is fallen within
Protection scope of the present invention.
Etching stop layer 203 is formed, etching stop layer 203 covers 202 side wall of 200 surface of substrate and side wall.Etching stopping
Layer 203 is act as：When subsequent etching forms source conductive plug through hole or Drain Electrodes Conductive plug through hole, on the one hand so that source electrode
Conductive plunger through hole and Drain Electrodes Conductive plug through hole are all stopped on etching stop layer 203, and etching stop layer 203 can protect quarter
The substrate 200 lost below stop-layer 203 is injury-free, on the other hand, source conductive plug through hole and Drain Electrodes Conductive plug through hole
It all stops on etching stop layer 203, over etching will not be all formed to etching stop layer 203, it is identical so as to form depth
Source conductive plug through hole or Drain Electrodes Conductive plug through hole.In the present embodiment, the material of etching stop layer 203 is silicon nitride.
The method of etching stop layer is formed as deposition.In other embodiment, etching stop layer is not formed, falls within the protection model of the present invention
It encloses.
In the present embodiment, interlayer layer of dielectric material, covering etching stop layer 203, side wall 202 and dummy grid 201 are formed.So
Inter-level dielectric is formed higher than the interlevel dielectric material layer of dummy grid 201 using the removal of the method for chemical mechanical grinding or etching afterwards
Layer 204.204 top of interlayer dielectric layer is equal with 201 top of dummy grid.Wherein, the method for interlayer layer of dielectric material is formed to change
It learns vapor deposition or high depth ratio fills out ditch technique（HARP,High Aspect Ratio Process）.
Then, with reference to figure 6, step S12 is performed, 201 top of dummy grid is at least covered using being epitaxially-formed
First sacrificial layer 205.
In the present embodiment, the material of the first sacrificial layer 205 is polysilicon.First sacrificial layer 205 not only covers dummy grid 201
Top, also cover the top of side wall 202,203 top of etching stop layer and part interlayer dielectric layer 204.The epitaxial growth is
Reduced pressure epitaxy, specific formation process are as follows：Silicon source gas is silane or dichloro-dihydro silane, and extension pressure is 20~100Torr.
When silicon source gas is silane, epitaxial growth temperature is 600~950 DEG C；When silicon source gas is dichloro-dihydro silane, extension life
Long temperature is 1000~1100 DEG C.In other embodiment, the epitaxial growth or normal pressure extension（Pressure is 760Torr
Left and right）Growth or selective epitaxial growth.
Then, with reference to figure 7, step S13 is performed, forms the second sacrificial layer 206 on interlayer dielectric layer 204, described second
206 top of sacrificial layer is equal with 205 top of the first sacrificial layer.
In the present embodiment, the material of the second sacrificial layer 206 is amorphous carbon.In other embodiment, the material of the second sacrificial layer 206
Material or first polymer or bottom antireflective coating（BARC, Bottom Anti-Reflective Coating）.Institute
Stating first polymer includes carbon or one kind or their any combination in fluorine, bromine, chlorine element.Form the second sacrificial layer
206 method is specially：Second sacrificial material layer is formed using deposition or the method smeared, second sacrificial material layer is covered
204 and first sacrificial layer 205 of lid interlayer dielectric layer.Then, removed using etching or the method for chemical mechanical grinding or etching
Higher than second sacrificial material layer at 205 top of the first sacrificial layer, the second sacrificial layer 206 is formed.The top of second sacrificial layer 206 and the
One sacrificial layer, 205 top is equal.
Wherein, when the second sacrificial layer 206 is first polymer, the concrete technology for forming the second sacrificial material layer is：For
The flow of deposition gases be 100sccm~1000sccm, deposition pressure be 3mTorr~30mTorr, exciting power for 300W~
1500W, bias power are 2MHz~60MHz, and processing time is 8s~60s.The deposition gases include carbon and fluorine, bromine,
One kind or their any combination in chlorine element.
Then, with reference to figure 8, step S14 is performed, removes first sacrificial layer 205（With reference to figure 7）, it is sacrificial described second
Opening 207 is formed in domestic animal layer 206,201 top of dummy grid is exposed in 207 bottoms of the opening.
In the present embodiment, the method for the first sacrificial layer 205 of removal is dry etching or wet etching.Wherein dry etching
Concrete technology is as follows：Etching gas include HBr and Cl2One or both of, with O2As diluent gas, wherein etching gas
Ratio with diluent gas is 100:1~1:100.Wet etching agent is 10~50% tetramethylammonium hydroxide for concentration（TMAH）
Solution, the temperature of wet etching is 10~100 DEG C.
In the present embodiment, since the first sacrificial layer 205 not only covers the top of dummy grid 201, also cover side wall 202 and push up
Portion, the top of etching stop layer 203 and part interlayer dielectric layer 204, therefore, after removing the first sacrificial layer 205, be open 207 bottom
Portion also exposes 202 top of side wall, 203 top of etching stop layer and part interlayer dielectric layer 204.
It should be noted that during the first sacrificial layer 205 of etching, although 201 top of dummy grid, side to 207 bottom of opening
The interlayer dielectric layer 204 at 202 top of wall, 203 top of etching stop layer and exposing can all have smaller damage, with prior art phase
Than the smaller damage can be ignored.
Then, with reference to figure 9, formed in the side wall of the opening 207 and sacrifice side wall 208.
In the present embodiment, the material of side wall 208 is sacrificed for second polymer, is prepared by hydrocarbon gas.It is formed and sacrifices side wall
208 method is specific as follows：The deposited sacrificial spacer material layer on the bottom of opening 207, side wall and the second sacrificial layer 206, so
The method carved is used back to be formed in the side wall of opening 207 afterwards and sacrifices side wall 208.Adjacent two expose between sacrificing side wall 208
The top of dummy grid 201.Chemical formula is used as CxHyFxDeposition gases deposit to be formed sacrifice spacer material layer, concrete technology is such as
Under：Chemical formula is CH3F,CH2F2, C3HF3Deposition gases in one kind, two or three, the total flows 100 of deposition gases~
2000sccm.In the present embodiment, the 100~2000W of exciting power, 0~50W of bias power for carving and being formed and sacrificing side wall 208 are returned.
Then, with reference to figure 10, step S15 is performed, removes the dummy grid 201（With reference to figure 9）, in the interlayer dielectric layer
Gate recess 209 is formed in 204.
It is formed after sacrificing side wall 208, to sacrifice side wall 208 for mask, removes dummy grid 201.Remove the side of dummy grid 201
Method is dry etching either wet etching.Belong to those skilled in the art's well-known processes, details are not described herein.Remove dummy grid
During 201, due to sacrificing 208 and second sacrificial layer 206 of side wall to interlayer dielectric layer 204, side wall 202 and etching stop layer
203 protection makes interlayer dielectric layer 204, side wall 202 and etching stop layer 203 not damage, so as to cause inter-level dielectric
Layer 204, side wall 202, the height of etching stop layer 203 decline, into the depth minus without causing the gate recess 209 to be formed
It is small, it ensure that the height of the metal gates subsequently formed in gate recess 209.
It should be noted that：Formed sacrifice side wall 208 with etching removal dummy grid 201 technique be same chamber into
Capable.Why carried out in same chamber, reason is as follows：（1）If being formed in the first reaction chamber and sacrificing side wall 208,
In the technique that the second reaction chamber performs etching removal dummy grid 201, then during substrate is removed the first reaction chamber,
Substrate surface can aoxidize in air, and the progress for being unfavorable for subsequent technique or the performance for being subsequently formed device are bad.（2）
Processing step and process equipment can be saved.
Need to illustrate again is：During etching removal dummy grid 201, it can be covered in the lateral wall for sacrificing side wall 208
Lid etch by-products, which is also second polymer, during removing dummy grid 201 in etching, is sacrificed
Side wall 208 and etch by-products can preferably protect 202 top of side wall, 203 top of etching stop layer and part inter-level dielectric
Layer 204 is injury-free.
In the present embodiment, after forming gate recess 209, the bottom of gate recess 209 can expose high-k gate dielectric layer.Other
In embodiment, if the material of gate dielectric layer is silica, gate silicon oxide dielectric layer is exposed in 209 bottom of gate recess.
Then, with reference to figure 11, side wall 208 is sacrificed in removal（With reference to figure 10）.
In the present embodiment, removal sacrifices the method for side wall 208 for ashing or wet etching.
It should be noted that：Why sacrifice the material of side wall 208 cannot use silica or silicon nitride.Be because, after
When side wall 208 is sacrificed in continuous removal, interlayer dielectric layer 204, side wall 202 and 203 part of etching stop layer can equally be removed.
Then, with continued reference to Figure 11 and Figure 12, step S16 is performed, the second sacrificial layer 206 is removed, in the gate recess
Filling metal material layer 210 ' forms metal gates 210 in 209.
In the present embodiment, when the material of the second sacrificial layer 206 is amorphous carbon, the method removal of ashing may be employed.When
When the material of two sacrificial layers 206 is first polymer, ashing or the method removal of wet etching may be employed.The wet etching
Agent is hydrofluoric acid containing solution.
In the present embodiment, in order to save processing step, while remove the second sacrificial layer 206 and sacrifice side wall 208.Other realities
The second sacrificial layer 206 and sacrifice side wall 208 can also be removed step by step by applying in example.
In the second sacrificial layer 206 of removal and after sacrificing side wall 208, form metal material layer, fill gate recess 209 and
Cover 202 top of side wall, 203 top of etching stop layer and interlayer dielectric layer 204.Then, with reference to figure 12, removal is situated between higher than interlayer
The metal material layer at 204 top of matter layer, forms metal gates 210.
In other embodiments, if gate recess bottom is gate silicon oxide dielectric layer, the second sacrificial layer and sacrifice are removed
After the step of side wall, formed metal material layer the step of before, it is necessary to gate silicon oxide dielectric layer be removed, then in gate recess
Bottom and side wall formed high-k gate dielectric layer.
In the present embodiment, the first sacrificial layer being epitaxially-formed not only covers the top of dummy grid, also covers side wall
Top, etching stop layer top and part interlayer dielectric layer.Then, the second sacrificial layer is formed on interlayer dielectric layer, described
It is equal at the top of first sacrificial layer at the top of two sacrificial layers.After removing the first sacrificial layer, what is formed in the second sacrificial layer opens
Mouth bottom not only exposes the top of dummy grid, also exposes side wall top, etching stop layer top and part interlayer dielectric layer.
Therefore, it is necessary to be formed to sacrifice side wall in the side wall of opening, adjacent two are sacrificed an exposing dummy grid between side wall.In this way, it carves
During etching off removes dummy grid, sacrifice side wall and the second sacrificial layer protects side wall top, etching stop layer top and portion jointly
Divide interlayer dielectric layer injury-free, therefore, during etching removal dummy grid, interlayer dielectric layer, side wall and quarter will not be caused
The height for losing stop-layer declines.So that the depth of the gate recess formed will not reduce, ensure that subsequently in gate recess
The height of the metal gates of formation improves the performance of metal gates.
Why the first sacrificial layer at least covered at the top of dummy grid is formed using the method for epitaxial growth, reason is as follows：
First sacrificial layer is formed using the method for epitaxial growth, the first sacrificial layer can all cover dummy grid, moreover, first sacrifices
The position of layer determines the position of the opening in the second sacrificial layer, so that the sacrifice side wall of the second sacrificial layer and opening sidewalls
Accurately the top of dummy grid can be exposed.And then can accurately remove dummy grid, meanwhile, avoid side wall, etch-stop
Only layer and interlayer dielectric layer are damaged.This process is autoregistration process, and before etching removes dummy grid, the second of formation sacrifices
Layer and sacrifice side wall can accurately expose dummy grid.
And second in background technology is mentioned in attempting：If patterned light is directly formed at the top of interlayer dielectric layer
Photoresist ideally wishes that the patterned photoresist only exposes the top of dummy grid.However, the CD sizes and light of dummy grid
The limitation of the alignment precision of carving technology so that patterned photoresist accurately can not only expose dummy grid, while also can or it is more
Or it is a kind of in few exposing side wall, etching stop layer and interlayer dielectric layer, two or three.Therefore, dummy grid is removed in etching
During, can be damaged side wall, etching stop layer and interlayer dielectric layer.
Therefore, it can avoid the problem that the alignment precision that second of trial is run into is poor using the method for the present embodiment,
It can be very good using self aligned method at the top of protection interlayer dielectric layer, side wall top and etching stop layer in removal dummy grid
During it is injury-free so that the depth of gate recess will not reduce, and then make the height of metal gates being subsequently formed
It will not reduce.
In other embodiment, only covered at the top of dummy grid and at the top of side wall using the first sacrificial layer being epitaxially-formed
Within belonging to the scope of protection of the present invention.
In other embodiment, the first sacrificial layer is only covered at the top of dummy grid, at the top of side wall and etching stop layer top also belongs to
Within protection scope of the present invention.
In other embodiment, the first sacrificial layer is only covered at the top of dummy grid, is fallen within protection scope of the present invention.It needs
It is noted that after the first sacrificial layer of removal, only exposed in the open bottom that the second sacrificial layer is formed at the top of dummy grid, because
This, need not form the step of sacrificing side wall in the opening sidewalls of the second sacrificial layer.After removing the first sacrificial layer, can directly it go
Except dummy grid.Then remove the second sacrificial layer and form gate recess.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (16)
1. a kind of forming method of metal gates, which is characterized in that including：
Semiconductor substrate is provided, dummy grid is formed in the substrate surface, forms interlayer dielectric layer on substrate, the interlayer is situated between
It is equal at the top of the dummy grid at the top of matter layer；
Using being epitaxially-formed the first sacrificial layer at least covered at the top of the dummy grid；
The second sacrificial layer is formed on interlayer dielectric layer, the second sacrificial layer top is equal at the top of first sacrificial layer；
First sacrificial layer is removed, opening is formed in second sacrificial layer, the open bottom exposes the dummy grid
Top；
After removing first sacrificial layer, the dummy grid is removed, gate recess is formed in the interlayer dielectric layer；
The second sacrificial layer is removed, metal layer is filled in the gate recess and forms metal gates；
First sacrificial layer also covering part interlayer dielectric layer, after removing the first sacrificial layer, the step of removing the dummy grid
Before, step is further included：It is formed in the opening sidewalls and sacrifices side wall；
After the step of removing the dummy grid, remove the second sacrificial layer the step of before, further include step：Remove the sacrifice
Side wall.
2. the forming method of metal gates as described in claim 1, which is characterized in that it is sacrificial that second is formed on interlayer dielectric layer
The method of domestic animal layer includes：
The second sacrificial material layer is formed, covers the interlayer dielectric layer and the first sacrificial layer；
Removal is higher than the second sacrificial material layer at the top of the first sacrificial layer.
3. the forming method of metal gates as claimed in claim 2, which is characterized in that the material of second sacrificial layer is non-
Brilliant carbon or first polymer, the first polymer include one kind in carbon or fluorine, bromine, chlorine element.
4. the forming method of metal gates as claimed in claim 2, which is characterized in that the material of second sacrificial layer is bottom
Portion's anti-reflecting layer.
5. the forming method of the metal gates as described in claim 3 or 4, which is characterized in that form second expendable material
The method of layer is deposition or smears；
Removal is chemical mechanical grinding or etching higher than the method for the second sacrificial material layer at the top of the first sacrificial layer.
6. the forming method of the metal gates as described in claim 3 or 4, which is characterized in that the method for the second sacrificial layer of removal
For ashing.
7. the forming method of metal gates as described in claim 1, which is characterized in that the forming method bag for sacrificing side wall
It includes：
It is formed and sacrifices spacer material layer, fill the opening and cover second sacrificial layer；
The sacrifice spacer material layer is etched, is formed in the opening sidewalls and sacrifices side wall.
8. the forming method of metal gates as claimed in claim 7, which is characterized in that the material for sacrificing side wall is second
Polymer, the second polymer are prepared by hydrocarbon gas.
9. the forming method of metal gates as claimed in claim 8, which is characterized in that removing the method for sacrificing side wall is
Ashing.
10. the forming method of metal gates as described in claim 1, which is characterized in that the material of first sacrificial layer with
The material identical of the dummy grid.
11. the forming method of metal gates as claimed in claim 10, which is characterized in that the material of the dummy grid is polycrystalline
Silicon, the material of first sacrificial layer is polysilicon.
12. the forming method of metal gates as claimed in claim 11, which is characterized in that removal the first sacrificial layer method be
Wet etching or dry etching.
13. the forming method of metal gates as described in claim 1, which is characterized in that form pseudo- grid in the substrate surface
After the step of pole, on substrate before the step of formation interlayer dielectric layer, further include：Side is formed around the dummy gate
Wall.
14. the forming method of metal gates as described in claim 1, which is characterized in that the material of the interlayer dielectric layer is
Silica.
15. the forming method of metal gates as described in claim 1, which is characterized in that in the substrate and the dummy grid
Between further include gate dielectric layer, the gate dielectric layer is exposed in the gate recess bottom, and the gate dielectric layer is high-k gate dielectric
Layer.
16. the forming method of metal gates as described in claim 1, which is characterized in that in the substrate and the dummy grid
Between further include gate dielectric layer, the gate dielectric layer is exposed in the gate recess bottom, and the gate dielectric layer is silicon oxide layer, is gone
After the second sacrificial layer, in the gate recess fill metal layer the step of before, further include：Remove the silica
Layer forms high-k gate dielectric layer in the bottom and side wall of the gate recess.
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| CN105161408A (en) * | 2015-09-22 | 2015-12-16 | 上海华力微电子有限公司 | Method for manufacturing high-K metal gate structure |
| CN109917503B (en) * | 2019-03-18 | 2021-04-23 | 京东方科技集团股份有限公司 | Grating device, manufacturing method thereof and display device |
| CN112951760B (en) * | 2019-11-26 | 2022-06-24 | 长鑫存储技术有限公司 | Memory and forming method thereof |
| CN112141999B (en) * | 2020-09-27 | 2024-01-02 | 地球山(苏州)微电子科技有限公司 | Manufacturing method of MEMS device and MEMS device |
| CN112151386B (en) * | 2020-09-27 | 2023-01-06 | 中国科学院微电子研究所 | Stacked nanowire ring gate device and manufacturing method thereof |
| CN112670172A (en) * | 2020-12-29 | 2021-04-16 | 上海集成电路装备材料产业创新中心有限公司 | Preparation method of metal gate device |
| CN115332061B (en) * | 2022-10-13 | 2022-12-16 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
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