CN103390547B - There is the method for forming semiconductor structure of metal gate electrode layer - Google Patents
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Abstract
A method for forming semiconductor structure with metal gate electrode layer, comprising: substrate is provided, and substrate surface is formed with the first alternative gate electrode layer, the second alternative gate electrode layer, etching barrier layer and interlayer dielectric layer; Planarization interlayer dielectric layer and etching barrier layer are until expose the first alternative gate electrode layer and the second alternative gate electrode layer; Remove the first alternative gate electrode layer and form the first opening, and fill the first opening and form the first metal gate electrode layer; Planarization the first metal gate electrode layer, interlayer dielectric layer, etching barrier layer and the second alternative gate electrode layer, form protective layer on the first metal gate electrode layer surface; Remove the second alternative gate electrode layer and form the second opening, and fill the second opening and form the second metal gate electrode layer; Planarization the second metal gate electrode layer, interlayer dielectric layer, etching barrier layer and the first metal gate electrode layer. Utilize method for forming semiconductor structure provided by the present invention can improve the performance of the semiconductor structure with metal gate electrode layer.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of semiconductor with metal gate electrode layerStructure formation method.
Background technology
Along with combined metal oxide semiconductor's structure (CMOS, ComplementaryMetal-Oxide-Semiconductor) constantly dwindling of characteristic size, high-K metal gate electrode layer is extensiveSubstituted traditional polygate electrodes layer. And the formation of high-K metal gate electrode layer comprises " front grid "(gate-first) (gate-last) two kinds of techniques of technique and " rear grid ". Wherein, answering of " rear grid " techniqueWith more extensive. The rear grid technique that high-K metal gate electrode layer forms in technique is specially:
First, provide substrate, described substrate surface has polysilicon dummy gate layer and is positioned at the pseudo-grid of polysiliconThe side wall of utmost point layer both sides;
Secondly the etching that, covers described polysilicon dummy gate layer and side wall in described substrate surface formation stopsLayer;
Afterwards, form interlayer dielectric layer on described etching barrier layer surface;
Described in the planarization of employing flatening process, interlayer dielectric layer and etching barrier layer are until expose described manyCrystal silicon dummy gate layer;
Remove described polysilicon dummy gate layer, form opening;
Form high K dielectric layer in described open bottom, described in the formation filling of described high K dielectric layer surfaceThe metal gate electrode layer of opening.
In the U.S. patent documents that is US2010/0081262A1 at publication number, can also find moreThe formation technique of HKMG.
But find in practice the semiconductor junction with metal gate electrode layer forming by said methodThe performance of structure is also bad.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure side of formation with metal gate electrode layerMethod,, can improve the performance of the semiconductor structure with metal gate electrode layer.
For addressing the above problem, the invention provides following technical scheme:
A method for forming semiconductor structure with metal gate electrode layer, comprising:
Substrate is provided, and described substrate surface is formed with the first alternative gate electrode layer and the second alternative gate electrode layer,And cover the etching barrier layer of described the first alternative gate electrode layer and the second alternative gate electrode layer; Described quarterErosion barrier layer surface is formed with interlayer dielectric layer;
Interlayer dielectric layer and etching barrier layer described in planarization are until expose described the first alternative gate electrode layerWith the second alternative gate electrode layer;
Remove described the first alternative gate electrode layer, form the first opening, and fill described the first opening, shapeBecome the first metal gate electrode layer;
The first metal gate electrode layer described in planarization, described interlayer dielectric layer, described etching barrier layer andDescribed the second alternative gate electrode layer, and form protective layer on described the first metal gate electrode layer surface;
Remove described the second alternative gate electrode layer, form the second opening, and fill described the second opening, shapeBecome the second metal gate electrode layer;
The second metal gate electrode layer described in planarization, described interlayer dielectric layer, described etching barrier layer andDescribed the first metal gate electrode layer.
Preferably, the formation technique of described protective layer is plasma oxidation process.
Preferably, the processing gas in described plasma oxidation process is O2Or O3。
Preferably, the formation technique of described protective layer is non-plasma oxidation technology.
Preferably, the formation technique of described protective layer is plasma nitridation process.
Preferably, the processing gas in described plasma nitridation process is NO, NH3Or NO2。
Preferably, the formation technique of described protective layer is non-plasma nitriding process.
Preferably, the thickness of described protective layer is 50 dust-200 dusts.
Preferably, the material of described metal gate electrode layer is Al, Cu, Ag or W.
Preferably, between described the first alternative gate electrode layer bottom and described substrate, described second grid replacesFor being formed with high-K gate dielectric layer between layer and described substrate.
Preferably, described high-K gate dielectric layer material is hafnium oxide, hafnium silicon oxide, lanthana, oxidationLanthanum aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, oxidationStrontium titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc.
Preferably, described high-K gate dielectric layer surface is formed with dielectric barrier.
Preferably, the material of described dielectric barrier is TiN or TaN.
Compared with prior art, the present invention has the following advantages:
Technical scheme provided by the present invention, first forms protection on described the first metal gate electrode layer surfaceLayer, and then remove described the second alternative gate electrode layer, form the second opening, and fill described second and openMouthful, form the second metal gate electrode layer, thereby removing after described the second alternative gate electrode layer, remove instituteWhile stating the existing oxide layer of the second open bottom, described protective layer can be to described the first metal gate electrodeLayer plays certain protective effect, and then reduces in the time removing the oxide layer of described the second open bottom, rightThe metal loss that the first metal gate electrode layer brings, improves the semiconductor with metal gate electrode layer with thisThe performance of structure.
Brief description of the drawings
Fig. 1 is the method for forming semiconductor structure with metal gate electrode layer that the embodiment of the present invention providesProcess flow diagram;
Fig. 2-Fig. 8 is that the semiconductor structure with metal gate electrode layer that the embodiment of the present invention provides formsThe cross-sectional view of procedure.
Detailed description of the invention
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but thisBrightly can also adopt other to be different from alternate manner described here to implement, those skilled in the art canWithout prejudice to intension of the present invention in the situation that, do similar popularization, therefore the present invention is not subject to following public concreteThe restriction of embodiment.
Just as described in the background section, the semiconductor with metal gate electrode layer forming in prior artThe performance of structure is also bad. Inventor studies discovery, and this is due to described combined metal oxide semiconductorStructure (CMOS) comprises the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, therefore, need to form two and substituteGate electrode layer, and successively carry out twice removal alternative gate electrode layer, forms metal gate electrode layer, theAfter one metal gate electrode layer forms, then remove the second alternative gate electrode layer, form the second metal gate electrodeLayer. But in actual process manufacturing process, remove described alternative gate electrode layer, after forming opening,Find that described open bottom can exist layer of oxide layer, and in the forming process of the second metal gate electrode layer,While removing the oxide layer of the open bottom corresponding with it, can be to the first metal gate electrode layer band having formedCarry out certain metal loss, thereby reduce the performance of the semiconductor structure with metal gate electrode layer.
Inventor further studies discovery, if want in the situation that described the first metal gate electrode layer exposes,Remove the oxide layer of described the second open bottom, need the etch rate of very high oxide layer and metal to selectRatio, and the material of metal gate electrode layer described in prior art mostly is Al, Al is not only dissolved in strong acid but also be dissolved in strongAlkali, therefore, in the time utilizing wet etching to remove the oxide layer of described the second open bottom, the choosing of etching liquidSelect comparatively difficulty, and can dissolve part metals Al simultaneously, thereby described the first metal gate electrode layer is madeBecome certain metal loss.
In view of this, the present inventor provides a kind of semiconductor structure with metal gate electrode layerFormation method, as shown in Figure 1, comprises the following steps:
Step S01: substrate is provided, and described substrate surface is formed with the first alternative gate electrode layer and second and substitutesGate electrode layer, and the etching that covers described the first alternative gate electrode layer and the second alternative gate electrode layer stopsLayer; Described etching barrier layer surface is formed with interlayer dielectric layer;
Step S102: interlayer dielectric layer and etching barrier layer described in planarization are until expose described first and replaceFor gate electrode layer and the second alternative gate electrode layer;
Step S103: remove described the first alternative gate electrode layer, form the first opening, and fill described theOne opening, forms the first metal gate electrode layer;
Step S104: the first metal gate electrode layer, described interlayer dielectric layer, described etching described in planarizationBarrier layer and described the second alternative gate electrode layer, and form and protect on described the first metal gate electrode layer surfaceSheath;
Step S105: remove described the second alternative gate electrode layer, form the second opening, and fill described theTwo openings, form the second metal gate electrode layer;
Step S106: the second metal gate electrode layer, described interlayer dielectric layer, described etching described in planarizationBarrier layer and described the first metal gate electrode layer.
As from the foregoing, technical scheme provided by the present invention, first at described the first metal gate electrode layer tableFace forms protective layer, and then removes described the second alternative gate electrode layer, forms the second opening, and fillsDescribed the second opening, forms the second metal gate electrode layer, thereby is removing described the second alternative gate electrode layerAfter, while removing the existing oxide layer of described the second open bottom, described protective layer can be to described firstMetal gate electrode layer plays certain protective effect, and then reduces at the oxygen of removing described the second open bottomChange when layer, the metal loss that the first metal gate electrode layer is brought, has metal gate electrode layer to improveThe performance of semiconductor structure.
What below in conjunction with specific embodiment, the embodiment of the present invention is provided has partly leading of metal gate electrode layerThe formation method of body structure is specifically described.
Step 101, as shown in Figure 2, provides substrate 200, and described substrate 200 surfaces are formed with first and replaceFor gate electrode layer 201 and the second alternative gate electrode layer 202, and cover described the first alternative gate electrode layer201 and the etching barrier layer 203 of the second alternative gate electrode layer 202; The surperficial shape of described etching barrier layer 203Become to have interlayer dielectric layer 204.
The effect of described substrate 200 is for follow-up formation semiconductor devices provides workbench, described substrate200 materials can be silicon (SOI) substrate, the nitrogenize on N-shaped silicon substrate, p-type silicon substrate, insulating barrierThe III-V such as silicon substrate and GaAs compounds of group etc. Described the first alternative gate electrode layer 201 and second replacesCan be one or the group in polysilicon, germanium, SiGe, silicon nitride or silica for gate electrode layer 202Close. In the present embodiment, described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202 are manyCrystal silicon, thickness is 1000 ~ 2000 dusts.
In an embodiment of the present invention, described the first alternative gate electrode layer 201 bottoms and described substrate 200Between and between described the second alternative gate electrode layer 202 bottoms and described substrate 200, be also formed with high KGate dielectric layer 205. Wherein, the material of described high-K gate dielectric layer 205 be hafnium oxide, hafnium silicon oxide,Lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, oxygenChange barium titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc etc., and described high KThe formation technique of gate dielectric layer 205 can be chemical vapour deposition technique or physical vapour deposition (PVD).
Cover the etching barrier layer of described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202203 material is silicon nitride, and formation method is chemical vapour deposition technique, in the present embodiment, and described etchingThe material on barrier layer 203 is silicon nitride, and described etching barrier layer 203 covers described the first alternative gate electricityUtmost point layer 201 and the second alternative gate electrode layer 202 and described substrate 200. At other embodiment of the present inventionIn, can also remove the etching barrier layer 203 that is positioned at described substrate 200 surfaces.
Described interlayer dielectric layer 204 is the inorganic silicon matrix layer (inorganicsilicon with low-kBasedlayer), general described low-k is less than 3.0, for example silicon oxide carbide (SiCO) or silicon fluorideGlass (FSG), in the present embodiment, the material of described interlayer dielectric layer 204 is silica, formsTechnique is chemical vapour deposition technique.
In described substrate 200, be also formed with multiple STI(fleet plough groove isolation structures) 207 and multiple source-drain area(not shown), wherein, described source-drain area lays respectively at the first alternative gate electrode layer 201 and second and replacesIn semiconductor base 200 for gate electrode layer 202 down either side; Described STI(fleet plough groove isolation structure)207 are positioned at described source-drain area centre and the semiconductor base 200 away from described alternative gate electrode layer, forIsolate adjacent metal-oxide-semiconductor, it specifically forms technique and please refer to prior art, repeats no more here.
Step 102, as shown in Figure 3, interlayer dielectric layer 204 and etching barrier layer 203 are straight described in planarizationTo exposing described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202.
Described flatening process is the first CMP process, concrete, described the first chemical machineryThe Basic Mechanism of polishing is surface hydration effect, and the water in lapping liquid and silica or silicon nitride reaction are rawBecome hydrogen-oxygen key, form moisture soft top layer, thereby reduce hardness, intensity and the change of silica or silicon nitrideLearn durability, then adopt mechanical means to utilize particle in lapping liquid by the silica in moisture soft top layerOr silicon nitride is removed.
Described in the embodiment of the present invention, the first CMP process parameter is: chemically mechanical polishing adoptsLapping liquid taking silica or cerium oxide as main component, described lapping liquid is to silica and nitrogenizeThe planarization speed of silicon is selected than being greater than 1.
Step 103, as shown in Figure 4, removes described the first alternative gate electrode layer 201, forms the first opening208, and fill described the first opening 208, as shown in Figure 5, form the first metal gate electrode layer 210.
The technique of described removal the first alternative gate electrode layer 201 is dry etching or wet etching. At thisIn a bright embodiment, described dry etching method adopts reactive ion etching method, and the gas of employing canSelect fluorine gas or chlorine. Adopt the advantage of dry etching to be, anisotropy, selective good and etching effectRate is high. In another embodiment of the present invention, described wet etching can select TMAH moltenLiquid, also can select ammoniacal liquor to remove described the first alternative gate electrode layer 201.
As shown in Figure 4, remove after described the first alternative gate electrode layer 201, can find that first of formation holdsThere is layer of oxide layer 215 in mouth 208 bottoms, this is due in aforesaid technical process, described substrateSilicon atom in 200 can be diffused into described high-K gate dielectric layer 205 surfaces, thereby is removing described firstOxidized in the process of alternative gate electrode layer 201, and then form one deck oxygen on described high K dielectric layer surfaceChange layer 215, finally affect the performance of the follow-up semiconductor devices of making. Therefore, form described the first openingAfter 208, need first the oxide layer 215 of described the first opening 208 bottoms to be removed, then form the first gold medalBelong to gate electrode layer 210.
The removal of the oxide layer 215 of described the first opening 208 bottoms can adopt strong acid and strong base solution to carry outRepeatedly clean, in the embodiment of the present invention, adopt the HF acid of dilution repeatedly to clean.
In a preferred embodiment of the invention, for fear of removing described the first alternative gate electrode layer 201Process in described high K dielectric layer is caused to damage, described high K dielectric layer surface is also formed with medium resistanceGear layer 206. The material of described dielectric barrier 206 is TiN or TaN, and forming technique is that chemical gaseous phase is heavyLong-pending method or physical vapour deposition (PVD).
As shown in Figure 5, after removing the oxide layer 215 of described the first opening 208 bottoms, need first to existDeposit work function layer 209 on the inwall of described the first opening 208, and then carry out metal filledly, form theOne metal gate electrode layer 210, its concrete technology, with reference to prior art, repeats no more here. Wherein, described inThe material of the first metal gate electrode layer 210 can be Al, Cu, Ag or W etc.; Described work function layer 209Material be TiN, TaN, TiAl or Ta.
Step S104, as shown in Figure 6, the first metal gate electrode layer 210, described interlayer described in planarizationDielectric layer 204, described etching barrier layer 203 and described the second alternative gate electrode layer 202, and describedThe first metal gate electrode layer 210 surfaces form protective layer 211.
Described flatening process is the second CMP process, concrete, described the second chemical machineryThe mechanism of polishing is chemical oxidation and mechanical lapping mechanism, and abrasive material first and Metal Contact it is carried out to oxygenChange, thereby form oxide layer in metal surface, and then utilize particle in abrasive material by the oxide layer formingGet rid of. Once this layer of oxide layer is removed, the chemical composition in abrasive material can continue oxidation and newly exposeMetal surface, and then utilize the particle in abrasive material that the oxide layer of formation is got rid of, carry out and so forth,Until described metal surface planarization. The second CMP process parameter described in the embodiment of the present inventionDepend on the circumstances according to the material of described the first metal gate electrode layer 210.
In one embodiment of the invention, described protective layer 211 is oxide layer, and its formation technique can bePlasma oxygen metallization processes or non-plasma oxygen metallization processes. The formation of protective layer 211 described in the present embodiment canAdopt non-plasma oxygen metallization processes, as thermal oxide, also can adopt plasma oxygen metallization processes, described in formationProtective layer 211 thickness are 50 dust-200 dusts.
Described plasma oxygen metallization processes is that can to change plasma by the oxidation reactor of suitable design closeDegree and underlayer temperature, so that at quite low temperature, raw on inherent metal of shorter time or semiconductorThe technique of the oxide-film that long thickness is suitable. The formation of protective layer 211 described in the present embodiment adopts plasmaWhen oxidation technology, oxidizing temperature is 20 DEG C-60 DEG C, and oxidation pressure is 2mTorr-100mTorr, and radio frequency frequentlyRate is 0.5MHz-3MHz, and described processing gas is O2Or O3, processing gas flow is 1sccm-1000sccm. Compared to non-plasma oxidation technology, the technological temperature of plasma oxidation process is lower,And growth rate is higher.
In another embodiment of the present invention, described protective layer 211 is nitration case, and its formation technique can bePlasma nitridation process or non-plasma nitridation process, the thickness of the described protective layer 211 of formation is 50 dusts-200 dusts. When the formation of protective layer 211 described in the present embodiment adopts plasma nitridation process, nitrogenize temperatureDegree is 100 DEG C-600 DEG C, and nitrogenize pressure is 0.1Torr-2Torr, and rf frequency is 0.5MHz-3MHz,Described processing gas is NO, NH3Or NO2, processing gas flow is 1sccm-1000sccm.
It should be noted that, in the time forming the protective layer 211 on described the first metal gate electrode layer 210 surfaces,Described the second alternative gate electrode layer 202 surfaces also likely form layer of oxide layer 212 simultaneously, but due toDescribed the first metal gate electrode layer 210 is different from the material of described the second alternative gate electrode layer 202, therefore,Be formed at the protective layer 211 on described the first metal gate electrode layer 210 surfaces and be formed at described second and substituteThe material of the oxide layer 212 on gate electrode layer 202 surfaces is not identical yet, thereby makes at described protective layer 211When described the first metal gate electrode layer 210 is protected, be formed at described the second alternative gate electrodeThe oxide layer 212 on layer 202 surface can't affect the etching of described the second alternative gate electrode layer 202, andAnd be etched away together together with described the second alternative gate electrode layer 202.
Step S105: as shown in Figure 7, remove described the first alternative gate electrode layer 202, form second and openMouth 213, and fill described the second opening 213, as shown in Figure 8, form the second metal gate electrode layer 214.
After described protective layer 211 forms, can adopt dry etching or wet etching to remove described second and replaceFor gate electrode layer 202, form the second opening 213, and on described opening inwall deposit work function layer 209,Then described the second opening 213 is carried out metal filled, form the second metal gate electrode layer 214, it is concreteTechnique refer step 103, is no longer described in detail here.
It should be noted that, as shown in Figure 7, remove after described the second alternative gate electrode layer 202, sameCan find that described the second opening 213 bottoms exist layer of oxide layer 215, therefore need to be at described the second openingAfter 213 formation, the oxide layer 215 of described the second opening 213 bottoms is cleaned. But due to thisShi Suoshu the first metal gate electrode layer 210 has formed, if directly to described the second opening 213 bottomsOxide layer 215 clean, can cause certain metal to damage to described the first metal gate electrode layer 210Lose. Therefore, in the step 104 before this step 105, in advance at described the first metal gate electrode layer210 surfaces have formed layer protective layer 211.
Compared to prior art, the technical scheme that the embodiment of the present invention provides, opens in removal described secondWhen the oxide layer 215 of mouthful 213 bottoms, described the first metal gate electrode layer 210 surfaces are formed with protective layer211, described protective layer 211 covers described the first metal gate electrode layer 210 completely, thereby to describedWhen the oxide layer 215 of two opening 213 bottoms is cleaned, described protective layer 211 can be to described firstMetal gate electrode layer 210 carries out certain protection, and then minimizing is positioned at described the second opening 213 in removalIn the process of bottom oxidization layer 215, the metal loss that described the first metal gate electrode layer 210 is brought.
Also it should be noted that, if there is no protective layer 211 on described the first metal gate electrode layer 210 surfacesIn situation about covering, described the second alternative gate electrode layer 202 is carried out in the process of etching, due to dry methodIn etching, there is plasma, therefore, in whole etching process, be easy at described the first metal gateElectrode layer 210 is inner forms electrolytic cell, thereby brings certain to described the first metal gate electrode layer 210Metal loss; And the etching liquid that adopts of wet etching, not only need the second higher alternative gate electrodeThe etch rate ratio of layer 202 and metal, also can bring certain to described the first metal gate electrode layer 210Metal loss.
And the protective layer 211 providing in the embodiment of the present invention, to described the second alternative gate electrode layer 202Carry out in the process of etching, cover described the first metal gate electrode layer 210 completely, thereby can remove instituteState in the process of the second alternative gate electrode layer 202, described the first metal gate electrode layer 210 protected,Thereby avoid in the etching process of described the second alternative gate electrode layer 202, to described the first metal gate electrodeLayer 210 loss bringing.
Otherwise the first metal gate electrode layer 210 surfaces do not have protective layer 211 described in prior art, butUnder the environment exposing at described the first metal gate electrode layer 210, to described the second alternative gate electrode layer 202Carry out etching, and the oxide layer 215 that is positioned at described the second opening 213 bottoms is cleaned, because carveErosion liquid and cleaning fluid have certain Etch selectivity to metal, thereby easily cause described the first metal gate electricityMetal loss in utmost point layer 210.
Step S106: the second metal gate electrode layer 214, described interlayer dielectric layer 204, institute described in planarizationState etching barrier layer 203 and described the first metal gate electrode layer 210.
Described flatening process is the second CMP process, concrete refer step S104.
In sum, in the formation method of gate electrode layer provided by the present invention, replace in removal described secondBefore gate electrode layer 202, form layer protective layer on described the first metal gate electrode layer 210 surfaces in advance211, and described protective layer 211 covers described the first metal gate electrode layer 210 completely, thereby to describedWhen the second alternative gate electrode layer 202 carries out etching, and remove the oxidation of described the second opening 213 bottomsLayer 215 o'clock, described protective layer 211 can play certain guarantor to described the first metal gate electrode layer 210Protect effect, remove described the second alternative gate electrode layer 202 and described the second opening 213 bottoms thereby reduce215 two processes of oxide layer in, the metal loss that described the first metal gate electrode layer 210 is brought,And then raising has the performance of the semiconductor structure of metal gate electrode layer.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (12)
1. a method for forming semiconductor structure with metal gate electrode layer, is characterized in that, comprising:
Substrate is provided, and described substrate surface is formed with the first alternative gate electrode layer and the second alternative gate electrode layer, and covers the etching barrier layer of described the first alternative gate electrode layer and the second alternative gate electrode layer; Described etching barrier layer surface is formed with interlayer dielectric layer, between described the first alternative gate electrode layer and described substrate and between described the second alternative gate electrode layer and described substrate, is formed with high-K gate dielectric layer;
Interlayer dielectric layer and etching barrier layer described in planarization are until expose described the first alternative gate electrode layer and the second alternative gate electrode layer;
Remove described the first alternative gate electrode layer, form the first opening, remove the oxide layer of described the first open bottom, and fill described the first opening, form the first metal gate electrode layer;
The first metal gate electrode layer, described interlayer dielectric layer, described etching barrier layer and described the second alternative gate electrode layer described in planarization, and form protective layer on described the first metal gate electrode layer surface;
Remove described the second alternative gate electrode layer, form the second opening, clean the oxide layer of described the second open bottom, and fill described the second opening, form the second metal gate electrode layer;
The second metal gate electrode layer, described interlayer dielectric layer, described etching barrier layer and described the first metal gate electrode layer described in planarization.
2. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is plasma oxidation process.
3. method for forming semiconductor structure as claimed in claim 2, is characterized in that, the processing gas in described plasma oxidation process is O2Or O3。
4. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is non-plasma oxidation technology.
5. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is plasma nitridation process.
6. method for forming semiconductor structure as claimed in claim 5, is characterized in that, the processing gas in described plasma nitridation process is NO, NH3Or NO2。
7. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is non-plasma nitriding process.
8. the method for forming semiconductor structure as described in claim 2-7 any one, is characterized in that, the thickness of described protective layer is 50 dust-200 dusts.
9. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the material of described metal gate electrode layer is Al, Cu, Ag or W.
10. method for forming semiconductor structure as claimed in claim 1, it is characterized in that, described high-K gate dielectric layer material is hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc.
11. method for forming semiconductor structures as described in claim 1 or 10, is characterized in that, described high-K gate dielectric layer surface is formed with dielectric barrier.
12. method for forming semiconductor structures as claimed in claim 11, is characterized in that, the material of described dielectric barrier is TiN or TaN.
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| CN102420185A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) |
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| CN101036225A (en) * | 2004-07-20 | 2007-09-12 | 英特尔公司 | A semiconductor device with a high-k gate dielectric and a metal gate electrode |
| CN102420185A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) |
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