CN103390547A - Method for forming semiconductor structure with metal gate electrode layers - Google Patents
Method for forming semiconductor structure with metal gate electrode layers Download PDFInfo
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- CN103390547A CN103390547A CN201210141553XA CN201210141553A CN103390547A CN 103390547 A CN103390547 A CN 103390547A CN 201210141553X A CN201210141553X A CN 201210141553XA CN 201210141553 A CN201210141553 A CN 201210141553A CN 103390547 A CN103390547 A CN 103390547A
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Abstract
The invention provides a method for forming a semiconductor structure with metal gate electrode layers. The method includes the steps that a substrate is provided, and a first replacement gate electrode layer, a second replacement gate electrode layer, an etching barrier layer and an interlayer medium layer are formed on the surface of the substrate; the interlayer dielectric layer and the etching barrier layer are flattened until the first replacement gate electrode layer and the second replacement gate electrode layer are exposed; the first replacement gate electrode layer is removed to form a first opening, and the first opening is filled to form a first metal gate electrode layer; the first metal gate electrode layer, the interlayer dielectric layer, the etching barrier layer and the second replacement gate electrode layer are flattened, and a protective layer is formed on the surface of the first metal gate electrode layer; the second replacement gate electrode layer is removed to form a second opening, and the second opening is filled to form a second metal gate electrode layer; the second metal gate electrode layer, the interlayer dielectric layer, the etching barrier layer and the first metal gate electrode layer are flattened. According to the method for forming the semiconductor structure with the metal gate electrode layers, the performance of the semiconductor structure with the metal gate electrode layers can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method for forming semiconductor structure with metal gate electrode layer.
Background technology
Along with constantly dwindling of combined metal oxide semiconductor's structure (CMOS, Complementary Metal-Oxide-Semiconductor) characteristic size, the high-K metal gate electrode layer has substituted traditional polygate electrodes layer widely.And the formation of high-K metal gate electrode layer comprises " front grid " (gate-first) (gate-last) two kinds of techniques of technique and " rear grid ".Wherein, the application of " rear grid " technique is more extensive.The rear grid technique that the high-K metal gate electrode layer forms in technique is specially:
At first, provide substrate, described substrate surface has the polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides;
Secondly, form at described substrate surface the etching barrier layer that covers described polysilicon dummy gate layer and side wall;
Afterwards, form interlayer dielectric layer on described etching barrier layer surface;
Adopt the described interlayer dielectric layer of flatening process planarization and etching barrier layer until expose described polysilicon dummy gate layer;
Remove described polysilicon dummy gate layer, form opening;
Form the high K dielectric layer in described open bottom, on described high K dielectric layer surface, form the metal gate electrode layer of filling described opening.
In being the U.S. patent documents of US2010/0081262A1, publication number can also find the formation technique of more HKMG.
But find in practice, the performance by the formed semiconductor structure with metal gate electrode layer of said method is also bad.
Summary of the invention
The problem that the present invention solves is to provide a kind of method for forming semiconductor structure with metal gate electrode layer,, can improve the performance of the semiconductor structure with metal gate electrode layer.
, for addressing the above problem, the invention provides following technical scheme:
A kind of method for forming semiconductor structure with metal gate electrode layer comprises:
Substrate is provided, and described substrate surface is formed with the first alternative gate electrode layer and the second alternative gate electrode layer, and the etching barrier layer that covers described the first alternative gate electrode layer and the second alternative gate electrode layer; Described etching barrier layer surface is formed with interlayer dielectric layer;
The described interlayer dielectric layer of planarization and etching barrier layer are until expose described the first alternative gate electrode layer and the second alternative gate electrode layer;
Remove described the first alternative gate electrode layer, form the first opening, and fill described the first opening, form the first metal gate electrode layer;
Described the first metal gate electrode layer of planarization, described interlayer dielectric layer, described etching barrier layer and described the second alternative gate electrode layer, and on described the first metal gate electrode layer surface, form protective layer;
Remove described the second alternative gate electrode layer, form the second opening, and fill described the second opening, form the second metal gate electrode layer;
Described the second metal gate electrode layer of planarization, described interlayer dielectric layer, described etching barrier layer and described the first metal gate electrode layer.
Preferably, the formation technique of described protective layer is plasma oxidation process.
Preferably, the processing gas in described plasma oxidation process is O
2Or O
3.
Preferably, the formation technique of described protective layer is the non-plasma oxidation technology.
Preferably, the formation technique of described protective layer is plasma nitridation process.
Preferably, the processing gas in described plasma nitridation process is NO, NH
3Or NO
2.
Preferably, the formation technique of described protective layer is the non-plasma nitriding process.
Preferably, the thickness of described protective layer is 50 dusts-200 dusts.
Preferably, the material of described metal gate electrode layer is Al, Cu, Ag or W.
Preferably, between described the first alternative gate electrode layer bottom and described substrate, be formed with high-K gate dielectric layer between described second grid substitutable layer and described substrate.
Preferably, described high-K gate dielectric layer material is hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc.
Preferably, described high-K gate dielectric layer surface is formed with dielectric barrier.
Preferably, the material of described dielectric barrier is TiN or TaN.
Compared with prior art, the present invention has the following advantages:
technical scheme provided by the present invention, at first form protective layer on described the first metal gate electrode layer surface, and then remove described the second alternative gate electrode layer, form the second opening, and fill described the second opening, form the second metal gate electrode layer, thereby after removing described the second alternative gate electrode layer, while removing described the second existing oxide layer of open bottom, described protective layer can play certain protective effect to described the first metal gate electrode layer, and then reduce when removing the oxide layer of described the second open bottom, the metal loss that the first metal gate electrode layer is brought, improve the performance of the semiconductor structure with metal gate electrode layer with this.
Description of drawings
Fig. 1 is the process flow diagram of the method for forming semiconductor structure with metal gate electrode layer that provides of the embodiment of the present invention;
Fig. 2-Fig. 8 is the cross-sectional view of the method for forming semiconductor structure process with metal gate electrode layer that provides of the embodiment of the present invention.
Embodiment
, for above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
The performance of the semiconductor structure with metal gate electrode layer that forms in prior art just as described in the background section, is also bad.The inventor studies discovery, this is because described combined metal oxide semiconductor structure (CMOS) comprises the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, therefore, need to form two alternative gate electrode layers, and successively carry out twice and remove the alternative gate electrode layer, form metal gate electrode layer, namely after the first metal gate electrode layer forms, remove again the second alternative gate electrode layer, form the second metal gate electrode layer.Yet in actual process manufacturing process, remove described alternative gate electrode layer, after forming opening, find that can there be layer of oxide layer in described open bottom, and in the forming process of the second metal gate electrode layer, while removing the oxide layer of the open bottom corresponding with it, can bring certain metal loss to the first metal gate electrode layer that has formed, thereby reduce the performance of the semiconductor structure with metal gate electrode layer.
The inventor further studies discovery, if think in the situation that described the first metal gate electrode layer exposes, remove the oxide layer of described the second open bottom, need the etch rate of very high oxide layer and metal to select ratio, and the material of metal gate electrode layer described in prior art mostly is Al, Al not only is dissolved in strong acid but also be dissolved in highly basic, therefore, when utilizing wet etching to remove the oxide layer of described the second open bottom, the selection of etching liquid is difficulty comparatively, and can dissolve simultaneously part metals Al, thereby described the first metal gate electrode layer is caused certain metal loss.
In view of this, the present inventor provides a kind of method for forming semiconductor structure with metal gate electrode layer, as shown in Figure 1, comprises the following steps:
Step S01: substrate is provided, and described substrate surface is formed with the first alternative gate electrode layer and the second alternative gate electrode layer, and the etching barrier layer that covers described the first alternative gate electrode layer and the second alternative gate electrode layer; Described etching barrier layer surface is formed with interlayer dielectric layer;
Step S102: the described interlayer dielectric layer of planarization and etching barrier layer are until expose described the first alternative gate electrode layer and the second alternative gate electrode layer;
Step S103: remove described the first alternative gate electrode layer, form the first opening, and fill described the first opening, form the first metal gate electrode layer;
Step S104: described the first metal gate electrode layer of planarization, described interlayer dielectric layer, described etching barrier layer and described the second alternative gate electrode layer, and on described the first metal gate electrode layer surface, form protective layer;
Step S105: remove described the second alternative gate electrode layer, form the second opening, and fill described the second opening, form the second metal gate electrode layer;
Step S106: described the second metal gate electrode layer of planarization, described interlayer dielectric layer, described etching barrier layer and described the first metal gate electrode layer.
as from the foregoing, technical scheme provided by the present invention, at first form protective layer on described the first metal gate electrode layer surface, and then remove described the second alternative gate electrode layer, form the second opening, and fill described the second opening, form the second metal gate electrode layer, thereby after removing described the second alternative gate electrode layer, while removing described the second existing oxide layer of open bottom, described protective layer can play certain protective effect to described the first metal gate electrode layer, and then reduce when removing the oxide layer of described the second open bottom, the metal loss that the first metal gate electrode layer is brought, the performance that has the semiconductor structure of metal gate electrode layer with raising.
The formation method of the semiconductor structure with metal gate electrode layer that the embodiment of the present invention is provided below in conjunction with specific embodiment is specifically described.
Step 101, as shown in Figure 2, substrate 200 is provided, and described substrate 200 surfaces are formed with the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202, and the etching barrier layer 203 that covers described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202; Described etching barrier layer 203 surfaces are formed with interlayer dielectric layer 204.
The effect of described substrate 200 is for follow-up formation semiconductor device provides workbench, and described substrate 200 materials can be III-V compounds of group such as silicon (SOI) substrate, silicon nitride substrate and GaAs on N-shaped silicon substrate, p-type silicon substrate, insulating barrier etc.Described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202 can be a kind of or combination in polysilicon, germanium, SiGe, silicon nitride or silica.In the present embodiment, described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202 are polysilicon, and thickness is 1000 ~ 2000 dusts.
In an embodiment of the present invention, also be formed with high-K gate dielectric layer 205 between described the first alternative gate electrode layer 201 bottoms and described substrate 200 and between described the second alternative gate electrode layer 202 bottoms and described substrate 200.Wherein, the material of described high-K gate dielectric layer 205 is hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc etc., and the formation technique of described high-K gate dielectric layer 205 can be chemical vapour deposition technique or physical vapour deposition (PVD).
The material that covers the etching barrier layer 203 of described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202 is silicon nitride, the formation method is chemical vapour deposition technique, in the present embodiment, the material of described etching barrier layer 203 is silicon nitride, and described etching barrier layer 203 covers described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202 and described substrate 200.In other embodiments of the invention, can also remove the etching barrier layer 203 that is positioned at described substrate 200 surfaces.
Described interlayer dielectric layer 204 is the inorganic silicon matrix layers (inorganic silicon based layer) with low-k, general described low-k is less than 3.0, for example silicon oxide carbide (SiCO) or fluorinated silica glass (FSG), in the present embodiment, the material of described interlayer dielectric layer 204 is silicon dioxide, and formation technique is chemical vapour deposition technique.
Also be formed with a plurality of STI(fleet plough groove isolation structures in described substrate 200) 207 and a plurality of source-drain area (not shown), wherein, described source-drain area lays respectively in the semiconductor base 200 of the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202 down either side; Described STI(fleet plough groove isolation structure) 207 are positioned in the middle of described source-drain area and, away from the semiconductor base 200 of described alternative gate electrode layer, are used for isolating adjacent metal-oxide-semiconductor, and it specifically forms technique and please refer to prior art, repeats no more here.
Step 102, as shown in Figure 3, the described interlayer dielectric layer 204 of planarization and etching barrier layer 203 are until expose described the first alternative gate electrode layer 201 and the second alternative gate electrode layer 202.
Described flatening process is the first CMP (Chemical Mechanical Polishing) process, concrete, the Basic Mechanism of described the first chemico-mechanical polishing is the surface hydration effect, be water and silica or the silicon nitride reaction generation hydrogen-oxygen key in lapping liquid, form moisture soft top layer, thereby reduce hardness, intensity and the chemical durability of silica or silicon nitride, then adopt mechanical means to utilize the particle in lapping liquid that the silica in moisture soft top layer or silicon nitride are removed.
Described in the embodiment of the present invention, the first CMP (Chemical Mechanical Polishing) process parameter is: the lapping liquid that chemico-mechanical polishing is adopted is take silica or cerium oxide as main component, and described lapping liquid is selected than greater than 1 the planarization speed of silica and silicon nitride.
Step 103, as shown in Figure 4, remove described the first alternative gate electrode layer 201, forms the first opening 208, and fill described the first opening 208, as shown in Figure 5, forms the first metal gate electrode layer 210.
The technique of described removal the first alternative gate electrode layer 201 is dry etching or wet etching.In one embodiment of the invention, described dry etching method adopts the reactive ion etching method, and the gas of employing can be selected fluorine gas or chlorine.Adopt the advantage of dry etching to be, anisotropy, selectivity is good and etching efficiency is high.In another embodiment of the present invention, described wet etching can be selected tetramethyl ammonium hydroxide solution, also can select ammoniacal liquor to remove described the first alternative gate electrode layer 201.
As shown in Figure 4, after removing described the first alternative gate electrode layer 201, can find that there is layer of oxide layer 215 in the first opening 208 bottoms that form, this is due in aforesaid technical process, silicon atom in described substrate 200 can be diffused into described high-K gate dielectric layer 205 surfaces, thereby oxidized in the process of removing described the first alternative gate electrode layer 201, and then on described high K dielectric layer surface, form layer of oxide layer 215, finally affect the performance of the follow-up semiconductor device of making.Therefore, after forming described the first opening 208, need to first the oxide layer of described the first opening 208 bottoms 215 be removed, then form the first metal gate electrode layer 210.
The removal of the oxide layer 215 of described the first opening 208 bottoms can adopt strong acid and strong base solution repeatedly to clean, and adopts the HF acid of dilution repeatedly to clean in the embodiment of the present invention.
In a preferred embodiment of the invention, for fear of in removing the process of described the first alternative gate electrode layer 201 to described high K dielectric layer injury, described high K dielectric layer surface also is formed with dielectric barrier 206.The material of described dielectric barrier 206 is TiN or TaN, and forming technique is chemical vapour deposition technique or physical vapour deposition (PVD).
As shown in Figure 5, after removing the oxide layer 215 of described the first opening 208 bottoms, need first deposit work function layer 209 on the inwall of described the first opening 208, and then carry out metal filled, form the first metal gate electrode layer 210, its concrete technology, with reference to prior art, repeats no more here.Wherein, the material of described the first metal gate electrode layer 210 can be Al, Cu, Ag or W etc.; The material of described work function layer 209 is TiN, TaN, TiAl or Ta.
Step S104; as shown in Figure 6; described the first metal gate electrode layer 210 of planarization, described interlayer dielectric layer 204, described etching barrier layer 203 and described the second alternative gate electrode layer 202, and on described the first metal gate electrode layer 210 surfaces, form protective layer 211.
Described flatening process is the second CMP (Chemical Mechanical Polishing) process, concrete, the mechanism of described the second chemico-mechanical polishing is chemical oxidation and mechanical lapping mechanism, be abrasive material first and Metal Contact and it is carried out oxidation, thereby form oxide layer in metal surface, and then the oxide layer of utilizing the particle in abrasive material to form is got rid of.In case this layer oxide layer is removed, the chemical composition in abrasive material can continue the metal surface that oxidation is newly exposed, and then the oxide layer of utilizing the particle in abrasive material to form gets rid of, and carries out and so forth, until the planarization of described metal surface.Described in the embodiment of the present invention, the second CMP (Chemical Mechanical Polishing) process parameter depends on the circumstances according to the material of described the first metal gate electrode layer 210.
In one embodiment of the invention, described protective layer 211 is oxide layer, and it forms technique can be plasma oxidation technique or non-plasma oxygen metallization processes.The formation of protective layer described in the present embodiment 211 can be adopted non-plasma oxygen metallization processes,, as thermal oxidation, also can adopt the plasma oxygen metallization processes, and described protective layer 211 thickness of formation are 50 dusts-200 dusts.
Described plasma oxygen metallization processes is that the oxidation reactor by suitable design can change plasma density and underlayer temperature, so that at quite low temperature, and the technique of the oxide-film that on inherent metal of shorter time or semiconductor, growth thickness is suitable.When the plasma oxygen metallization processes was adopted in the formation of protective layer described in the present embodiment 211, oxidizing temperature was 20 ℃-60 ℃, and oxidation pressure is 2mTorr-100mTorr, and rf frequency is 0.5MHz-3MHz, and described processing gas is O
2Or O
3, the processing gas flow is 1sccm-1000sccm.Compared to the non-plasma oxidation technology, the technological temperature of plasma oxidation process is lower, and growth rate is higher.
In another embodiment of the present invention, described protective layer 211 is nitration case, and it forms technique can be plasma nitridation process or non-plasma nitridation process, and the thickness of the described protective layer 211 of formation is 50 dusts-200 dusts.When plasma nitridation process was adopted in the formation of protective layer described in the present embodiment 211, nitriding temperature was 100 ℃-600 ℃, and nitrogenize pressure is 0.1Torr-2Torr, and rf frequency is 0.5MHz-3MHz, and described processing gas is NO, NH
3Or NO
2, the processing gas flow is 1sccm-1000sccm.
need to prove, when forming the protective layer 211 on described the first metal gate electrode layer 210 surfaces, described the second alternative gate electrode layer 202 surfaces also likely form layer of oxide layer 212 simultaneously, but because described the first metal gate electrode layer 210 is different from the material of described the second alternative gate electrode layer 202, therefore, the protective layer 211 that is formed at described the first metal gate electrode layer 210 surfaces is not identical with the material of the oxide layer 212 that is formed at described the second alternative gate electrode layer 202 surfaces yet, thereby make when 211 pairs of described the first metal gate electrode layers 210 of described protective layer are protected, the oxide layer 212 that is formed at described the second alternative gate electrode layer 202 surfaces can't affect the etching of described the second alternative gate electrode layer 202, and together with described the second alternative gate electrode layer 202, be etched away together.
Step S105: as shown in Figure 7, remove described the first alternative gate electrode layer 202, form the second opening 213, and fill described the second opening 213, as shown in Figure 8, form the second metal gate electrode layer 214.
After described protective layer 211 forms; can adopt dry etching or wet etching to remove described the second alternative gate electrode layer 202; form the second opening 213; and on described opening inwall deposit work function layer 209; then carry out metal filled to described the second opening 213; form the second metal gate electrode layer 214, its concrete technology refer step 103, repeat here no longer in detail.
Need to prove, as shown in Figure 7, after removing described the second alternative gate electrode layer 202, can find that equally there is layer of oxide layer 215 in described the second opening 213 bottoms, therefore need to after described the second opening 213 forms, the oxide layer 215 of described the second opening 213 bottoms be cleaned.But due to this moment described the first metal gate electrode layer 210 formed,, if directly the oxide layer 215 of described the second opening 213 bottoms is cleaned, can cause certain metal loss to described the first metal gate electrode layer 210.Therefore, in the step 104 before this step 105, formed layer protective layer 211 on described the first metal gate electrode layer 210 surfaces in advance.
compared to prior art, the technical scheme that the embodiment of the present invention provides, when removing the oxide layer 215 of described the second opening 213 bottoms, described the first metal gate electrode layer 210 surfaces are formed with protective layer 211, described protective layer 211 covers described the first metal gate electrode layer 210 fully, thereby when the oxide layer 215 to described the second opening 213 bottoms is cleaned, described protective layer 211 can carry out certain protection to described the first metal gate electrode layer 210, and then minimizing is arranged in the process of described the second opening 213 bottom oxidization layer 215 in removal, the metal loss that described the first metal gate electrode layer 210 is brought.
Also need to prove, if in the situation that described the first metal gate electrode layer 210 surfaces do not have protective layer 211 to cover, described the second alternative gate electrode layer 202 is carried out in the process of etching, owing to there being plasma in dry etching, therefore, in whole etching process, be easy at described the first inner formation electrolytic cell of metal gate electrode layer 210, thereby described the first metal gate electrode layer 210 is brought certain metal loss; And the etching liquid that adopts of wet etching, not only need the second higher alternative gate electrode layer 202 and the etch rate ratio of metal, also can bring certain metal loss to described the first metal gate electrode layer 210.
And the protective layer 211 that provides in the embodiment of the present invention; in described the second alternative gate electrode layer 202 is carried out the process of etching; cover described the first metal gate electrode layer 210 fully; thereby can be in the process of removing described the second alternative gate electrode layer 202; described the first metal gate electrode layer 210 is protected; thereby avoid in the etching process of described the second alternative gate electrode layer 202 loss that described the first metal gate electrode layer 210 is brought.
Otherwise; described in prior art, the first metal gate electrode layer 210 surfaces do not have protective layer 211; but under the environment that described the first metal gate electrode layer 210 exposes; described the second alternative gate electrode layer 202 is carried out etching; clean with the oxide layer 215 to being positioned at described the second opening 213 bottoms; because etching liquid and cleaning fluid have certain Etch selectivity to metal, thereby easily cause metal loss in described the first metal gate electrode layer 210.
Step S106: described the second metal gate electrode layer 214 of planarization, described interlayer dielectric layer 204, described etching barrier layer 203 and described the first metal gate electrode layer 210.
Described flatening process is the second CMP (Chemical Mechanical Polishing) process, concrete refer step S104.
in sum, in the formation method of gate electrode layer provided by the present invention, before removing described the second alternative gate electrode layer 202, form layer protective layer 211 on described the first metal gate electrode layer 210 surfaces in advance, and described protective layer 211 covers described the first metal gate electrode layer 210 fully, thereby when described the second alternative gate electrode layer 202 is carried out etching, and while removing the oxide layer 215 of described the second opening 213 bottoms, described protective layer 211 can play certain protective effect to described the first metal gate electrode layer 210, thereby reduce in 215 two processes of oxide layer of removing described the second alternative gate electrode layer 202 and described the second opening 213 bottoms, the metal loss that described the first metal gate electrode layer 210 is brought, and then raising has the performance of the semiconductor structure of metal gate electrode layer.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention;, to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (13)
1. the method for forming semiconductor structure with metal gate electrode layer, is characterized in that, comprising:
Substrate is provided, and described substrate surface is formed with the first alternative gate electrode layer and the second alternative gate electrode layer, and the etching barrier layer that covers described the first alternative gate electrode layer and the second alternative gate electrode layer; Described etching barrier layer surface is formed with interlayer dielectric layer;
The described interlayer dielectric layer of planarization and etching barrier layer are until expose described the first alternative gate electrode layer and the second alternative gate electrode layer;
Remove described the first alternative gate electrode layer, form the first opening, and fill described the first opening, form the first metal gate electrode layer;
Described the first metal gate electrode layer of planarization, described interlayer dielectric layer, described etching barrier layer and described the second alternative gate electrode layer, and on described the first metal gate electrode layer surface, form protective layer;
Remove described the second alternative gate electrode layer, form the second opening, and fill described the second opening, form the second metal gate electrode layer;
Described the second metal gate electrode layer of planarization, described interlayer dielectric layer, described etching barrier layer and described the first metal gate electrode layer.
2. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is plasma oxidation process.
3. method for forming semiconductor structure as claimed in claim 2, is characterized in that, the processing gas in described plasma oxidation process is O
2Or O
3.
4. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is the non-plasma oxidation technology.
5. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is plasma nitridation process.
6. method for forming semiconductor structure as claimed in claim 5, is characterized in that, the processing gas in described plasma nitridation process is NO, NH
3Or NO
2.
7. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the formation technique of described protective layer is the non-plasma nitriding process.
8., as the described method for forming semiconductor structure of claim 2-7 any one, it is characterized in that, the thickness of described protective layer is 50 dusts-200 dusts.
9. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the material of described metal gate electrode layer is Al, Cu, Ag or W.
10. method for forming semiconductor structure as claimed in claim 1, is characterized in that, between described the first alternative gate electrode layer bottom and described substrate, be formed with high-K gate dielectric layer between described second grid substitutable layer and described substrate.
11. method for forming semiconductor structure as claimed in claim 10, it is characterized in that, described high-K gate dielectric layer material is hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc.
12. method for forming semiconductor structure as described in claim 10 or 11, is characterized in that, described high-K gate dielectric layer surface is formed with dielectric barrier.
13. method for forming semiconductor structure as claimed in claim 12, is characterized in that, the material of described dielectric barrier is TiN or TaN.
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| CN104766822A (en) * | 2014-01-06 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN104766822B (en) * | 2014-01-06 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN105655252A (en) * | 2014-11-10 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
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