CN106206318B - Fin type field effect transistor and preparation method thereof - Google Patents
Fin type field effect transistor and preparation method thereof Download PDFInfo
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- CN106206318B CN106206318B CN201610663545.XA CN201610663545A CN106206318B CN 106206318 B CN106206318 B CN 106206318B CN 201610663545 A CN201610663545 A CN 201610663545A CN 106206318 B CN106206318 B CN 106206318B
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- 238000002360 preparation method Methods 0.000 title claims description 26
- 238000002353 field-effect transistor method Methods 0.000 title description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 128
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 128
- 239000010703 silicon Substances 0.000 claims abstract description 128
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 116
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 116
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 80
- 238000002955 isolation Methods 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims abstract description 53
- 230000005669 field effect Effects 0.000 claims abstract description 33
- 238000011065 in-situ storage Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 49
- 239000002245 particle Substances 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 11
- 229910052735 hafnium Inorganic materials 0.000 claims description 10
- 229910003460 diamond Inorganic materials 0.000 claims description 9
- 239000010432 diamond Substances 0.000 claims description 9
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 5
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 5
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical group [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 230000007547 defect Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 230000000877 morphologic effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 238000000137 annealing Methods 0.000 description 12
- 238000002347 injection Methods 0.000 description 12
- 239000007924 injection Substances 0.000 description 12
- 239000000243 solution Substances 0.000 description 9
- -1 oxygen alkane Chemical class 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 229910003481 amorphous carbon Inorganic materials 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- 229910020696 PbZrxTi1−xO3 Inorganic materials 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229920000620 organic polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- TZHYBRCGYCPGBQ-UHFFFAOYSA-N [B].[N] Chemical compound [B].[N] TZHYBRCGYCPGBQ-UHFFFAOYSA-N 0.000 description 3
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 125000003118 aryl group Chemical group 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 229910052726 zirconium Inorganic materials 0.000 description 3
- 229910015890 BF2 Inorganic materials 0.000 description 2
- 229910052693 Europium Inorganic materials 0.000 description 2
- 229910005898 GeSn Inorganic materials 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000012190 activator Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052747 lanthanoid Inorganic materials 0.000 description 2
- 150000002602 lanthanoids Chemical class 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052702 rhenium Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 229910016285 MxNy Inorganic materials 0.000 description 1
- 229910016310 MxSiy Inorganic materials 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002000 scavenging effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000013268 sustained release Methods 0.000 description 1
- 239000012730 sustained-release form Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- BJAARRARQJZURR-UHFFFAOYSA-N trimethylazanium;hydroxide Chemical compound O.CN(C)C BJAARRARQJZURR-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Abstract
When the FinFET device is manufactured by the fin field effect transistor manufacturing method, a silicon fin part and an isolation part are formed firstly, and then the silicon fin part is etched in situ to form a reserved space for a silicon germanium fin and a germanium fin; and finally, sequentially forming a silicon germanium fin and a germanium fin through epitaxial growth. Because the silicon germanium fin is between the silicon substrate and the germanium fin, the effect of a strain buffer layer is achieved, and the lattice mismatch degree between germanium and silicon is reduced, so that a precondition is established for the formation of the germanium fin, the situation that germanium materials are directly filled into small-size gaps between isolation parts, the gaps cannot be filled with the germanium materials, the germanium fins have morphological defects, and then the situation that the reliability of the FinFET device is reduced is avoided.
Description
Technical field
The application designing semiconductor device technical field, more specifically to a kind of fin formula field effect transistor and its
Preparation method.
Background technique
In order to meet the needs of electronic equipment is increasingly miniaturized, the size of semiconductor devices constantly reduces, fin field effect
The appearance of transistor (Fin Field-Effect Transisitor, FinFET) solves traditional complementary metal-oxide
Go out when semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistor is below 20nm thread
The processing procedure of semiconductor devices has really been brought into 20nm thread or less and led by the leakage phenomenon between existing source electrode and drain electrode
Domain provides new direction for the miniaturization of semiconductor devices.
The structure of FinFET is as shown in Figure 1, comprising: multiple fins 11 positioned at 10 surface of silicon substrate are located at adjacent
The fin 11 between isolation part (not shown in figure 1)；Positioned at the fin away from the silicon substrate side source region 12,
Channel region 13 and drain region 14, the channel region 13 is between the source region 12 and drain region 14；Deviate from institute positioned at the fin 11
The gate structure 20 of 10 1 side surface of silicon substrate is stated, the germanium fin 11 of the gate structure 20 towards 10 side of silicon substrate is institute
Channel region 13 is stated, the gate structure two sides are located at, covers the side wall 30 and the covering fin of the gate structure side
11, the interlayer dielectric layer 40 of isolation part side and top surface and 30 side of the side wall.
The material of the fin 11 in the prior art is usually identical as the silicon substrate 10, is body silicon or silicon-on-insulator
Etc. common semiconductor silicon sill.Studies have found that the fin 11 is higher using electron mobility and hole mobility
Material, such as germanium (electron mobility 3900cm2/ Vs, hole mobility 1900cm2/ Vs), preparation will be big
The carrier mobility of big enhancing FinFET so that using the FinFET integrated circuit response speed more
Fastly.
But due to lattice mismatch issue existing between germanium and silicon, small size device is being formed, especially forming line
When journey is in 20nm FinFET below, the defect as existing for lattice mismatch can make extension in silicon at germanium and silicon interface
Germanium fin existing forms defect on substrate, so that the problem of reliability decrease occurs in the FinFET of preparation.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of fin formula field effect transistor and preparation method thereof, with solution
Certainly make the anomalad occurred when preparing fin using germanium due to lattice defect, so that the FinFET of preparation goes out
The problem of existing reliability decrease.
In order to solve the above technical problems, the embodiment of the invention provides following technical solutions:
A kind of preparation method of fin formula field effect transistor, comprising:
Silicon substrate is provided, the surface of silicon has multiple discrete silicon fin portions；
Isolation part, the height phase of the isolation part height and the silicon fin portion are formed between the adjacent silicon fin portion
Together；
The silicon fin portion is removed using etching method；
Epitaxial growth SiGe in gap between the isolation part forms SiGe fin, and in epitaxial process
It is in situ to etch the SiGe fin, so that the height of the SiGe fin is less than the height of the isolation part；
In SiGe fin surface epitaxial growth Ge, germanium fin is formed, the germanium fin is concordant with the isolation part, the germanium fin
It is referred to as fin with the SiGe fin；
The isolation part is thinned, the germanium fin is exposed；
The dummy structure of at least one germanium fin is developed across away from one side surface of silicon substrate in the isolation part,
The dummy structure covers atop part surface and the sidewall surfaces of the germanium fin, is located at the dummy structure and serves as a contrast towards the silicon
The germanium fin of bottom side is channel region；
Side wall is formed in the dummy structure two sides, the side wall covers the side of the dummy structure；
Inside the fin, the channel region two sides form source region and drain region；
Form the interlayer dielectric layer for covering the fin, isolation part side and top surface and the side wall side；
The dummy structure is removed using rear grid technique, forms gate structure.
Preferably, the material for preparing of the SiGe fin is Si1-xGex, wherein the value range of x is 0-0.7, including endpoint
Value.
Preferably, described that the isolation part is thinned, it is described to deviate from the isolation part after the germanium fin is exposed
One side surface of silicon substrate is developed across before the dummy structure of at least one germanium fin further include:
The SiGe fin close to germanium fin one end inject the first default particle, formed be located at the SiGe fin with it is described
Break-through stop-layer between germanium fin.
Preferably, described inside the fin, after channel region two sides formation source region and drain region, the formation is covered
It covers before the interlayer dielectric layer of the fin, isolation part side and top surface and the side wall side further include:
Inside the source region and drain region inject the second default particle, formed be located at the germanium fin at the top of lifting source region and
It is lifted drain region.
Preferably, when the fin formula field effect transistor of preparation is N-type device, the second default particle is germanium
Silicon；
When the fin formula field effect transistor of preparation is P-type device, the second default particle is tin germanium.
Preferably, the lifting source region and the shape in lifting drain region are diamond shape or brilliant.
Preferably, described to include: using the etching method removal silicon fin portion
The silicon fin portion is removed using wet etching, and is formed in the surface of silicon and is directed toward the silicon substrate side
Sharp slot.
Preferably, described to remove the dummy structure using rear grid technique, forming gate structure includes:
The dummy structure is removed, gate openings are left；
Hafnium is deposited in the gate openings, forms gate dielectric layer；
Conductive material is deposited in the gate dielectric layer surface, forms grid.
A kind of fin formula field effect transistor, comprising:
Positioned at multiple fins of the surface of silicon, the fin include positioned at the surface of silicon SiGe fin with
And deviate from the germanium fin of one side surface of silicon substrate positioned at the SiGe fin；
Isolation part between the adjacent fin；
Deviate from the source region, channel region and drain region of described silicon substrate one end inside the germanium fin, the channel region is located at
Between the source region and drain region；
Deviate from the gate structure of one side surface of silicon substrate positioned at the germanium fin, the gate structure is across at least one
The germanium fin, covers atop part surface and the sidewall surfaces of the germanium fin, and the gate structure is towards the silicon substrate side
Germanium fin be the channel region；
Positioned at the gate structure two sides, the side wall of the gate structure side is covered；
Cover the interlayer dielectric layer of the germanium fin, isolation part side and top surface and the side wall side.
Preferably, the material of the SiGe fin is Si1-xGex, wherein the value range of x is 0-0.7, including endpoint value.
Preferably, further includes:
Break-through stop-layer between the SiGe fin and the germanium fin, the break-through stop-layer is by the SiGe
Fin injects the first default particle and is formed.
It preferably, further include positioned at the fin away from the lifting source region of described silicon substrate one end and lifting drain region, it is described
Lifting source region and lifting drain region are formed by injecting the second default particle to the germanium fin.
Preferably, when the fin formula field effect transistor is P-type device, the second default particle is tin germanium；
When the fin formula field effect transistor is N-type device, the second default particle is SiGe.
Preferably, the lifting source region and the shape in lifting drain region are diamond shape or brilliant.
Preferably, the SiGe fin has the raised structures extended to the silicon substrate direction.
Preferably, the gate structure includes:
Deviate from the gate dielectric layer of one side surface of silicon substrate positioned at the channel region；
Deviate from the grid of one side surface of silicon substrate positioned at the gate dielectric layer.
It can be seen from the above technical proposal that the embodiment of the invention provides a kind of fin formula field effect transistor and its preparations
Method, wherein when preparing FinFET using the preparation method of the fin formula field effect transistor, with multiple discrete
The substrate surface in silicon fin portion is initially formed the isolation part, then using etching method remove the silicon fin portion with the isolation part it
Between form multiple gaps；Epitaxial growth SiGe in gap between the isolation part forms SiGe fin, and in epitaxial growth
It is in situ in the process to etch the SiGe fin, so that the height of the SiGe fin is less than the height of the isolation part, is the germanium fin
Grow reserved space；Finally in SiGe fin surface epitaxial growth Ge, germanium fin is formed.Since the SiGe fin is served as a contrast in the silicon
Between bottom and the germanium fin, play the role of strained buffer layer, reduces the lattice mismatch degree between germanium and silicon, to be
Precondition is established in the formation of germanium fin, avoids directly occurring in small size gap that germanium material is inserted between the isolation part
Gap can not be filled up and make germanium fin existing forms defect by germanium, so that the case where reliability decrease occurs in FinFET
Occur.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the schematic diagram of the section structure of fin formula field effect transistor in the prior art；
Fig. 2 is a kind of production process schematic diagram for fin formula field effect transistor that one embodiment of the application provides；
Fig. 3-15,17-19 and 21-25 are the knot of the manufacturing process of fin formula field effect transistor provided by the embodiments of the present application
Structure schematic diagram；
Figure 16 is a kind of production process signal for fin formula field effect transistor that the preferred embodiment of the application provides
Figure；
Figure 20 is that a kind of production process for fin formula field effect transistor that another preferred embodiment of the application provides shows
It is intended to；
Figure 26 is a kind of structural schematic diagram for fin formula field effect transistor that one embodiment of the application provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present application provides a kind of preparation method of fin formula field effect transistor, as shown in Figure 2, comprising:
S101: providing silicon substrate, and the surface of silicon has multiple discrete silicon fin portions.
Specifically, the forming process of the silicon substrate includes:
As shown in figure 3, forming mask graph PR on one piece of smooth surface initial substrate N0.The material of the initial substrate N0
Matter can be the common semiconductor silicon-based substrate such as body silicon or silicon-on-insulator.The mask graph PR can use spin coating or spray
It applies or the techniques such as silk-screen printing or vapor deposition (Chemical Vapor Deposition, CVD) is formed, the mask graph
PR can be the soft exposure mask of photoresist, can also be the hard of nitride or oxide or its stacked structure (such as ONO structure)
Matter exposure mask, the application to the specific type of the initial substrate N0 and the specific type of the mask pattern PR and without limitation,
Specifically depending on actual conditions.
As shown in figure 4, etching the initial substrate N0 using the mask graph PR as exposure mask, formed with multiple discrete
Silicon fin portion 101 silicon substrate 100.Anisotropic etching side is preferably used to the technique that the initial substrate N0 is performed etching
Method for example, by using fluorine-based dry plasma etch, reactive ion etching (Reactive Ion Etching, RIE), or uses
Tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) wet etching.Preferably, etching parameters are controlled, so that the silicon fin
The depth-to-width ratio in portion 101 is greater than 5:1 and preferably greater than 10:1.
S102: isolation part, the isolation part height and the silicon fin portion are formed between the adjacent silicon fin portion 101
101 height is identical.
Specifically, as shown in figure 5, fill insulant forms isolation structure between the silicon fin portion 101.Before this
It also needs using dry process such as plasma etching, ashing or using the wet processing of oxidant and acid solution mixture removal institute
State mask graph.Then high-aspect-ratio depositing operation (HARP), high density plasma chemical vapor deposition technique are used
(HDPCVD) or flowable chemical gas-phase deposition (flowable CVD) is filled out in groove between the silicon fin portion 101
It fills insulating materials and forms the isolation structure.Formed the isolation structure insulating materials can for silica, silicon oxynitride or
Person's low-K material, wherein the low-K material includes but is not limited to that organic low-K material is (such as organic poly- containing aryl or polynary ring
Close object), it is inorganic low-K material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG and BPSG), more
Hole low-K material (such as two silicon, three oxygen alkane (SSQ) base porous low-k materials, porous silica, porous SiOCH, mix C titanium dioxide
Silicon mixes the porous amorphous carbon of F, porous diamond and porous organic polymer).
In this process, due to the silicon fin portion 101, relative to the silicon substrate 100, there are protrusions, so that formed
The top of isolation structure also has corresponding protrusion in the top corresponding position in the silicon fin portion 101.
As shown in fig. 6, flatening process is executed to the isolation structure, until exposing the top in the silicon fin portion 101.
The flatening process can be chemically mechanical polishing (Chemical Mechanical Polish, CMP) technique either needle
Execute return carving technology (etch-back) to the Etch selectivity in the isolation part STI and the silicon fin portion 101, stays in institute
It states the isolation structure between silicon fin portion 101 and constitutes the isolation part STI of FinFET, also referred to as shallow trench isolation.
S103: the silicon fin portion 101 is removed using etching method.
As shown in fig. 7, selective etch removes the silicon fin portion 101.It is preferred that using anisotropic etching technics.At this
In one preferred embodiment of application, the silicon fin portion 101 is removed preferably by wet etching, and in the surface of silicon shape
At the sharp slot 100A for being directed toward the silicon substrate side.Specifically, the process that the silicon fin portion 101 is removed using wet etching
Include:
The silicon fin portion 101 is cleaned using diluted hydrofluoric acid solution；
Continue to etch the silicon fin portion 101 using the alkaline corrosion liquid of diluted trimethylammonium hydroxide (dTMAH), until
Form the sharp slot 100A for being directed toward the silicon substrate side.
It is primary that 101 surface of silicon fin portion is removed using the purpose that diluted hydrofluoric acid solution cleans the silicon fin portion 101
Etch selectivity and rate of the oxide when being performed etching using dTMAH to the silicon fin portion 101 with improving.It is described diluted
Hydrofluoric acid solution can be the hydrofluoric acid solution of 100:1, can be 30s, the application couple to the scavenging period in the silicon fin portion 101
This and without limitation, specifically depending on actual conditions.
The point slot 100A be formed as dTMAH for each crystal orientation of the silicon substrate 100 corrosion rate not
Together, wherein dTMAH is minimum for the corrosion rate of (111) crystal orientation of the silicon substrate 100, therefore can the silicon substrate 100 again
The middle inclined sharp slot 100A formed along (111) crystal orientation.The depth of point slot 100A only 1-5nm.
S104: epitaxial growth SiGe in the gap between the isolation part STI forms SiGe fin, and raw in extension
The SiGe fin is etched in growth process in situ, the height of the SiGe fin is made to be less than the height of the isolation part STI.
Specifically, as shown in figure 8, the SiGe that epitaxial growth SiGe is formed in gap between the isolation part STI
Fin 200 can exceed the isolation part STI, likewise, as shown in figure 9, being needed at this time using to the silicon for exceeding the isolation part STI
Germanium fin 200 executes flatening process, until the height of the SiGe fin 200 is identical as the isolation part STI, the flat chemical industry
Skill can be chemically mechanical polishing (Chemical Mechanical Polish, CMP) technique or be directed to the isolation part
The Etch selectivity of STI and the SiGe fin 200 and execute return carving technology (etch-back)；Then, as shown in Figure 10, exist
The SiGe fin 200 is etched during epitaxial growth SiGe in situ, the height of the SiGe fin 200 is made to be less than the isolation
The height of portion STI, for epitaxial growth Ge fin reserved space.
In one embodiment of the application, the etching SiGe fin 200 in situ can use diluted hydrochloric acid solution pair
It is performed etching, but can also be performed etching using other acid or alkaline solutions to it.The application etches the silicon in situ
The concrete mode and without limitation that germanium fin 200 uses is specific depending on actual conditions.
In this application, since the SiGe fin 200 is between the silicon substrate 100 and the germanium fin, strain is played
The effect of buffer layer reduces the lattice mismatch degree between germanium and silicon, so that precondition is established in the formation for germanium fin, avoids
Directly by small size gap that germanium material is inserted between the isolation part STI and germanium occur can not fill up gap and make germanium
Fin existing forms defect, so that the appearance of the case where reliability decrease occurs in FinFET.
On the basis of the above embodiments, in the specific embodiment of the application, the material of the SiGe fin 200 is
Si1-xGex, wherein the value range of x is 0-0.7, including endpoint value.But the application is to the specific value of x and without limitation, tool
Depending on stereoscopic actual conditions.
S105: in the 200 surface epitaxial growth Ge of SiGe fin, germanium fin is formed, the germanium fin and the isolation part STI are flat
Together, the germanium fin and the SiGe fin 200 are referred to as fin.
Likewise, as shown in figure 11, also can during the 200 surface epitaxial growth Ge of SiGe fin forms germanium fin
Occur occurring the part beyond the isolation part STI such as the SiGe fin 200, needs to exceeding the isolation part STI
300 part of germanium fin executes flatening process, so that the germanium fin 300 is concordant with the isolation part STI, as shown in figure 12.
As shown in table 1, germanium material has highest hole mobility and higher electron mobility, if using germanium material
Material is used as the fin, then the carrier mobility of FinFET can be greatly enhanced, so that using the FinFET device
The response speed of the integrated circuit of part is faster.
The substrate strain parameter of 1 different materials of table
S106: being thinned the isolation part STI, and the germanium fin 300 is exposed.
As shown in figure 13, the isolation part STI is thinned using shallow trench oxide thinning method, exposes the germanium fin 300
Partial sidewall.In the other embodiments of the application, anisotropic dry etch process can also be used, or using diluted
Hydrofluoric acid or diluted sustained release etching agent wet etching carry out the isolation part STI thinned.The height of the germanium fin 300 exposed
Degree can be depending on surrounding the pattern demand of grid in FinFET.
S107: at least one described germanium fin is developed across away from 100 1 side surface of silicon substrate in the isolation part STI
300 dummy structure, the dummy structure cover atop part surface and the sidewall surfaces of the germanium fin 300, are located at the vacation
The germanium fin 300 of grid structure towards the silicon substrate side is channel region.
As shown in figure 14, at least one institute is developed across away from 100 1 side surface of silicon substrate in the isolation part STI
The false grid layer structure of germanium fin 300 is stated, the vacation grid layer structure is including vacation gate dielectric layer 400A and is located at the false gate medium
Layer 400A deviates from the false grid 400B of the side the isolation part STI.The formation of the vacation grid layer structure can be with using plasma
Enhance chemical vapour deposition technique (Plasma Enhanced ChemicalVapor Deposition, PECVD) or high density etc.
Gas ions chemical vapour deposition technique (HDPCVD) or molecular beam epitaxy (Molecular Beam Epitaxy, MBE) or atomic layer
Deposit (Atomic layer deposition, ALD) or the techniques such as the oxidation of thermal evaporation fire or magnetron sputtering.The one of the application
In a preferred embodiment, it is described vacation grid layer structure preferably across all germanium fins 300, but the application other implementation
In example, the vacation grid layer structure 400A can also across the 1 or 2 germanium fin 300, the application to this and without limitation,
Specifically depending on actual conditions.
As shown in figure 15, Figure 15 is the top view of Figure 14, is patterned to the false grid layer structure, forms the vacation
Grid structure 400, the dummy structure 400 cover atop part surface and the sidewall surfaces of the germanium fin 300, are located at the false grid
The germanium fin 300 of structure 400 towards the silicon substrate side is channel region；Likewise, the dummy structure 400 includes false gate medium
The layer 400A and false grid 400B for deviating from mono- side surface isolation part STI positioned at the vacation gate dielectric layer 400A, the vacation grid are situated between
The material of matter layer 400A can be silica, and the material of the vacation grid 400B can be polysilicon or amorphous silicon or microcrystal silicon or more
The material selection of brilliant germanium or amorphous germanium or amorphous carbon etc., the vacation gate dielectric layer 400A and false grid 400B with improve with surrounding other
The Etch selectivity of material.
On the basis of the above embodiments, in the preferred embodiment of the application, as shown in figure 16, the thinned institute
Isolation part STI is stated, it is described to deviate from the silicon substrate 100 1 in the isolation part STI after the germanium fin 300 is exposed
Side surface is developed across before the dummy structure 400 of at least one germanium fin 300 further include:
S1067: the first default particle is injected close to described 300 one end of germanium fin in the SiGe fin 200, is formed described in being located at
Break-through stop-layer between SiGe fin 200 and the germanium fin 300.
Specifically, as shown in figure 17, the first default particle is injected close to described 300 one end of germanium fin in the SiGe fin 200
Can using the injection of vertical and/or angle-tilt ion, with after annealing activator impurity, formed with usually intrinsic 200 material of SiGe fin,
Doping type break-through the stop-layer 200A, the break-through stop-layer 200A different with concentration are for inhibiting to reduce FinFET along vertical
The leakage current in 100 direction of silicon substrate.In one embodiment of the application, for the FinFET of N-type, described first is pre-
If particle can be the dopants such as B or In or BF2, for the FinFET of p-type, the first default particle can be As or P etc.
Dopant.In another embodiment of the application, the first default particle can also be that C or N or O etc. are easy and the silicon
The doping particle that germanium fin 200 chemically reacts, using (such as 600 DEG C -900 DEG C, including endpoint of high annealing after injection
Value) to adulterate particle and reacts to form insulator (such as oxide or nitride or carbide with the material of the SiGe fin 200
Deng), pass through the leakage path between the insulator partition of formation and the silicon substrate 100.It can also be by adjusting the agent of injection
Amount, energy, angle and annealing temperature, the position for the break-through stop-layer 200A that rationally control is formed.
S108: side wall is formed in 400 two sides of dummy structure, the side wall covers the side of the dummy structure 400.
Specifically, as shown in figure 18, silica or silicon oxynitride or class first are formed using techniques such as PECVD, magnetron sputterings
The insulating dielectric materials such as diamond film (DLC), then using anisotropic etching technics removal horizontal component (B- in attached drawing 18
The direction B) and only retain the insulating dielectric materials to be formed in 400 two sides of dummy structure, form the side wall 500.
S109: inside the fin, the channel region two sides form source region and drain region.
Specifically, the lightly-doped source drain region (source including LDD structure is formed in the fin portion surface, the channel region two sides
Area 300S and drain region 300D).For p-type FinFET, the lightly-doped source drain region passes through injection B or In or BF2Deng doping
It activates to be formed using techniques such as spike annealing, short annealings after agent, for N-type FinFET, the lightly-doped source drain region is logical
It activates to be formed using techniques such as spike annealing, short annealings after crossing the dopants such as injection As or P.It mixes in the lightly-doped source drain region
Miscellany type is opposite with the break-through stop-layer 200A.
Then the top in the lightly-doped source drain region, the native oxide in removal injection, annealing process are cleaned.Finally lead to
Raising dopant dosage is crossed, the particle types of injection are identical as LDD structure, form source region 300S and drain region as shown in figure 19
300D。
On the basis of the above embodiments, as shown in figure 20, described in institute in another preferred embodiment of the application
State that fin is internal, the channel region two sides are formed after source region 300S and drain region 300D further include:
S1091: injecting the second default particle inside the source region 300S and drain region 300D, is formed and is located at the germanium fin
The lifting source region at 300 tops and lifting drain region.
Specifically, as shown in figure 21, it before injecting the second default particle inside the source region 300S and drain region 300D, needs
It to be injected using the top in lightly-doped source drain region described in the solvent cleans such as diluted hydrofluoric acid, removal, is in annealing process primary
Oxide.Then grain is preset using the epitaxial growth second on the source region 300S or drain region 300D of selective epitaxial growth technology
The lifting source region HS and lifting drain region HD of sub- material, and at the same time foring high concentration using doping techniques in situ.For N-type
FinFET, the second default particle are SiGe or SiGeC or SiC；For p-type FinFET, the second default particle is
GeSn.The lifting source region HS can be different to the channel layer application for being located at 400 lower section of dummy structure with lifting drain region HD
Stress, to effectively increase the channel region carrier mobility, and then increase the response speed of the FinFET.
Figure 22 is the cross-sectional view along the line B-B direction of Figure 21；In Figure 22, the lifting source region HS is with lifting drain region HD's
Shape is diamond shape or brilliant.
S110: it is formed and covers the fin, the interlayer of 500 side of the isolation part side STI and top surface and the side wall is situated between
Matter layer.
Figure 23 is cross-sectional view of the Figure 21 along line A-A, and the interlayer dielectric layer (ILD) is using spin coating or spraying or silk-screen printing
Or the techniques such as DVD form the ILD of low-K material, including but not limited to organic low-K material (such as having containing aryl or polynary ring
Machine polymer), inorganic low-K material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG),
Porous low-k materials (such as two silicon, three oxygen alkane (SSQ) base porous low-k materials, porous silica, porous SiOCH, mix C titanium dioxide
Silicon mixes the porous amorphous carbon of F, porous diamond, porous organic polymer).Preferably, using CMP process planarization ILD until
400 top of dummy structure is exposed, interlayer dielectric layer as of fig. 24 is formed.
S111: the dummy structure 400 is removed using rear grid technique, forms gate structure.
Described to remove the dummy structure 400 using rear grid technique such as Figure 25, forming gate structure includes:
The dummy structure 400 is removed, gate openings are left；
Hafnium is deposited in the gate openings, forms gate dielectric layer 600A；
Conductive material is deposited in the gate dielectric layer surface, forms grid 600B.
Depositing technique used by hafnium and conductive material can be HDPCVD or MOCVD or MBE or ALD.The height
K material includes but is not limited to nitride (such as SiN, AlN, TiN), metal oxide (predominantly subgroup and lanthanide element
Oxide, such as MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3), nitrogen oxides (such as
HfSiON)；Perovskite Phase oxide (such as PbZrxTi1-xO3 (PZT), BaxSr1-xTiO3 (BST)).The material of the grid
Material include but is not limited to polysilicon, poly-SiGe or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re,
The nitridation of the alloy and these metals of the metal simple-substances such as Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals
Object, can also be doped with elements such as C, F, N, O, B, P, As to adjust work function in the grid 600B.
On the basis of the above embodiments, in the preferred embodiment of the application, the gate dielectric layer and grid
Between the barrier layer of nitride is further preferably formed by the conventional methods such as PVD, CVD, ALD, barrier layer material is MxNy、MxSiyNz、
MxAlyNz、MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.It is highly preferred that the grid and barrier layer
, can also be using the injection doped layer structure mixed not only with lamination layer structure stacked up and down, namely constitute the grid
It is deposited on the gate dielectric layer simultaneously with the material on barrier layer, therefore the grid 600B includes the material on above-mentioned barrier layer
Material.Later, further etching ILD forms the exposure lifting source region HS and is lifted the contact hole of drain region HD, fills out in contact hole
It fills the metals such as W, Al, Cu, Ti, Ta, Mo, metal alloy, metal nitride etc. and forms contact plug.And further preferably herein it
The preceding nickel based metal silicide that formed in contact hole is to reduce contact resistance.
Correspondingly, the embodiment of the present application also provides a kind of fin formula field effect transistors, as shown in figure 26, comprising:
Multiple fins positioned at 100 surface of silicon substrate, the fin include the silicon positioned at 100 surface of silicon substrate
Germanium fin 200 and the germanium fin 300 for deviating from 100 1 side surface of silicon substrate positioned at the SiGe fin 200；
Isolation part between the adjacent fin；
Inside the germanium fin 300 (in attached drawing 26 not away from the source region 300S of described 100 one end of silicon substrate, channel region
Mark) and drain region 300D, the channel region is between the source region 300S and drain region 300D；
Deviate from the gate structure of 100 1 side surface of silicon substrate positioned at the germanium fin 300, the gate structure is across extremely
A few germanium fin 300, covers atop part surface and the sidewall surfaces of the germanium fin 300, and the gate structure is towards institute
The germanium fin 300 for stating 100 side of silicon substrate is the channel region；
Positioned at the gate structure two sides, the side wall 500 of the gate structure side is covered；
Cover the interlayer dielectric layer ILD of the germanium fin 300, isolation part side and top surface and 500 side of the side wall.
Since the SiGe fin 200 is between the silicon substrate 100 and the germanium fin 300, strained buffer layer is played
Effect, reduces the lattice mismatch degree between germanium and silicon, so that precondition is established in the formation for germanium fin 300, avoids directly
By in small size gap that germanium material is inserted between the isolation part STI and germanium occur can not fill up gap and make germanium fin
300 existing forms defects, so that the appearance of the case where reliability decrease occurs in FinFET.
It should be noted that the interlayer dielectric layer ILD (ILD) is using spin coating or spraying or the works such as silk-screen printing or DVD
The ILD of skill formation low-K material, including but not limited to organic low-K material (such as organic polymer containing aryl or polynary ring),
Inorganic low-K material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low-K material
Material (such as two silicon, three oxygen alkane (SSQ) base porous low-k materials, porous silica, porous SiOCH, mix that C silica, to mix F more
Hole amorphous carbon, porous diamond, porous organic polymer).
It should also be noted that, specifically, the gate structure includes: positioned at the channel region away from the silicon substrate
The gate dielectric layer 600A of 100 1 side surfaces；
Deviate from the grid 600B of 100 1 side surface of silicon substrate positioned at the gate dielectric layer.
The gate dielectric layer 600A is formed by depositing hafnium, and the grid 600B passes through deposition conductive material shape
At depositing technique used by hafnium and conductive material can be HDPCVD or MOCVD or MBE or ALD.The hafnium
Including but not limited to nitride (such as SiN, AlN, TiN), metal oxide (predominantly subgroup and lanthanide element oxidation
Object, such as MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3), nitrogen oxides (such as
HfSiON)；Perovskite Phase oxide (such as PbZrxTi1-xO3 (PZT), BaxSr1-xTiO3 (BST)).The material of the grid
Material include but is not limited to polysilicon, poly-SiGe or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re,
The nitridation of the alloy and these metals of the metal simple-substances such as Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals
Object, can also be doped with elements such as C, F, N, O, B, P, As to adjust work function in the grid.
On the basis of the above embodiments, in the specific embodiment of the application, the material of the SiGe fin 200 is
Si1-xGex, wherein the value range of x is 0-0.7, including endpoint value.But the application is to the specific value of x and without limitation, tool
Depending on stereoscopic actual conditions.
On the basis of the above embodiments, in another embodiment of the application, the SiGe fin 200 has to described
The raised structures that 100 direction of silicon substrate extends.
This raised structures make the SiGe fin 200 reduce in epitaxial process with the silicon substrate 100 it
Between lattice mismatch, keep the pattern of the SiGe fin 200 better.
On the basis of the above embodiments, in the preferred embodiment of the application, as shown in figure 25, the fin field
Effect transistor further include:
Break-through stop-layer between the SiGe fin 200 and the germanium fin 300, the break-through stop-layer is by institute
The the first default particle of injection of SiGe fin 200 is stated to be formed.
Specifically, injecting the first default particle close to described 300 one end of germanium fin in the SiGe fin 200 can be using vertical
And/or angle-tilt ion injection is formed and usual intrinsic 200 material of SiGe fin, doping type and dense with after annealing activator impurity
Different break-through stop-layers is spent, the break-through stop-layer is used to inhibit to reduce FinFET along vertical 100 direction of silicon substrate
Leakage current.In one embodiment of the application, for the FinFET of N-type, the first default particle can be B or In or
The dopants such as BF2, for the FinFET of p-type, the first default particle can be the dopants such as As or P.In the another of the application
In one embodiment, the first default particle can also be that C or N or O etc. are easy to chemically react with the SiGe fin 200
Doping particle, after injection using high annealing (such as 600 DEG C -900 DEG C, including endpoint value) to adulterate particle with it is described
The material of SiGe fin 200 reacts to form insulator (such as oxide or nitride or carbide etc.), passes through the insulator of formation
Leakage path between partition and the silicon substrate 100.It can also be by adjusting the dosage of injection, energy, angle and annealing
Temperature, the position for the break-through stop-layer that rationally control is formed.
On the basis of the above embodiments, in another preferred embodiment of the application, as shown in figure 25, the fin
Field effect transistor further include:
Positioned at the fin away from the lifting source region HS of described 100 one end of silicon substrate and lifting drain region HD, the lifting source
Area HS and lifting drain region HD is formed by injecting the second default particle to the germanium fin 300.
It should be noted that the lifting source region HS and lifting drain region HD can be to positioned at 400 lower section of dummy structure
Channel layer apply different stress, to effectively increase the channel region carrier mobility, and then described in increasing
The response speed of FinFET.
It should also be noted that, the second default particle is SiGe or SiGeC or SiC for N-type FinFET；For P
Type FinFET, the second default particle are GeSn.The application to the specific type of the described second default particle and without limitation,
Specifically depending on actual conditions.
As shown in figure 22, the shape of the lifting source region HS and lifting drain region HD are diamond shape or brilliant.
In conclusion the embodiment of the present application provides a kind of fin formula field effect transistor and preparation method thereof, wherein utilize
When the preparation method of the fin formula field effect transistor prepares FinFET, in the silicon substrate with multiple discrete silicon fin portions
100 surfaces are initially formed the isolation part, and it is more to be formed between the isolation part then to remove the silicon fin portion using etching method
A gap；Epitaxial growth SiGe in gap between the isolation part forms SiGe fin 200, and in epitaxial process
The middle etching SiGe fin 200 in situ, makes the height of the SiGe fin 200 be less than the height of the isolation part, is the germanium fin
300 growth reserved space；Finally in the 200 surface epitaxial growth Ge of SiGe fin, germanium fin 300 is formed.Due to the SiGe
Fin 200 plays the role of strained buffer layer, reduces between germanium and silicon between the silicon substrate 100 and the germanium fin 300
Lattice mismatch degree to establish precondition for the formation of germanium fin 300 avoid that germanium material is directly inserted the isolation part
Between small size gap in and germanium occur can not fill up gap and make 300 existing forms defect of germanium fin so that
There is the appearance of the case where reliability decrease in FinFET.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of preparation method of fin formula field effect transistor characterized by comprising
Silicon substrate is provided, the surface of silicon has multiple discrete silicon fin portions；
Isolation part is formed between the adjacent silicon fin portion, the isolation part height is identical as the height in the silicon fin portion；
The silicon fin portion is removed using etching method；
Epitaxial growth SiGe in gap between the isolation part forms SiGe fin, and in situ in epitaxial process
The SiGe fin is etched, the height of the SiGe fin is made to be less than the height of the isolation part；
In SiGe fin surface epitaxial growth Ge, germanium fin is formed, the germanium fin is concordant with the isolation part, the germanium fin and institute
It states SiGe fin and is referred to as fin；
The isolation part is thinned, the germanium fin is exposed；
The dummy structure of at least one germanium fin is developed across away from one side surface of silicon substrate in the isolation part, it is described
Dummy structure covers atop part surface and the sidewall surfaces of the germanium fin, is located at the dummy structure towards the silicon substrate one
The germanium fin of side is channel region；
Side wall is formed in the dummy structure two sides, the side wall covers the side of the dummy structure；
Inside the fin, the channel region two sides form source region and drain region；
Form the interlayer dielectric layer for covering the fin, isolation part side and top surface and the side wall side；
The dummy structure is removed using rear grid technique, forms gate structure.
2. the preparation method of fin formula field effect transistor according to claim 1, which is characterized in that the system of the SiGe fin
Standby material is Si1-xGex, wherein the value range of x is 0-0.7, including endpoint value.
3. the preparation method of fin formula field effect transistor according to claim 1, which is characterized in that it is described be thinned it is described every
From portion, after the germanium fin is exposed, it is described the isolation part away from one side surface of silicon substrate be developed across to
Before the dummy structure of a few germanium fin further include:
The first default particle is injected close to germanium fin one end in the SiGe fin, is formed and is located at the SiGe fin and the germanium fin
Between break-through stop-layer.
4. the preparation method of fin formula field effect transistor according to claim 1, which is characterized in that described in the fin
Internal, described channel region two sides are formed after source region and drain region, the is formationed covering fin, isolation part side and top surface with
And before the interlayer dielectric layer of the side wall side further include:
The second default particle is injected inside the source region and drain region, forms the lifting source region and lifting being located at the top of the germanium fin
Drain region.
5. the preparation method of fin formula field effect transistor according to claim 4, which is characterized in that when the fin of preparation
When formula field effect transistor is N-type device, the second default particle is SiGe；
When the fin formula field effect transistor of preparation is P-type device, the second default particle is tin germanium.
6. the preparation method of fin formula field effect transistor according to claim 4, which is characterized in that the lifting source region and
The shape for being lifted drain region is diamond shape or hexagon.
7. the preparation method of fin formula field effect transistor according to claim 1, which is characterized in that described to utilize etching method
Removing the silicon fin portion includes:
The silicon fin portion is removed using wet etching, and forms the point for being directed toward the silicon substrate side in the surface of silicon
Slot.
8. the preparation method of fin formula field effect transistor according to claim 1, which is characterized in that described to use rear grid work
Skill removes the dummy structure, forms gate structure and includes:
The dummy structure is removed, gate openings are left；
Hafnium is deposited in the gate openings, forms gate dielectric layer；
Conductive material is deposited in the gate dielectric layer surface, forms grid.
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| US20080073667A1 (en) * | 2006-09-27 | 2008-03-27 | Amberwave Systems Corporation | Tri-gate field-effect transistors formed by aspect ratio trapping |
| CN103140930A (en) * | 2010-09-24 | 2013-06-05 | 英特尔公司 | Non-planar quantum well device having interfacial layer and method of forming same |
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| CN105244379A (en) * | 2014-07-10 | 2016-01-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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