CN107968122B - Fin type field effect transistor and preparation method thereof - Google Patents

Fin type field effect transistor and preparation method thereof Download PDF

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CN107968122B
CN107968122B CN201711165223.3A CN201711165223A CN107968122B CN 107968122 B CN107968122 B CN 107968122B CN 201711165223 A CN201711165223 A CN 201711165223A CN 107968122 B CN107968122 B CN 107968122B
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dummy gate
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CN107968122A (en
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李春龙
霍宗亮
叶甜春
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

The application discloses a fin field effect transistor and a preparation method thereof, wherein the preparation method of the fin field effect transistor divides a main etching process of a dummy gate into two etching processes, namely, the first etching to the false gate layer and the second etching to the false gate prototype structure, and introduces a nitridation treatment in the two main etching processes, so as to form an insulating film on the surface of one end of the dummy gate prototype structure which is formed by the first etching and is far away from the substrate, the insulating film plays a role in protecting the dummy gate at one end of the dummy gate prototype structure, which is far away from the substrate, in the second etching process, so that the possibility of damage phenomena such as recess and the like caused by long-time over-etching of the dummy gate at the top in the second etching process is avoided, therefore, the appearance of the grid electrode of the subsequently formed fin field effect transistor is improved, and the electrical performance of the finally formed fin field effect transistor is further improved.

Description

Fin type field effect transistor and preparation method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to a fin type field effect transistor and a manufacturing method thereof.
Background
In order to meet the demand of continuous miniaturization of electronic equipment, the size of a Semiconductor device is continuously reduced, the occurrence of a Fin-Field-Effect Transistor (FinFET) solves the problem of leakage current between a source electrode and a drain electrode of a conventional Complementary Metal Oxide Semiconductor (CMOS) Transistor when the conventional CMOS Transistor is below a 20nm thread, the manufacturing process of the Semiconductor device is really brought into the Field below the 20nm thread, and a new direction is provided for the miniaturization of the Semiconductor device.
The structure of the fin field effect transistor is shown in fig. 1, and includes: a plurality of fins 11 on the surface of the substrate 10, and spacers (not shown in fig. 1) between adjacent fins 11; a source region 12, a channel region 13 and a drain region 14 which are positioned at one side of the fin part, which faces away from the substrate, wherein the channel region 13 is positioned between the source region 12 and the drain region 14; the gate structure 20 is located on the surface of one side, away from the substrate 10, of the fin portion 11, the germanium fin 11, facing one side of the substrate 10, of the gate structure 20 is the channel region 13, is located on two sides of the gate structure, covers the side wall 30 of the side face of the gate structure, and covers the fin portion 11, the side face and the top face of the isolation portion, and the interlayer dielectric layer 40 on the side face of the side wall 30.
In the prior art, when a gate structure of a fin field effect transistor is formed, a dummy gate process is usually adopted, that is, after a fin portion 11 and an isolation portion are formed on the surface of a substrate 10, a gate structure including a dummy gate dielectric layer and a dummy gate is formed first, then a gate-last process is adopted to remove the dummy gate structure after a subsequent process is completed, and a gate structure is formed in a gate opening left after the dummy gate structure is removed, wherein due to the limitation of the three-dimensional shape of the dummy gate, the dummy gate above the fin portion 11 (on the side away from the substrate 10) is formed first in the process of etching the dummy gate, so that the dummy gate above the fin portion 11 needs to undergo long-time over-etching in the etching process of a gate portion below the top of the fin portion 11, thereby forming damage phenomena such as recess or surface damage, which can cause adverse effects on the appearance of the subsequently formed gate structure, the electrical performance of the final fin field effect transistor is adversely affected.
Disclosure of Invention
In order to solve the technical problems, the invention provides a fin field effect transistor and a manufacturing method thereof, which aim to solve the problem of damage phenomena such as recess and the like caused by long-time over-etching of a dummy gate positioned above a fin part in the forming process of the dummy gate.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
a method for manufacturing a fin field effect transistor comprises the following steps:
providing a substrate, wherein the surface of the substrate is provided with a plurality of isolation parts and fin parts which are arranged at intervals, and the isolation parts partially cover the side walls of the fin parts;
depositing a dummy gate dielectric layer on the surface of one side, away from the substrate, of the fin part so that the dummy gate dielectric layer covers the exposed surface of the fin part;
depositing a dummy gate layer on the surface of one side of the isolation part and the fin part, which is far away from the substrate;
carrying out first etching on the false gate layer to form a false gate rudiment structure, wherein the duration of the first etching is first preset time;
performing nitridation treatment on the dummy gate prototype structure to form an insulating film on the surface of one end, away from the substrate, of the dummy gate prototype structure;
and performing second etching on the nitridized dummy gate prototype structure to form a dummy gate crossing at least one fin part, wherein the dummy gate and the dummy gate dielectric layer form a dummy gate structure, the duration of the second etching is second preset time, the ratio of the first preset time to the second preset time is greater than or equal to 1, and the sum of the first preset time and the second preset time is equal to the time required by a main etching process of the dummy gate.
Optionally, the performing nitridation on the dummy gate prototype structure to form an insulating film on a surface of the dummy gate prototype structure, where the surface is away from the substrate, includes:
setting the pressure of a reaction wall body of the environment where the preliminary structure of the false grating is located at 70-80 mTorr, introducing 40-60 milliliters of nitrogen every minute, and carrying out nitridation treatment on the preliminary structure of the false grating for 90-110 seconds at the reaction power of 700-900 watts.
Optionally, a value range of a ratio of the first preset time to the second preset time is
Figure GDA0002421440840000021
Including the endpoint values.
Optionally, a ratio of the first preset time to the second preset time is 0.65: 0.35.
optionally, after performing the second etching on the dummy gate prototype structure after the nitridation processing, the method further includes:
and performing over-etching on the dummy gate.
Optionally, after the over-etching the dummy gate, the method further includes:
forming side walls on two sides of the dummy gate structure, wherein the side walls cover the side faces of the dummy gate structure;
forming a source region and a drain region in the fin portion and on two sides of a channel region, wherein the channel region is the fin portion on one side, facing the substrate, of the dummy gate;
forming an interlayer dielectric layer covering the fin part, the side face and the top face of the isolation part and the side face of the side wall;
removing the dummy gate structure by adopting a gate-last process to form a gate opening;
and forming a gate structure in the gate opening.
Optionally, the forming a gate structure in the gate opening includes:
depositing a high-K material in the gate opening to form a gate dielectric layer;
and depositing a conductive material on the surface of the gate dielectric layer to form a gate.
Optionally, the forming process of the substrate includes:
providing an initial substrate;
forming a mask pattern on the surface of the initial substrate;
etching the initial substrate by taking the mask pattern as a mask to form a plurality of discrete fin parts;
removing the mask pattern, and filling an insulating material between the fin parts to form an isolation structure;
performing a planarization process on the isolation structure until the top of the fin part is exposed;
and thinning the isolation structure to expose partial side walls of the fin part, wherein the rest isolation structure becomes the isolation part.
A fin field effect transistor is manufactured by the fin field effect transistor manufacturing method.
It can be seen from the above technical solutions that the embodiments of the present invention provide a fin field effect transistor and a method for manufacturing the same, wherein the method for manufacturing the fin field effect transistor divides a main etching process of a dummy gate into two etching processes, that is, a first etching process for a dummy gate layer and a second etching process for a dummy gate prototype structure, and introduces a nitridation process in the two main etching processes to form an insulating film on a surface of one end of the dummy gate prototype structure, which is formed by the first etching process, that is away from a substrate, the insulating film plays a role in protecting the dummy gate of the dummy gate prototype structure, which is away from the substrate, during the second etching process, thereby preventing the top dummy gate from being over-etched for a long time during the second etching process to form a recess and other damage phenomena, thereby improving the appearance of a subsequently formed gate electrode of the fin field effect transistor, and further improves the electrical performance of the finally formed fin field effect transistor.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a finfet in the prior art;
fig. 2 is a schematic flow chart illustrating a method for fabricating a finfet according to an embodiment of the present disclosure;
fig. 3-12 (b) are schematic diagrams illustrating a process flow for fabricating a finfet according to an embodiment of the present application;
fig. 13 is a schematic flow chart illustrating a method of fabricating a finfet according to another embodiment of the present application;
fig. 14 is a schematic flow chart illustrating a method for fabricating a finfet according to yet another embodiment of the present application;
fig. 15 is a schematic flow chart illustrating a method of fabricating a finfet according to yet another embodiment of the present application;
fig. 16 is a flow chart illustrating a method of fabricating a finfet according to an embodiment of the present disclosure;
fig. 17 is a cross-sectional view of a finfet according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the application provides a method for manufacturing a fin field effect transistor, as shown in fig. 2, including:
s101: providing a substrate, wherein the surface of the substrate is provided with a plurality of isolation parts and fin parts which are arranged at intervals, and the isolation parts partially cover the side walls of the fin parts;
specifically, the forming process of the substrate comprises the following steps:
as shown in fig. 3, a mask pattern is formed on a flat initial substrate surface. The material of the initial substrate can be a common semiconductor silicon-based substrate such as bulk silicon or silicon-on-insulator. The mask pattern may be formed by spin coating, spray coating, screen printing, Vapor Deposition (CVD), or other processes, and may be a soft mask of a photoresist, or a hard mask of a nitride, an oxide, or a stacked structure thereof (e.g., an ONO structure), and the specific type of the initial substrate and the specific type of the mask pattern are not limited in this application, and are determined according to the actual situation; reference numeral N0 in fig. 3 denotes the initial substrate, and PR denotes the mask pattern.
As shown in fig. 4, reference numeral 101 in fig. 4 denotes a fin portion, and the initial substrate is etched by using the mask pattern as a mask, so as to form a substrate having a plurality of discrete fin portions. The process of Etching the initial substrate preferably employs an anisotropic Etching method, such as fluorine-based plasma dry Etching, Reactive Ion Etching (RIE), or tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) wet Etching. Preferably, the etch parameters are controlled such that the aspect ratio of the silicon fin 101 is greater than 5:1 and preferably greater than 10: 1.
And after a plurality of discrete fin parts are formed, removing the mask pattern by adopting a dry process such as plasma etching, ashing and the like or a wet process adopting a mixture of an oxidant and an acid solution. As shown in fig. 5, an isolation structure is formed by filling an insulating material into the recess between the fins by using a high aspect ratio deposition process (HARP), a high density plasma chemical vapor deposition process (HDPCVD), or a flowable chemical vapor deposition process (flowable CVD). The insulating material forming the isolation structure may be silicon oxide, silicon oxynitride, or a low-K material, wherein the low-K material includes, but is not limited to, organic low-K materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-K materials (e.g., amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glasses, BSG, PSG, and BPSG), porous low-K materials (e.g., disiloxane (SSQ) -based porous low-K materials, porous silicon dioxide, porous SiOCH, C-doped silicon dioxide, F-doped porous amorphous carbon, porous diamond, and porous organic polymers).
In this process, due to the protrusion of the fin portion relative to the substrate, the top of the formed isolation structure also has a corresponding protrusion at a position corresponding to the top of the fin portion.
As shown in fig. 6, a planarization process is performed on the isolation structure until the top of the fin is exposed. The planarization process may be a Chemical Mechanical Polishing (CMP) process or an etch-back process performed with respect to the etch selectivity of the isolation portions and the fins, the isolation structures remaining between the fins constituting isolation portions of the FinFET, also referred to as shallow trench isolation, denoted by STI in fig. 6.
As shown in fig. 7, the isolation portion is thinned by using a shallow trench oxide thinning method, and a portion of the sidewall of the fin portion is exposed. In other embodiments of the present application, the isolation portion may also be thinned by using an anisotropic dry etching process, or by using diluted hydrofluoric acid or diluted slow-release etchant for wet etching. The height of the exposed fin may depend on the topography requirements of the surrounding gate in the FinFET device.
The fin formed through the steps of fig. 2-7 is a silicon fin, and in other embodiments of the present application, the silicon fin may be selectively etched and removed through an anisotropic etching process, and then another material with higher electron mobility and hole mobility is deposited in the groove left after the silicon fin is removed to serve as the fin, and the material includes but is not limited to germanium, gallium arsenide, and silicon germanium.
S102: depositing a dummy gate dielectric layer on the surface of one side, away from the substrate, of the fin part so that the dummy gate dielectric layer covers the exposed surface of the fin part;
referring to fig. 8, fig. 8 is a schematic cross-sectional structure diagram of the substrate and the surface structure thereof after step S102, and reference numeral 200A in fig. 8 denotes the dummy gate dielectric layer.
S103: depositing a dummy gate layer on the surface of one side of the isolation part and the fin part, which is far away from the substrate;
referring to fig. 9, fig. 9 is a schematic cross-sectional structure diagram of the substrate and its surface structure after step S103. The formation of the dummy gate dielectric layer and the dummy gate layer can adopt Plasma Enhanced Chemical Vapor Deposition (PECVD) or High Density Plasma Chemical Vapor Deposition (HDPCVD) or Molecular Beam Epitaxy (Molecular Beam Epitaxy, MBE) or Atomic Layer Deposition (ALD) or thermal evaporation fire oxidation or magnetron sputtering and other processes. This is not limited in the present application, and the reference numeral 200B in fig. 9 denotes the dummy gate layer, depending on the actual situation.
The material of the false gate dielectric layer can be silicon oxide, the material of the false gate layer can be polycrystalline silicon or amorphous silicon or microcrystalline silicon or polycrystalline germanium or amorphous carbon and the like, and the material of the false gate dielectric layer and the material of the false gate layer are selected to improve the etching selectivity with other surrounding materials.
S104: carrying out first etching on the false gate layer to form a false gate rudiment structure, wherein the duration of the first etching is first preset time;
referring to fig. 10, fig. 10 is a schematic cross-sectional structure diagram of the substrate and the surface structure thereof after step S104. It should be noted that the first etching refers to a part of a main etching (main etch, ME) process in the dummy gate forming process, and after the first etching is finished, a dummy gate portion on a side of the top of the fin portion away from the substrate needs to be formed. The etching time of the main etching is determined according to the thickness of the dummy gate layer, reference numeral 200C in fig. 10 denotes a portion of the dummy gate prototype structure higher than the top of the fin portion, which is formed in a subsequent process to form a portion of the dummy gate higher than the top of the fin portion, and 200D denotes a portion of the dummy gate prototype structure lower than the top of the fin portion.
S105: performing nitridation treatment on the dummy gate prototype structure to form an insulating film on the surface of one end, away from the substrate, of the dummy gate prototype structure;
referring to fig. 11, fig. 11 is a schematic cross-sectional structure diagram of the substrate and its surface structure after step S105, where reference numeral 300 in fig. 11 denotes the insulating film, and it is to be noted that, when the material forming the dummy gate layer is amorphous silicon, it is considered that the insulating film formed after the nitridation treatment is a silicon nitride film or a silicon oxynitride film.
S106: and performing second etching on the nitridized dummy gate prototype structure to form a dummy gate crossing at least one fin part, wherein the dummy gate and the dummy gate dielectric layer form a dummy gate structure, the duration of the second etching is second preset time, the ratio of the first preset time to the second preset time is greater than or equal to 1, and the sum of the first preset time and the second preset time is equal to the time required by a main etching process of the dummy gate.
Referring to fig. 12(a) and 12(b), fig. 12(a) is a schematic top view structure diagram of the substrate and its surface structure after step S106, and fig. 12(b) is a schematic cross-sectional structure diagram of fig. 12(a) along line a-a, where STI denotes an isolation portion, 101 denotes a fin portion, 300 denotes an insulating film covering a dummy gate, 200C and 200E together constitute the dummy gate, and 200A denotes the dummy gate dielectric layer.
The second etching and the first etching jointly form a main etching work process in the process of forming the false gate, because a plasma etching process is generally adopted for the main etching of the false gate, after the step S105, the surface of the false gate part above the top of the fin part is covered with a layer of insulating film, charged plasma can not be gathered on the surface of an insulator but can only be gathered around the unetched false gate layer in the subsequent second etching process, so that the agglomeration of charged active ions on the surface of the false gate part above the top of the fin part can be effectively prevented, the etching effect on the false gate part above the top of the fin part in the second etching process is reduced, and the phenomenon that the false gate is recessed in the etching process is inhibited or eliminated.
Preferably, the dummy gate spans all fins on the substrate.
On the basis of the foregoing embodiment, in an embodiment of the present application, as shown in fig. 13, the performing nitridation processing on the dummy gate prototype structure to form an insulating film on a surface of one end of the dummy gate prototype structure, the method includes:
s1051: setting the pressure of a reaction wall body of the environment where the preliminary structure of the false grating is located at 70-80 mTorr, introducing 40-60 milliliters of nitrogen every minute, and carrying out nitridation treatment on the preliminary structure of the false grating for 90-110 seconds at the reaction power of 700-900 watts.
More preferably, the process parameters of the nitridation process are preferably: setting the pressure of a reaction wall body of the environment where the preliminary structure of the false gate is positioned at 80 mTorr, introducing 50 milliliters of nitrogen every minute, and carrying out nitridation treatment on the preliminary structure of the false gate for 100 seconds at the reaction power of 800 watts;
the nitridation process can be abbreviated as 80MT/800W/50N2The reaction time is 100 seconds, namely the pressure of the reaction wall is 80 millitorr, the reaction power is 800 watts, and 50sccm (50 milliliters per minute) of nitrogen is introduced.
On the basis of the foregoing embodiment, in another embodiment of the present application, a value range of a ratio of the first preset time to the second preset time is
Figure GDA0002421440840000081
Including the endpoint values.
It should be noted that, in general, the etching time required for the dummy gate located above the top of the fin is longer than the etching time required for the dummy gate located below the top of the fin, that is, the first preset time is longer than or equal to the second preset time, and in an embodiment of the present application, the first preset time accounts for 50% -70% of the total main etching time, inclusive;
preferably, the ratio of the first preset time to the second preset time is 0.65: 0.35. namely, the first preset time accounts for 65% of the total time of the main etching.
On the basis of the foregoing embodiment, in another embodiment of the present application, as shown in fig. 14, after performing the second etching on the dummy gate prototype structure after the nitridation processing, the method further includes:
s107: and performing over-etching on the dummy gate.
Generally, after a main etching process for forming a dummy gate, an Over Etching (OE) process is required to modify the formed dummy gate so that the formed dummy gate has a better topography.
On the basis of the above embodiments, in an embodiment of the present application, a process after forming a dummy gate is provided, as shown in fig. 15, after performing over-etching on the dummy gate, the method further includes:
s108: forming side walls on two sides of the dummy gate structure, wherein the side walls cover the side faces of the dummy gate structure;
s109: forming a source region and a drain region in the fin portion and on two sides of a channel region, wherein the channel region is the fin portion on one side, facing the substrate, of the dummy gate;
s110: forming an interlayer dielectric layer covering the fin part, the side face and the top face of the isolation part and the side face of the side wall;
s111: removing the dummy gate structure by adopting a gate-last process to form a gate opening;
s112: and forming a gate structure in the gate opening.
Specifically, as shown in fig. 16, the forming of the gate structure in the gate opening includes:
s1121: depositing a high-K material in the gate opening to form a gate dielectric layer;
s1122: and depositing a conductive material on the surface of the gate dielectric layer to form a gate.
The process used to deposit the high-K material and the conductive material may be HDPCVD or MOCVD or MBE or ALD. The high-K materials include, but are not limited to, nitrides (e.g., SiN, AlN, TiN), metal oxides (primarily subgroup and lanthanide metal element oxides, e.g., MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3), oxynitrides (e.g., HfSiON); perovskite phase oxides (e.g., PbZrxTi1-xO3(PZT), BaxSr1-xTiO3 (BST)). The gate electrode material includes, but is not limited to, polysilicon, poly-silicon germanium, or a metal, wherein the metal may include simple metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or alloys of these metals, and nitrides of these metals, and the gate electrode 600B may be doped with elements such as C, F, N, O, B, P, As to adjust the work function.
On the basis of the above embodiments, in a preferred embodiment of the present application, a nitride barrier layer is preferably formed between the gate dielectric layer and the gate by PVD, CVD, ALD, or other conventional methods, and the material of the barrier layer is MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNzWherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. More preferably, the gate and the blocking layer not only adopt a composite layer structure stacked up and down, but also adopt a mixed implantation doping layer structure, that is, the materials constituting the gate and the blocking layer are simultaneously deposited on the gate dielectric layer, so that the gate 600B includes the materials of the blocking layer. And then, further etching the ILD to form a contact hole exposing the elevated source region HS and the elevated drain region HD, and filling metals such as W, Al, Cu, Ti, Ta, Mo and the like, metal alloy, metal nitride and the like in the contact hole to form a contact plug. And further preferably before forming a nickel-based metal silicide in the contact hole to reduce contactA contact resistance.
Correspondingly, the embodiment of the application also provides a fin field effect transistor, and the fin field effect transistor is prepared by adopting the preparation method of the fin field effect transistor in any one of the embodiments.
Alternatively, as shown in fig. 17, the finfet includes: a plurality of fins 101 on a surface of the substrate 100, and spacers (not shown in fig. 1) between adjacent fins 101; a source region 102, a channel region 103 and a drain region 104 which are positioned on the side of the fin part facing away from the substrate, wherein the channel region 103 is positioned between the source region 102 and the drain region 104; the gate structure 500 is located on the surface of one side of the fin portion 101, which is away from the substrate 100, the germanium fin 101, which is located on one side of the gate structure 500, which is towards the substrate 100, is the channel region 103, the side walls 600 are located on two sides of the gate structure, the side surfaces of the gate structure are covered with the side walls 600, the interlayer dielectric layers 400 are covered on the fin portion 101, the side surfaces and the top surface of the isolation portion, and the side surfaces of the side walls 600,
it should be noted that, in other embodiments of the present application, the fin portion 101 may be a silicon fin portion, a germanium fin portion, or a fin portion composed of a silicon germanium fin and a germanium fin. The present application does not limit this, which is determined by the actual situation.
In summary, the embodiments of the present application provide a fin field effect transistor and a method for fabricating the same, wherein, the preparation method of the fin field effect transistor divides the main etching process of the dummy gate into two etching processes, namely, the first etching to the false gate layer and the second etching to the false gate prototype structure, and introduces a nitridation treatment in the two main etching processes, so as to form an insulating film on the surface of one end of the dummy gate prototype structure which is formed by the first etching and is far away from the substrate, the insulating film plays a role in protecting the dummy gate at one end of the dummy gate prototype structure, which is far away from the substrate, in the second etching process, so that the possibility of damage phenomena such as recess and the like caused by long-time over-etching of the dummy gate at the top in the second etching process is avoided, therefore, the appearance of the grid electrode of the subsequently formed fin field effect transistor is improved, and the electrical performance of the finally formed fin field effect transistor is further improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A method for manufacturing a fin field effect transistor is characterized by comprising the following steps:
providing a substrate, wherein the surface of the substrate is provided with a plurality of isolation parts and fin parts which are arranged at intervals, and the isolation parts partially cover the side walls of the fin parts;
depositing a dummy gate dielectric layer on the surface of one side, away from the substrate, of the fin part so that the dummy gate dielectric layer covers the exposed surface of the fin part;
depositing a dummy gate layer on the surface of one side of the isolation part and the fin part, which is far away from the substrate;
carrying out first etching on the false gate layer to form a false gate rudiment structure, wherein the duration of the first etching is first preset time;
performing nitridation treatment on the dummy gate prototype structure to form an insulating film on the surface of one end, away from the substrate, of the dummy gate prototype structure;
and performing second etching on the nitridized dummy gate prototype structure to form a dummy gate crossing at least one fin part, wherein the dummy gate and the dummy gate dielectric layer form a dummy gate structure, the duration of the second etching is second preset time, the ratio of the first preset time to the second preset time is greater than or equal to 1, and the sum of the first preset time and the second preset time is equal to the time required by a main etching process of the dummy gate.
2. The method of claim 1, wherein the nitriding the dummy gate prototype structure to form an insulating film on a surface of the dummy gate prototype structure opposite to the substrate comprises:
setting the pressure of a reaction wall body of the environment where the preliminary structure of the false grating is located at 70-80 mTorr, introducing 40-60 milliliters of nitrogen every minute, and carrying out nitridation treatment on the preliminary structure of the false grating for 90-110 seconds at the reaction power of 700-900 watts.
3. The method of claim 1, wherein a ratio of the first predetermined time to the second predetermined time ranges from a value of
Figure FDA0002421440830000011
Including the endpoint values.
4. The method according to claim 3, wherein the ratio of the first preset time to the second preset time is 0.65: 0.35.
5. the method of claim 1, wherein after the second etching of the nitridized dummy gate prototype structure, further comprising:
and performing over-etching on the dummy gate.
6. The method of claim 5, wherein after over-etching the dummy gate, further comprising:
forming side walls on two sides of the dummy gate structure, wherein the side walls cover the side faces of the dummy gate structure;
forming a source region and a drain region in the fin portion and on two sides of a channel region, wherein the channel region is the fin portion on one side, facing the substrate, of the dummy gate;
forming an interlayer dielectric layer covering the fin part, the side face and the top face of the isolation part and the side face of the side wall;
removing the dummy gate structure by adopting a gate-last process to form a gate opening;
and forming a gate structure in the gate opening.
7. The method of claim 6, wherein the forming a gate structure in the gate opening comprises:
depositing a high-K material in the gate opening to form a gate dielectric layer;
and depositing a conductive material on the surface of the gate dielectric layer to form a gate.
8. The method of claim 1, wherein the forming of the substrate comprises:
providing an initial substrate;
forming a mask pattern on the surface of the initial substrate;
etching the initial substrate by taking the mask pattern as a mask to form a plurality of discrete fin parts;
removing the mask pattern, and filling an insulating material between the fin parts to form an isolation structure;
performing a planarization process on the isolation structure until the top of the fin part is exposed;
and thinning the isolation structure to expose partial side walls of the fin part, wherein the rest isolation structure becomes the isolation part.
9. A fin field effect transistor manufactured by the method of manufacturing a fin field effect transistor according to any one of claims 1 to 8.
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