CN104167359A - Semiconductor device manufacture method - Google Patents
Semiconductor device manufacture method Download PDFInfo
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- CN104167359A CN104167359A CN201310185048.XA CN201310185048A CN104167359A CN 104167359 A CN104167359 A CN 104167359A CN 201310185048 A CN201310185048 A CN 201310185048A CN 104167359 A CN104167359 A CN 104167359A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a semiconductor device manufacture method comprising the following steps: a fake grid electrode stack is formed on a substrate, a forerunner layer having an amorphous or polycrystalline structure is formed side faces of the fake grid electrode stack, annealing operation is performed, the forerunner layer is converted into a seed crystal layer having a monocrystalline structure, the seed crystal layer is doped, and therefore a source-drain area is formed. According to the semiconductor device manufacture method of the invention, the monocrystalline seed crystal layer is formed by annealing the forerunner layer formed a two sides of the fake grid electrode stack, the forerunner layer is formed through use of fine line s, the source-drain area is formed by doping the seed crystal layer, and therefore an ultrathin SOI semiconductor device is formed; device miniaturization is realized and device performance is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, more specifically, relate to the transistorized manufacture method of silicon (ETSOI) on a kind of ultrathin insulating body.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, this structural reinforcing grid control ability, suppressed electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, can suppress short-channel effect (SCE) and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, can realize raceway groove light dope, can carry out adjusting threshold voltage by the work function that metal gates is set, can obtain the drive current of approximately 2 times, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, grid has surrounded channel region end face and two sides, and grid control ability is stronger.Further, loopful has more advantage around nano wire multiple-grid device.These devices, because size is little, complex structure, easily interfere with each other between adjacent raceway groove, and therefore the isolation technology of raceway groove becomes more and more important.
Existing FinFET structure and manufacture method comprise: the 1) FinFET of SOI substrate, utilize the mask etching SOI substrates such as photoresist, automatically stop on oxygen buried layer, remaining top silicon layer forms fin, and isolate adjacent fin because oxygen buried layer can insulate well, therefore carry out isolation channel without extra processing step or structure; 2) the body substrate FinFET of knot isolation, utilize mask etching body silicon substrate to form groove and fin, in groove between fin, deposit fill oxide and carry out the adjacent fin of side direction insulation isolation, angle-tilt ion is injected high dose dopant subsequently, dopant implant district in the formation of fin bottom with top different conduction-types, utilizes PN junction to isolate fin and substrate; 3) the body substrate FinFET isolating based on material; utilize mask etching body substrate-like to become groove and fin; in groove between fin, deposition oxide is isolated with side direction; form the side walls such as nitride in fin side so that protection to be provided; carry out thermal oxidation; make not by the fin base section of side wall protection or all oxidized so that the oxide layer that formation connected with each other is horizontal utilizes the oxide layer obtaining to isolate fin and substrate.
In above-mentioned these structures and method, although FinFET structure and the technique of SOI substrate are simple, backing material cost is high, not as body Si substrate is easy to for large-scale production; On body silicon substrate, utilize the FinFET of PN junction isolation to utilize and inject knot isolation, isolation effect is subject to the restriction of implantation dosage, the degree of depth and effect is poor, and injection technology is difficult to control, and easily introduces extra doping to channel region and affects device electric conductivity; Complex process is with high costs on body silicon substrate, to utilize the FinFET of horizontal selective oxidation isolation, and oxidate temperature is high, thereby extra-stress and strain impact conduction are easily introduced in channel region.In addition, these technology are all to make in the process that forms silicon fin conventionally, and when after FinFET adopts, grid technique is manufactured, false grid form the isolation structure of making in silicon fin process before forming, and when experience subsequent technique, insulation property may be impaired.In addition, these current silicon fin trench isolation structures be all conventionally along vertical-channel direction (hereinafter referred to as X-X ' direction or second direction, also be the direction that grid lines extend) upper formation, for along between the upper fin of channel direction (hereinafter referred to as Y-Y ' direction or first direction, being also the direction that fin lines extend) and perfect not with the isolation of substrate.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of method, semi-conductor device manufacturing method of novelty, overcome the problems referred to above, realize the miniaturization of device and improve insulation isolation performance.
Realizing above-mentioned purpose of the present invention, is by one one kinds of method, semi-conductor device manufacturing methods are provided, and comprising: on substrate, form false grid stacking; Form the precursor layer of amorphous or polycrystalline structure in the stacking side of false grid; Annealing, makes precursor layer change the kind crystal layer of mono-crystalline structures into; Kind of a crystal layer doping is formed to source-drain area.
Wherein, substrate is ETSOI, comprises substrate, oxygen buried layer and top layer, and wherein top layer thickness is 1～5nm.
Wherein, forming the stacking step of false grid further comprises: on substrate, form laying and sacrifice layer; Etching sacrificial layer and laying, until expose substrate, form first grid groove; Form grid curb wall at first grid trenched side-wall; In first grid groove, form packed layer; Remove sacrifice layer and laying, leave false grid stacking.
Wherein, laying material comprises silica, TEOS, silicon nitride, silicon oxynitride and combination thereof; Preferably, sacrifice layer material comprises polysilicon, amorphous silicon, amorphous germanium, amorphous carbon, SiGe, SiC and combination thereof; Preferably, grid curb wall material comprises silicon nitride, silicon oxynitride, SiOCN, SiCN, diamond like carbon amorphous carbon (DLC) and combination thereof; Preferably, packed layer material comprises silica, TEOS, silicon oxynitride, SiOC, SiOH and combination thereof.
Wherein, wet etching is removed sacrifice layer and/or laying, and packed layer top is lower than grid curb wall top.
Wherein, precursor layer material comprises Si, SiGe, SiC and the combination thereof of amorphous or polycrystalline structure.
Wherein, annealing temperature is 800～1400 degrees Celsius, preferably 1000～1300, and the best is 1150 degrees Celsius.
Wherein, forming source-drain area further comprises afterwards: remove part false grid stacking; Form metal level at source-drain area and false grid on stacking; Annealing makes metal level react with source-drain area and forms metal silicide; Peel off unreacted metal level, continue to remove part false grid stacking, leave second grid groove; In second grid groove, form gate stack.
Wherein, gate stack comprises boundary layer, gate insulator, work function regulating course, resistance adjustment layer.
Wherein, second grid groove upper width is greater than lower width.
According to method, semi-conductor device manufacturing method of the present invention, utilize the precursor layer annealing of the stacking both sides of false grid of meticulous lines to form the kind crystal layer of monocrystalline, doping forms source-drain area, has formed thus ultra-thin SOI semiconductor device, realize the miniaturization of device, improved device performance.
Brief description of the drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 20 is the cutaway view according to the each step of method, semi-conductor device manufacturing method of the present invention; And
Figure 21 is according to method, semi-conductor device manufacturing method indicative flowchart of the present invention.
Embodiment
Also describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score, " thick ", " thin " etc. can be used for modifying various device architectures and/or manufacturing step.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture and/or manufacturing step.
As shown in Figure 1, on substrate 1, form laying 2 and sacrifice layer 3.Substrate 1 is provided, and it can be body Si, SOI, body Ge, GeOI, SiGe, GeSb, can be also III-V family or II-VI compound semiconductor substrate, for example GaAs, GaN, InP, InSb etc.For with existing CMOS process compatible to be applied to large-scale digital ic manufacture, substrate 1 is preferably SOI or SiGe, SiGeOI etc. containing Si material.In a preferred embodiment of the invention, substrate 1 is ultra-thin SOI (ETSOI), comprises thicker monocrystalline silicon Si substrate 1A, such as the oxygen buried layer 1B of silica material and thinner single crystalline Si top layer 1C, and wherein oxygen buried layer 1B thickness for example
and preferably
, SOI top layer 1C thickness for example
(1～5nm) is also preferred
.The thickness of top layer 1C can be adjusted by controlling (temporarily suprabasil) SOI substrate epitaxial growth parameter(s), or after the interim substrate of laser lift-off, SOI top layer is carried out to attenuate and obtain.Top layer 1C will be used to form the channel region of device.
Then on whole wafer, be, also to form successively laying 2 and sacrifice layer 3 on the top layer 1C of SOI substrate 1 by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputters.Preferably adopt the depositing operation of good shape retention to form thinner laying 2, its material silica based materials that such as silica, TEOS(are prepared as raw material CVD taking TEOS), silicon nitride, silicon oxynitride etc. and combination thereof.In a preferred embodiment, laying 2 is silica prepared by HDPCVD.For example 3～20nm only of the thickness of laying 2
.Sacrifice layer 3 materials for example comprise polysilicon, amorphous silicon, amorphous germanium, amorphous carbon, SiGe, SiC, diamond like carbon amorphous carbon (DLC) etc. and combination thereof, so that the Etch selectivity between raising and laying 2 and the following upper layer of material of lower floor.In a preferred embodiment of the invention, sacrifice layer 3 is amorphous silicons, and thickness is 10～50nm for example.
As shown in Figure 2, on sacrifice layer 3, form the first photoetching offset plate figure PR1.On whole device, apply photoresist layer PR by techniques such as spin coating, spraying, silk screen printings, and utilize predetermined mask plate exposure, development to form the first photoetching offset plate figure PR1, wherein PR1 has near the opening being positioned at center, active area to expose sacrifice layer 3, for limiting the position of grid in the future.
As shown in Figure 3, taking the first photoetching offset plate figure PR1 as mask, etching sacrificial layer 3 is to form groove 3G, until expose laying 2.Can select various anisotropic lithographic methods according to the material difference of sacrifice layer 3, such as plasma dry etching, reactive ion etching (RIE) or Tetramethylammonium hydroxide (TMAH) wet etching etc.Preferably, form groove 3G and remove the first photoetching offset plate figure PR1 by dry method or wet processing afterwards.
As shown in Figure 4, remove the laying 2 exposing in groove 3G, until expose the top layer 1C of ETSOI substrate 1.For the material of laying 2, preferred anisotropic etching technics, for example plasma dry etching or RIE.In the time that laying 2 has higher Etch selectivity compared with sacrifice layer 3, top layer 1C material, also can selective wet etching technique, for example sacrifice layer 3 for amorphous silicon, top layer 1C be monocrystalline silicon, laying 2 during for silica, can select HF base corrosive liquid (dHF, dBOE etc.).
As shown in Figure 5, on groove 3G bottom and sidewall and sacrifice layer 3, form spacer material layer 4.For example by the techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, magnetron sputtering form material more firmly, finer and close spacer material layer 4, for example silicon nitride of its material (SiN), silicon oxynitride (SiiO
xn
y, wherein nitrogen oxygen ratio is greater than 1.5:1 and is preferably greater than or equal to 2:1), SiOCN, SiCN, DLC etc. and combination thereof.For example 1～5nm only of spacer material layer 4 thickness.Now, the incomplete filling groove 3G of layer 4, but only covered bottom and sidewall.
As shown in Figure 6, etch layer 4, leaves grid curb wall 4S at groove 3G sidewall.Preferred isotropic dry etching, adjusting etching gas component (for example, carbon fluorine ratio in the fluorine-based etching gas of carbon) makes vertical direction etch rate significantly be greater than horizontal direction etch rate (for example ratio between two is greater than 5:1 preferred 10:1), remove the part material layer 4 at sacrifice layer 3 tops and groove 3G bottom liner layer 2 top, again expose laying 2, left grid curb wall 4S, its width equals or is slightly less than the thickness of spacer material layer 4.
As shown in Figure 7, in groove 3G and on sacrifice layer 3, form packed layer 5.Fill process is LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD etc. such as, and preferred high depth is than the depositing operation of (HARP).The packed layer 5 materials silica based materials that for example silica, TEOS(are prepared as raw material CVD taking TEOS, industry is called for short TEOS conventionally), silicon oxynitride (nitrogen oxygen ratio is less than 2:1), SiOC, SiOH etc. and combination thereof.Packed layer 5 thickness are at least greater than the degree of depth (being also the thickness of sacrifice layer 3) of groove 3G.
As shown in Figure 8, adopt CMP, return technique planarization packed layers 5 such as carving (etch-back) until expose sacrifice layer 3.Now, sacrifice layer 3 tops, grid curb wall 4S top flush with packed layer 5 top threes, are also positioned in same level.
As shown in Figure 9, selective etch is removed sacrifice layer 3, exposes laying 2.For the material of sacrifice layer 3, the technique that Etch selectivity is high, for example in the time that sacrifice layer 3 contains Si material for polysilicon, amorphous silicon etc., can select TMAH wet etching, in the time that sacrifice layer 3 is the other materials such as SiGe, SiC, amorphous carbon, amorphous germanium, can select strong oxidizer (ozone, hydrogen peroxide) to mix removal with strong acid (sulfuric acid, nitric acid).In addition, also can using plasma dry etching or RIE, and adjust etching gas content (the carbon fluorine of for example fluorine-based etching gas of carbon is than controlling for the Etch selectivity between silicon nitride-based material and silica based materials), make etching basic only longitudinally for sacrifice layer 3, and substantially do not corrode laying 2 and grid curb wall 4S.For example carbon of etching gas fluorine-based (CxHyFz, x is that 1～4, y is that 0～4, z is 1～8, triadic relation meet make to form saturated or undersaturated fluorohydrocarbon) gas, thereby recently control etching rate and obtain steep pattern by adjusting carbon fluorine.For example, etching gas can comprise CF
4, CH
3f, CHF
3, CH
2f
2, C
4f
8, C
4f
6deng and combination and enter one by one step and comprise O
2, the oxidizing gas such as CO to be to regulate etch rate.Etching terminal can be adjusted by controlling etch rate and etch period, or in detection etch chamber, reaction product material, content are determined.
As shown in figure 10, selective etch is removed laying 2.Similar with step shown in Fig. 9, can adopt HF base corrosive liquid to remove the laying 2 of silica based materials, or adjust etching gas component and carry out dry etching laying 2, until expose the ultra-thin top layer 1C of ETSOI substrate 1, only on substrate 1, leave thus the packed layer 5 that grid curb wall 4S surrounds.Now, etching technics also can corrode the top of packed layer 5 slightly, therefore makes the top of grid curb wall 5S a little more than the top of packed layer 5 remainders.
The step of above Fig. 1 to Figure 10 has shown the process that forms false grid stacking (being made up of grid curb wall 4S and packed layer 5) on ETSOI substrate top layer 1C, but it is stacking in other embodiments of the invention, can to adopt different processing steps to form this false grid.For example, (can adopt the ETSOI substrate that is different from the preferred embodiment of the present invention at substrate, but adopt conventional body Si or thick SOI substrate) the upper false grid material layer (identical with packed layer 5 materials) that forms, etching false grid material layer, to form false grid figure (with packed layer 5 syntypes of grid curb wall 4S encirclement), forms grid curb wall 4S around false grid figure.The processing step of Fig. 1 to Figure 10 is in order to enter the fineness of step raising false grid lines one by one, to be not intended to limit other modes that the present invention can implement.
As shown in figure 11, on whole device, form precursor layer 6.For example form precursor layer 6 by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputters, covered top layer 1C, grid curb wall 4S and the packed layer 5 of ETSOI substrate 1 completely.The material of precursor layer 6 preferably with the top layer 1C material close (for example lattice constant is close) of single crystalline Si, such as amorphous silicon, polysilicon, (monocrystalline, amorphous silicon or polysilicon) SiGe, (monocrystalline, amorphous silicon or polysilicon) SiC etc. and combination thereof.In the present invention one by one in preferred embodiment, under 450 degrees Celsius, adopt LPCVD or PECVD to prepare low temperature amorphous silicon with as precursor layer 6.Now, as shown in figure 11, precursor layer 6 end faces are higher than grid curb wall 4S top and enter to walk one by one higher than packed layer 5 tops.
As shown in figure 12, adopt CMP, return the technique planarization precursor layer 6 such as quarter until expose the packed layer 5 that grid curb wall 4S surrounds.Because packed layer in Figure 10 5 is lower than grid curb wall 4S, therefore first the flatening process shown in Figure 12 exposes grid curb wall 4S, and then further planarization is until expose packed layer 5.
As shown in figure 13, annealing, the lattice structure of adjusting precursor layer 6 makes its monocrystalline silicon Si that is further close to top layer 1C, for example, change the kind crystal layer of monocrystalline into, with the active area as device.In the present invention, one by one in embodiment, precursor layer 6 be amorphous silicon, therefore preferably 1000～1300 and preferably anneal under 1150 degrees Celsius and make amorphous silicon precursor layer 6 change the kind crystal layer 6 ' of monocrystalline silicon into.In other embodiments of the invention, precursor layer 6 is that SiGe, SiC etc. are containing Si compound, can under 800～1400 degree celsius temperature, anneal and make the layer 6 of amorphous silicon, polysilicon change the kind crystal layer 6 ' of mono-crystalline structures into, SiGe, the SiC layer of these monocrystalline can be to channel region stress application to improve carrier mobility.
In addition, it should be noted that, although Figure 11 to Figure 13 has shown the kind crystal layer 6 ' that first forms the precursor layer 6 of amorphous or polycrystalline annealing and change into monocrystalline, also can be in deposition, sputter procedure adjusting process parameter progressively, make the kind crystal layer 6 ' of a step formation monocrystalline.For example, carry out epitaxy technique, directly taking the top layer 1C of monocrystalline as Si, the SiGe of seed (seed) epitaxial growth mono-crystalline structures or the kind crystal layer 6 ' of SiC with the active area as device.
As shown in figure 14, the kind crystal layer 6 ' of mono-crystalline structures is carried out to dopant implant, in active area, form source region 6S and drain region 6D.The dopant injecting for example comprises Li, B, C, N, F, P, As, Be, Si, Ge, In, Ga etc. and combination thereof, for example 1～20KeV of Implantation Energy, and implantation dosage is 1E13～5E16cm for example
-2.Subsequently, under 400～750 degrees Celsius, carry out annealing to activate dopant.In addition, also can form layer 6 ' in-situ doped formation source-drain area simultaneously in extension.Now, due to stopping of packed layer 5 and grid curb wall 4S, in the top layer 1C of its below, do not there is dopant, and in the top layer 1C of source-drain area 6S/D below, may there is lighter doping content (obtaining by controlling Implantation Energy), make thus the top layer 1C of the below of packed layer 5 and grid curb wall 4S form the channel region 1CH of device.
As shown in figure 15, part is removed packed layer 5, again to expose groove 3G.Preferred anisotropic etching technics, such as plasma dry etching, RIIE etc.In addition, also can select wet etching for packed layer 5 feature different from surrounding structure material.Adjust etch-stop stop by control etch period, etch rate, make still to have retained in groove 3G the packed layer 5 of part, 1/5～1/3 of for example source-drain area 6S/6D thickness of its residual thickness.
As shown in figure 16, on whole device, form metal level 7 by techniques such as MOCVD, PECVD, MBE, ALD, evaporation, sputters, its material is Ni, Pt, Co, Ti, Ta and combination thereof.
As shown in figure 17, the 10ms～5min that anneals under 450～850 degrees Celsius, makes metal level 7 react formation metal silicide 8 with the Si planting in crystal layer 6 '/source-drain area 6S, 6D.Now, due to the version such as nitride, oxide that grid curb wall 4S, packed layer 5 are Si, cannot discharge independent Si and metal reaction, therefore in groove 3G, packed layer 5 tops cannot form metal silicide 8.Peel off subsequently unreacted metal level 7, only on source-drain area, leave metal silicide 8.With reference to Figure 16,17 known, metal level 7 can reaction consumes kind crystal layer 6 ' or the source-drain area 6S/6D of the mono-crystalline structures of part, therefore in Figure 17, plants crystal layer 6 ' or source-drain area thickness reduces.
As shown in figure 18, remove remaining packed layer 5, until exposed top layer 1C leaves gate trench.The etching adopting is removed shown in technique and Figure 15 similar, and preferably adopts dHF(dilution HF acid) or dBOE(dilute slowly-releasing etching liquid, the mixed solution of HF and NH4F) packed layer 5 of the silica-based material of erosion removal.Now, due to grid curb wall 4S and oxide or the nitride form that layer 5 is Si that be partially filled staying, cannot react formation metal silicide, therefore the groove opening staying after peeling off is T-shaped structure, also be that upper width is greater than lower width, this improves filling rate, minimizing or eliminates hole while being conducive to gate stack filling after a while.
Although Figure 15～Figure 18 has shown that first part is removed packed layer, formation metal silicide is removed packed layer afterwards more completely, this step will improve filling rate, minimizing or eliminate hole.But for example, when groove, opening size are greatly (more than 45nm, or more than 22nm) time, also can directly form metal silicide 8 at the upper depositing metal layers 7 of source-drain area 6 ' annealing injecting to form after source-drain area, be gate trench opening be now vertical sidewall structure and do not there is T-shaped pattern wide at the top and narrow at the bottom.
As shown in figure 19, in gate trench, form gate stack.Preferably, by chemical oxidation or thermal oxidation at gate trench top and sidewall form ultra-thin boundary layer 9A, for example silica material, for reducing cross section defect.Subsequently, adopt the techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputter to fill gate insulator 9B, work function regulating course 9C, resistance adjustment layer 9D in gate trench bottom and sidewall successively.Gate insulator 9B is high k material, includes but not limited to comprise be selected from HfO
2, HfSiO
x, HfSiON, HfAlO
x, HfTaO
x, HfLaO
x, HfAlSiO
x, HfLaSiO
xhafnium sill (wherein, each material is according to multi-element metal component proportion and chemical valence difference, and oxygen atom content x can rationally adjust, for example can be 1～6 and be not limited to integer), or comprise and be selected from ZrO
2, La
2o
3, LaAlO
3, TiO
2, Y
2o
3rare earth based high K dielectric material, or comprise Al
2o
3, with the composite bed of its above-mentioned material.Work function regulating course 9C material is M
xn
y, M
xsi
yn
z, M
xal
yn
z, M
aal
xsi
yn
z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.Resistance adjustment layer 9D material can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, in addition can be doped with elements such as C, F, N, O, B, P, As to enter step joint work function one by one.
As shown in figure 20, carry out CMP, return the techniques such as quarter with the stacking 9(9A～9D of planarized gate) until exposing metal silicide 8 or grid curb wall 4S.Subsequently, can further adopt various conventional process to complete device manufacture.For example on device, deposit interlayer dielectric layer (ILD), in ILD, etching forms contact hole with source of exposure drain region 6 or metal silicide 8, in contact hole, form metal silicide to reduce contact resistance, on metal silicide, fill metal material and form contact plug.
According to method, semi-conductor device manufacturing method of the present invention, utilize the precursor layer annealing of the stacking both sides of false grid of meticulous lines to form the kind crystal layer of monocrystalline, doping forms source-drain area, has formed thus ultra-thin SOI semiconductor device, realize the miniaturization of device, improved device performance.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention method that forms device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.
Claims (10)
1. a method, semi-conductor device manufacturing method, comprising:
On substrate, form false grid stacking;
Form the precursor layer of amorphous or polycrystalline structure in the stacking side of false grid;
Annealing, makes precursor layer change the kind crystal layer of mono-crystalline structures into;
Kind of a crystal layer doping is formed to source-drain area.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, substrate is ETSOI, comprises substrate, oxygen buried layer and top layer, wherein top layer thickness is 1～5nm.
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, forms the stacking step of false grid and further comprises:
On substrate, form laying and sacrifice layer;
Etching sacrificial layer and laying, until expose substrate, form first grid groove;
Form grid curb wall at first grid trenched side-wall;
In first grid groove, form packed layer;
Remove sacrifice layer and laying, leave false grid stacking.
4. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, laying material comprises silica, TEOS, silicon nitride, silicon oxynitride and combination thereof; Preferably, sacrifice layer material comprises polysilicon, amorphous silicon, amorphous germanium, amorphous carbon, SiGe, SiC and combination thereof; Preferably, grid curb wall material comprises silicon nitride, silicon oxynitride, SiOCN, SiCN, diamond like carbon amorphous carbon (DLC) and combination thereof; Preferably, packed layer material comprises silica, TEOS, silicon oxynitride, SiOC, SiOH and combination thereof.
5. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, wet etching is removed sacrifice layer and/or laying, and packed layer top is lower than grid curb wall top.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, precursor layer material comprises Si, SiGe, SiC and the combination thereof of amorphous or polycrystalline structure.
7. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, annealing temperature is 800～1400 degrees Celsius, preferably 1000～1300, and the best is 1150 degrees Celsius.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, forms source-drain area and further comprises afterwards:
Remove part false grid stacking;
Form metal level at source-drain area and false grid on stacking;
Annealing makes metal level react with source-drain area and forms metal silicide;
Peel off unreacted metal level, continue to remove part false grid stacking, leave second grid groove;
In second grid groove, form gate stack.
9. method, semi-conductor device manufacturing method as claimed in claim 8, wherein, gate stack comprises boundary layer, gate insulator, work function regulating course, resistance adjustment layer.
10. method, semi-conductor device manufacturing method as claimed in claim 8, wherein, second grid groove upper width is greater than lower width.
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