CN104167359B - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN104167359B CN104167359B CN201310185048.XA CN201310185048A CN104167359B CN 104167359 B CN104167359 B CN 104167359B CN 201310185048 A CN201310185048 A CN 201310185048A CN 104167359 B CN104167359 B CN 104167359B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000002243 precursor Substances 0.000 claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 15
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 9
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- 238000001039 wet etching Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
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- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 229910052741 iridium Inorganic materials 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
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- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a semiconductor device manufacturing method, which comprises the following steps: forming a dummy gate stack on a substrate; forming a precursor layer of an amorphous or polycrystalline structure on the side face of the dummy gate stack; annealing to convert the precursor layer into a seed layer with a single crystal structure; and doping the seed layer to form a source drain region. According to the manufacturing method of the semiconductor device, the precursor layers on two sides of the false grid stack of the fine lines are annealed to form the single crystal seed layer, and the source and drain regions are formed by doping, so that the ultrathin SOI semiconductor device is formed, the miniaturization of the device is realized, and the performance of the device is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly, to silicon on a kind of ultrathin insulating body
（ETSOI）The manufacture method of transistor.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device（FinFET or Tri-gate）It is main device architecture,
This structure enhances grid control ability, inhibits electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure can suppress short compared with traditional single grid body Si or SOI MOSFET
Channelling effect（SCE）And leakage causes induced barrier to reduce（DIBL）Effect, has lower junction capacity, can realize that raceway groove is gently mixed
It is miscellaneous, it can obtain about 2 times of driving current by setting the work function of metal gates come adjusting threshold voltage, reduce
For effective gate oxide thickness（EOT）Requirement.And tri-gate devices are compared with double-gated devices, grid enclose channel region top surface and
Two sides, grid control ability are stronger.Further, loopful is more advantageous around nano wire multi-gate device.These devices by
It is small, complicated in size, easily interfered with each other between adjacent raceway groove, therefore the isolation technology of raceway groove becomes increasingly to weigh
Will.
Existing FinFET structure and manufacture method include：1）The FinFET of SOI substrate, is carved using masks such as photoresists
SOI substrate is lost, is automatically stopped on oxygen buried layer, remaining top silicon layer forms fin, and since oxygen buried layer can insulate well
Isolate adjacent fin, therefore carry out isolation channel without extra processing step or structure；2）The body substrate of junction isolation
FinFET, forms groove and fin using mask etching body silicon substrate, fill oxide is deposited in the groove between fin
Adjacent fin is laterally dielectrically separated from, subsequent angle-tilt ion injects high dose dopant, is formed in fin bottom different from top
The injection doped region of conduction type, isolates fin and substrate using PN junction；3）Based on material come the body substrate FinFET that isolates,
Groove and fin are formed using mask etching body substrate, deposition oxide is laterally to isolate in the groove between fin, in fin
Piece side forms the side wall such as nitride to provide protection, performs thermal oxide so that not by the fin base section of side wall protection or
Person is all aoxidized so that be connected with each other to form horizontal oxide layer, isolates fin and substrate using obtained oxide layer.
In these above-mentioned structures and method, although the FinFET structures and technique of SOI substrate are simple, substrate material
Expect it is of high cost, not as body Si substrates are easily used to mass produce；On body silicon substrate note is utilized using the FinFET of PN junction isolation
Enter junction isolation, isolation effect be subject to implantation dosage, depth restriction and effect is poor, and injection technology is difficult to control, easily
Extra doping is introduced to channel region and influences device conducts performance；Horizontal selective oxidation isolation is utilized on body silicon substrate
Then complex process is with high costs by FinFET, and oxidate temperature is high, and channel region is readily incorporated extra-stress and strain so as to influence to lead
Electricity.In addition, these technologies are made during silicon fin is formed, when FinFET is manufactured using rear grid technique,
False grid form during silicon fin the isolation structure made before being formed, and insulation performance may be damaged when undergoing subsequent technique.Separately
Outside, these current silicon fin trench isolation structures are usually all along vertical-channel direction（Hereinafter referred to as X-X ' directions or
Second direction, namely the direction of grid lines extension）Upper formation, for along channel direction（Hereinafter referred to as Y-Y ' directions or
First direction, namely the direction of fin lines extension）It is between upper fin and then not perfect enough with isolating for substrate.
The content of the invention
In view of this, it is an object of the invention to provide a kind of innovative method, semi-conductor device manufacturing method, overcome above-mentioned
Problem, the miniaturization and raising for realizing device are dielectrically separated from performance.
Realize the present invention above-mentioned purpose, be by provide an a kind of method, semi-conductor device manufacturing method, including：On substrate
False grid is formed to stack；The precursor layer of side formation amorphous or polycrystalline structure is stacked in false grid；Annealing so that precursor layer turns
It is changed into the kind crystal layer of mono-crystalline structures；Kind of a crystal layer is adulterated to form source-drain area.
Wherein, substrate ETSOI, including substrate, oxygen buried layer and top layer, wherein top layer thickness are 1~5nm.
Wherein, the step of false grid stacks is formed to further comprise：Laying and sacrifice layer are formed on substrate；Etch sacrificial
Domestic animal layer and laying, until exposure substrate, forms first grid groove；Grid curb wall is formed in first grid trenched side-wall；
Filled layer is formed in first grid groove；Sacrifice layer and laying are removed, leaves false grid stacking.
Wherein, laying material includes silica, TEOS, silicon nitride, silicon oxynitride and combinations thereof；Preferably, sacrifice layer
Material includes polysilicon, non-crystalline silicon, amorphous germanium, amorphous carbon, SiGe, SiC and combinations thereof；Preferably, grid curb wall material includes
Silicon nitride, silicon oxynitride, SiOCN, SiCN, diamond-like amorphous carbon（DLC）And combinations thereof；Preferably, filled layer material bag
Include silica, TEOS, silicon oxynitride, SiOC, SiOH and combinations thereof.
Wherein, wet etching removes sacrifice layer and/or laying, is less than at the top of filled layer at the top of grid curb wall.
Wherein, precursor layer material includes Si, SiGe, SiC of amorphous or polycrystalline structure and combinations thereof.
Wherein, annealing temperature is 800~1400 degrees Celsius, preferably 1000~1300, and most preferably 1150 degrees Celsius.
Wherein, source-drain area is formed afterwards to further comprise：Part false grid is removed to stack；Stacked in source-drain area and false grid
Upper formation metal layer；Annealing is so that metal layer reacts to form metal silicide with source-drain area；Unreacted metal layer is peeled off, is continued
Remove part false grid to stack, leave second grid groove；Gate stack is formed in second grid groove.
Wherein, gate stack includes boundary layer, gate insulator, work function regulating course, resistance adjustment layer.
Wherein, second grid groove upper width is more than lower width.
According to the method, semi-conductor device manufacturing method of the present invention, the precursor layer that both sides are stacked using the false grid of fine lines is moved back
Fire forms the kind crystal layer of monocrystalline, and doping forms source-drain area, thus form ultra-thin SOI semiconductor devices, realize the small of device
Type, improves device performance.
Brief description of the drawings
Carry out the technical solution that the present invention will be described in detail referring to the drawings, wherein：
Fig. 1 to Figure 20 is the sectional view according to each step of method, semi-conductor device manufacturing method of the present invention；And
Figure 21 is the method, semi-conductor device manufacturing method indicative flowchart according to the present invention.
Embodiment
The feature and its skill for technical solution that the present invention will be described in detail referring to the drawings and with reference to schematical embodiment
Art effect.It is pointed out that the structure that similar reference numeral expression is similar, term use herein " first ", " the
Two ", " on ", " under ", " thickness ", " thin " etc. can be used for modifying various device architectures and/or manufacturing step.These modifications are unless special
Bright space, order or the hierarchical relationship for not implying that modified device architecture and/or manufacturing step is not mentionleted alone.
As shown in Figure 1, laying 2 and sacrifice layer 3 are formed on substrate 1.Substrate 1 is provided, it can be body Si, SOI, body
Ge, GeOI, SiGe, GeSb or iii-v or II-VI group compound semiconductor substrate, such as GaAs, GaN,
InP, InSb etc..In order to compatible with existing CMOS technology to be manufactured applied to large-scale digital ic, substrate 1 is preferred
Ground is the materials containing Si such as SOI or SiGe, SiGeOI.In a preferred embodiment of the invention, substrate 1 is ultra-thin SOI
（ETSOI）, including the oxygen buried layer 1B of thicker monocrystalline silicon Si substrates 1A, such as silica material and relatively thin single crystalline Si top layer
1C, wherein oxygen buried layer 1B thickness are for exampleAnd preferably, SOI top layer 1C thickness is for example（1~5nm）And preferably.The thickness of top layer 1C can pass through control（On temporary substrate）SOI
Substrate epitaxial growth parameter(s) adjusts, or after laser lift-off temporary substrate SOI top layers is thinned to obtain.Top layer
1C is by the channel region for forming device.
Then, LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxide, chemical oxidation, steaming are passed through
The techniques such as hair, sputtering sequentially form laying 2 and sacrifice layer 3 on whole chip namely on the top layer 1C of SOI substrate 1.It is preferred that
The depositing operation of good shape retention is used to form relatively thin laying 2, its material such as silica, TEOS（Using TEOS as original
Expect silica based materials prepared by CVD）, silicon nitride, silicon oxynitride etc. and combinations thereof.In a preferred embodiment, laying 2
It is silica prepared by HDPCVD.The thickness of laying 2 such as only 3~20nm.3 material example of sacrifice layer
Such as include polysilicon, non-crystalline silicon, amorphous germanium, amorphous carbon, SiGe, SiC, diamond-like amorphous carbon（DLC）Deng and combinations thereof, with
Just the Etch selectivity between the laying 2 of lower floor and following upper layer of material is improved.In a preferred embodiment of the invention
In, sacrifice layer 3 is non-crystalline silicon, thickness such as 10~50nm.
As shown in Fig. 2, the first photoetching offset plate figure PR1 is formed on sacrifice layer 3.Pass through the works such as spin coating, spraying, silk-screen printing
Skill coats photoresist layer PR on whole device, and forms the first photoetching offset plate figure using predetermined mask plate exposure, development
PR1, wherein PR1 have the opening positioned at active area immediate vicinity to expose sacrifice layer 3, for limiting the position of grid in future.
As shown in figure 3, using the first photoetching offset plate figure PR1 as mask, etching sacrificial layer 3 is to form groove 3G, until exposure
Laying 2.Material difference according to sacrifice layer 3 can select various anisotropic lithographic methods, such as plasma dry
Etching, reactive ion etching（RIE）Or tetramethylammonium hydroxide（TMAH）Wet etching etc..Preferably, formed groove 3G it
The first photoetching offset plate figure PR1 is removed by dry method or wet processing afterwards.
As shown in figure 4, the laying 2 of exposure in groove 3G is removed, until the top layer 1C of exposure ETSOI substrates 1.For lining
The material of bed course 2, preferably anisotropic etching technics, such as plasma dry etch or RIE.When laying 2 with it is sacrificial
Domestic animal layer 3, top layer 1C materials compared to when there is higher Etch selectivity, can also selective wet etching technique, such as sacrifice layer 3
Be monocrystalline silicon for non-crystalline silicon, top layer 1C, laying 2 is when being silica, HF base corrosive liquids can be selected（DHF, dBOE etc.）.
As shown in figure 5, spacer material layer 4 is formed on groove 3G bottoms and side wall and sacrifice layer 3.Such as pass through
The techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, magnetron sputtering formation material is harder, relatively causes
Close spacer material layer 4, its material such as silicon nitride（SiN）, silicon oxynitride（SiiOxNy, wherein nitrogen oxygen ratio is more than 1.5:1 and excellent
Choosing is more than or equal to 2:1）, SiOCN, SiCN, DLC etc. and combinations thereof.4 thickness of spacer material layer such as only 1~5nm.At this time, layer 4
Groove 3G is not filled up completely, but only covers bottom and side wall.
As shown in fig. 6, etch layer 4, grid curb wall 4S is left in groove 3G side walls.It is preferred that isotropic dry etching,
Adjust etching gas composition（Such as the carbon fluorine ratio in the fluorine-based etching gas of carbon）So that vertical direction etch rate is noticeably greater than water
Square to etch rate（Such as ratio between two is more than 5:1 and preferably 10:1）, eliminate the top of sacrifice layer 3 and groove 3G bottoms
The portion of material layer 4 at the top of laying 2, exposes laying 2, leaves grid curb wall 4S again, its width is equal to or smaller
In the thickness of spacer material layer 4.
As shown in fig. 7, filled layer 5 is formed in groove 3G and on sacrifice layer 3.Fill process such as LPCVD, PECVD,
HDPCVD, MOCVD, MBE, ALD etc., and preferably high depth ratio（HARP）Depositing operation.5 material of filled layer for example aoxidizes
Silicon, TEOS（The silica based materials prepared using TEOS as raw material CVD, the usual abbreviation TEOS of industry）, silicon oxynitride（Nitrogen oxygen is than small
In 2:1）, SiOC, SiOH etc. and combinations thereof.Depth of 5 thickness of filled layer at least above groove 3G（Namely the thickness of sacrifice layer 3
Degree）.
As shown in figure 8, using CMP, return and carve（etch-back）Etc. technique planarization filled layer 5 until exposure sacrifice layer 3.
At this time, the top of sacrifice layer 3, grid curb wall 4S tops are flushed with 5 top three of filled layer, namely in same level.
As shown in figure 9, selective etch removes sacrifice layer 3, exposure laying 2.For the material of sacrifice layer 3, etching choosing
The high technique of selecting property, for example, when sacrifice layer 3 for polysilicon, non-crystalline silicon when material containing Si when can select TMAH wet etchings, when
Sacrifice layer 3 is SiGe, SiC, amorphous carbon, amorphous germanium can select strong oxidizer when other materials（Ozone, hydrogen peroxide）With it is strong
Acid（Sulfuric acid, nitric acid）Mixing removes.In addition it is also possible to using plasma dry etching or RIE, and adjust etching gas
Content（Such as the carbon fluorine of the fluorine-based etching gas of carbon is than that can control for the quarter between silicon nitride-based material and silica based materials
Erosion selectivity）So that the basic only longitudinal direction of etching is directed to sacrifice layer 3, and does not corrode laying 2 and grid curb wall 4S substantially.Etching
Gas such as carbon is fluorine-based（CxHyFz, x are that 1~4, y is that 0~4, z is 1~8, and triadic relation meets so that forming saturation or not
The fluorohydrocarbon of saturation）Gas, by adjusting carbon fluorine than controlling etching rate so as to obtaining steep pattern.For example, etching gas
It can include CF4、CH3F、CHF3、CH2F2、C4F8、C4F6Deng and combinations thereof and into one by one step include O2, the oxidizing gas such as CO
To adjust etch rate.Etching terminal can be by controlling etch rate and etch period to adjust, or detection etch intracavitary
Reaction product material, content determine.
As shown in Figure 10, selective etch removes laying 2.It is similar with step shown in Fig. 9, HF base corrosive liquids can be used
The laying 2 of silica based materials is removed, or adjustment etching gas composition carrys out dry etching laying 2, until exposure ETSOI
The ultra-thin top layer 1C of substrate 1, thus only leaves the filled layer 5 that grid curb wall 4S is surrounded on substrate 1.At this time, etching technics
Also the top of filled layer 5 can be slightly corroded, hence in so that the top of grid curb wall 5S is slightly above the top of 5 remainder of filled layer
Portion.
Figure 1 above to the step of Figure 10, shows that false grid is formed on ETSOI substrate top layers 1C to be stacked（By grid curb wall
4S and filled layer 5 are formed）Process, but this can be formed using different processing steps in other embodiments of the present invention
False grid stacks.For example, in substrate（The ETSOI substrates different from the preferred embodiment of the present invention can be used, but are used common
Body Si or thick SOI substrate）Upper formation false grid material layer（It is identical with 5 material of filled layer）, etching false grid material layer with
Form false grid figure（5 syntype of filled layer surrounded with grid curb wall 4S）, grid curb wall 4S is formed around false grid figure.
The processing step of Fig. 1 to Figure 10 is that being not intended to the restriction present invention can in order to improve the fineness of false grid lines into step one by one
With the other modes of implementation.
As shown in figure 11, precursor layer 6 is formed on whole device.Such as by LPCVD, PECVD, HDPCVD, UHVCVD,
The techniques such as MOCVD, MBE, ALD, evaporation, sputtering form precursor layer 6, completely covers top layer 1C, the gate electrode side of ETSOI substrates 1
Wall 4S and filled layer 5.The material of precursor layer 6 is preferably close with the top layer 1C materials of single crystalline Si（Such as lattice constant is close）,
Such as non-crystalline silicon, polysilicon,（Monocrystalline, non-crystalline silicon or polysilicon）SiGe、（Monocrystalline, non-crystalline silicon or polysilicon）SiC etc. and
It is combined.In present invention preferred embodiment a one by one, low temperature is prepared using LPCVD or PECVD under 450 degrees Celsius
Non-crystalline silicon is for use as precursor layer 6.At this time, as shown in figure 11,6 top surface of precursor layer is higher than at the top of grid curb wall 4S and into walking one by one
Higher than the top of filled layer 5.
As shown in figure 12, using technique planarization precursor layers 6 such as CMP, time quarters until what exposure grid curb wall 4S was surrounded
Filled layer 5.Since filled layer 5 is less than grid curb wall 4S in Figure 10, the flatening process shown in Figure 12 exposes grid first
Side wall 4S, then further planarizes until exposure filled layer 5.
As shown in figure 13, anneal, the lattice structure of adjustment precursor layer 6 makes it further be close to the monocrystalline silicon of top layer 1C
Si, such as it is changed into the kind crystal layer of monocrystalline, for use as the active area of device.In one embodiment of the invention, precursor layer 6 is
Non-crystalline silicon, therefore annealing causes non-crystalline silicon precursor layer 6 to be changed into monocrystalline preferably under 1000~1300 and preferably 1150 degrees Celsius
The kind crystal layer 6 ' of silicon.In other embodiments of the present invention, precursor layer 6 is the compound containing Si such as SiGe, SiC, can 800~
Annealing causes non-crystalline silicon, the layer 6 of polysilicon to be changed into the kind crystal layer 6 ' of mono-crystalline structures under 1400 degree celsius temperatures, these monocrystalline
SiGe, SiC layer can apply stress to improve carrier mobility to channel region.
It is initially formed amorphous or polycrystalline precursor layer 6 furthermore it is noted that although Figure 11 to Figure 13 is shown and moves back
Fire is changed into the kind crystal layer 6 ' of monocrystalline, but can also in deposition, sputter procedure progressively adjusting process parameter so that a step shape
Into the kind crystal layer 6 ' of monocrystalline.For example, epitaxy technique is performed, directly using the top layer 1C of monocrystalline as seed（seed）Epitaxial growth monocrystalline
The kind crystal layer 6 ' of Si, SiGe or SiC of structure for use as device active area.
As shown in figure 14, injection doping is performed to the kind crystal layer 6 ' of mono-crystalline structures, source region 6S and leakage is formed in active area
Area 6D.The dopant of injection is such as including Li, B, C, N, F, P, As, Be, Si, Ge, In, Ga and combinations thereof, Implantation Energy example
Such as 1~20KeV, implantation dosage such as 1E13~5E16cm-2.Then, annealing is performed under 400~750 degrees Celsius to mix to activate
Miscellaneous dose.In addition it is also possible to form source-drain area in extension forming layer 6 ' while doping in situ.At this time, due to filled layer 5 and gate electrode side
The stop of wall 4S, does not have dopant in top layer 1C below, and may have in the top layer 1C below source-drain area 6S/D
Lighter doping concentration（By controlling Implantation Energy to obtain）, so that the top layer of the lower section of filled layer 5 and grid curb wall 4S
1C constitutes the channel region 1CH of device.
As shown in figure 15, part removes filled layer 5, to expose groove 3G again.It is preferred that anisotropic etching technics, example
Such as plasma dry etch, RIIE.Selected in addition it is also possible to be directed to the characteristics of filled layer 5 is different from surrounding structure material
Wet etching.By controlling etch period, etch rate to adjust etch-stop stop so that in groove 3G still remain part
Filled layer 5, the 1/5~1/3 of its residual thickness such as source-drain area 6S/6D thickness.
As shown in figure 16, gold is formed by techniques such as MOCVD, PECVD, MBE, ALD, evaporation, sputterings on whole device
Belong to layer 7, its material is Ni, Pt, Co, Ti, Ta and combinations thereof.
As shown in figure 17, anneal 10ms~5min under 450~850 degrees Celsius so that metal layer 7 and kind crystal layer 6 '/source
Si in drain region 6S, 6D reacts to form metal silicide 8.At this time, due to grid curb wall 4S, nitride, the oxygen that filled layer 5 is Si
The structure types such as compound, can not discharge single Si and metal reaction, therefore the top of filled layer 5 can not form metal in groove 3G
Silicide 8.Unreacted metal layer 7 is then peeled off, metal silicide 8 is only left on source-drain area.According to Figure 16,17,
Metal layer 7 can react the kind crystal layer 6 ' or source-drain area 6S/6D of the mono-crystalline structures of consumption part, therefore plant crystal layer 6 ' in fig. 17
Or source-drain area thickness reduces.
As shown in figure 18, remaining filled layer 5 is removed, until exposed top layer 1C, leaves gate trench.The etching of use is gone
Except technique is similar with shown in Figure 15, and preferably use dHF（Dilute HF acid）Or dBOE（Dilution sustained release etching liquid, HF with
The mixed solution of NH4F）Erosion removal aoxidizes the filled layer 5 of silicon substrate matter.At this time, due to grid curb wall 4S and the part left
Filled layer 5 is the oxide or nitride form of Si, can not react to form metal silicide, therefore peels off the ditch left afterwards
Channel opening is T-type structure, namely upper width is greater than lower width, this is conducive to improve filling during gate stack filling later
Rate, reduction eliminate hole.
Although Figure 15~Figure 18 shows that first part removes filled layer, forms metal silicide and removes filling completely again afterwards
Layer, this step will improve filling rate, reduction or eliminate hole.But when groove, opening size are larger（Such as 45nm with
On, or more than 22nm）When, deposited metal layer 7 and it can also be moved back directly on source-drain area 6 ' after injection forms source-drain area
Fire forms metal silicide 8, and simply gate trench opening at this time is vertical side wall structure without T-shaped shape wide at the top and narrow at the bottom
Looks.
As shown in figure 19, gate stack is formed in gate trench.Preferably, existed by chemical oxidation or thermal oxide
At the top of gate trench and side wall forms ultra-thin boundary layer 9A, such as silica material, for reducing section defect.Then,
Using the techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxide, chemical oxidation, evaporation, sputtering according to
It is secondary to fill gate insulator 9B, work function regulating course 9C, resistance adjustment layer 9D in gate trench bottom and side wall.Gate insulator
9B is high-g value, including but not limited to includes being selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、
HfAlSiOx、HfLaSiOxHafnium sill（Wherein, each material is different according to multi-element metal component proportion and chemical valence, and oxygen is former
Sub- content x can be adjusted rationally, be may be, for example, 1~6 and be not limited to integer）, or including selected from ZrO2、La2O3、LaAlO3、TiO2、
Y2O3Rare-earth-based high K dielectric material, or including Al2O3, with the composite bed of its above-mentioned material.Work function regulating course 9C materials
For MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.Resistance adjustment layer 9D
Material can be polysilicon, poly-SiGe or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta,
The nitride of the metal simple-substances such as Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or the alloy of these metals and these metals, in addition
Can also be doped with elements such as C, F, N, O, B, P, As with into step section work function one by one.
As shown in figure 20, carry out CMP, return the techniques such as quarter with planarized gate stacking 9（9A~9D）Until exposing metal silicon
Compound 8 or grid curb wall 4S.Then, device manufacture further can be completed using various conventional process.Such as sink on device
Interlevel dielectric layer（ILD）, etching forms contact hole to expose source-drain area 6 or metal silicide 8, in contact hole in ILD
Middle formation metal silicide fills metal material formation contact plug to reduce contact resistance on metal silicide.
According to the method, semi-conductor device manufacturing method of the present invention, the precursor layer that both sides are stacked using the false grid of fine lines is moved back
Fire forms the kind crystal layer of monocrystalline, and doping forms source-drain area, thus form ultra-thin SOI semiconductor devices, realize the small of device
Type, improves device performance.
Although with reference to an one or more exemplary embodiment explanation present invention, those skilled in the art could be aware that nothing
The scope of the invention need to be departed from and various suitable changes and equivalents are made to the method for formation device architecture.In addition, by institute
Disclosed teaching, which can make many, can be adapted to the modification of particular condition or material without departing from the scope of the invention.Therefore, this hair
Bright purpose, which is not lain in, to be limited to as the preferred forms for being used for realization the present invention and disclosed specific embodiment, and institute is public
The device architecture opened and its manufacture method are by all embodiments including falling within the scope of the present invention.
Claims (15)
1. a kind of method, semi-conductor device manufacturing method, including：
False grid is formed on substrate to stack；
The precursor layer of side formation amorphous or polycrystalline structure is stacked in false grid, precursor layer stacks top with false grid and flushes；
Annealing so that precursor layer is changed into the kind crystal layer of mono-crystalline structures；
Kind of a crystal layer is adulterated to form source-drain area.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, substrate ETSOI, including substrate, oxygen buried layer and top layer,
Wherein top layer thickness is 1~5nm.
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, form the step of false grid stacks and further comprise：
Laying and sacrifice layer are formed on substrate；
Etching sacrificial layer and laying, until exposure substrate, forms first grid groove；
Grid curb wall is formed in first grid trenched side-wall；
Filled layer is formed in first grid groove；
Sacrifice layer and laying are removed, leaves false grid stacking.
4. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, laying material include silica, TEOS, silicon nitride,
Silicon oxynitride and combinations thereof.
5. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, sacrifice layer material includes polysilicon, non-crystalline silicon, amorphous
Germanium, amorphous carbon, SiGe, SiC and combinations thereof.
6. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, grid curb wall material include silicon nitride, silicon oxynitride,
SiOCN, SiCN, diamond-like amorphous carbon (DLC) and combinations thereof.
7. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, filled layer material includes silica, TEOS, nitrogen oxidation
Silicon, SiOC, SiOH and combinations thereof.
8. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, wet etching removes sacrifice layer and/or laying, filling
Layer top is less than at the top of grid curb wall.
9. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, precursor layer material includes amorphous or polycrystalline structure
Si, SiGe, SiC and combinations thereof.
10. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, annealing temperature is 800~1400 degrees Celsius.
11. such as method, semi-conductor device manufacturing method of claim 10, wherein, annealing temperature is 1000~1300 degrees Celsius.
12. such as method, semi-conductor device manufacturing method of claim 11, wherein, annealing temperature is 1150 degrees Celsius.
13. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, form source-drain area and further comprise afterwards：
Part false grid is removed to stack；
In source-drain area and the stacked on formation metal layer of false grid heap；
Annealing is so that metal layer reacts to form metal silicide with source-drain area；
Unreacted metal layer is peeled off, continues to remove part false grid stacking, leaves second grid groove；
Gate stack is formed in second grid groove.
14. such as method, semi-conductor device manufacturing method of claim 13, wherein, gate stack includes boundary layer, gate insulator, work(
Function regulating course, resistance adjustment layer.
15. such as method, semi-conductor device manufacturing method of claim 13, wherein, it is wide that second grid groove upper width is more than lower part
Degree.
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| US9716158B1 (en) | 2016-03-21 | 2017-07-25 | International Business Machines Corporation | Air gap spacer between contact and gate region |
| US11081358B2 (en) * | 2018-07-05 | 2021-08-03 | Applied Materials, Inc. | Silicide film nucleation |
| US11164867B2 (en) * | 2019-08-07 | 2021-11-02 | Globalfoundries U.S. Inc. | Fin-type field-effect transistors over one or more buried polycrystalline layers |
| CN115849297A (en) * | 2022-12-27 | 2023-03-28 | 上海铭锟半导体有限公司 | Preparation method of MEMS cavity |
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