CN104167358B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
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- CN104167358B CN104167358B CN201310184801.3A CN201310184801A CN104167358B CN 104167358 B CN104167358 B CN 104167358B CN 201310184801 A CN201310184801 A CN 201310184801A CN 104167358 B CN104167358 B CN 104167358B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000001301 oxygen Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 123
- 239000000463 material Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 4
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
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- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
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- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005872 GeSb Inorganic materials 0.000 description 1
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of method, semi-conductor device manufacturing methods, including：SOI substrate, including substrate, oxygen buried layer and top layer are provided；Etching forms gate trench in top layer；Laying and filled layer are formed in gate trench；Filled layer, laying and top layer are etched, the opening of exposure oxygen buried layer is formed, the top layer in opening constitutes active area, the top layer constituting channel area of gate trench bottom；Fill insulant forms shallow trench isolation in the opening.According to the method, semi-conductor device manufacturing method of the present invention, etching forms gate trench and defines the channel region of lower section in SOI top layers, limits active area and shallow trench isolation after filling gate trench, thus forms ultra-thin SOI semiconductor devices, the miniaturization for realizing device, improves device performance.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly, to silicon on a kind of ultrathin insulating body
(ETSOI) manufacturing method of transistor.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture,
This structure enhances grid control ability, inhibits electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure can inhibit short compared with traditional single grid body Si or SOI MOSFET
Channelling effect (SCE) and leakage cause induced barrier to reduce (DIBL) effect, have lower junction capacity, can realize that raceway groove is gently mixed
Miscellaneous, work function that can be by the way that metal gates are arranged can obtain about 2 times of driving current, reduce come adjusting threshold voltage
Requirement for effective gate oxide thickness (EOT).And tri-gate devices are compared with double-gated devices, grid enclose channel region top surface and
Two sides, grid control ability are stronger.Further, loopful is more advantageous around nano wire multi-gate device.These devices by
It is small in size, complicated, it is easy to interfere with each other between adjacent raceway groove, therefore the isolation technology of raceway groove becomes increasingly to weigh
It wants.
Existing FinFET structure and manufacturing method include：1) FinFET of SOI substrate is carved using masks such as photoresists
SOI substrate is lost, is automatically stopped on oxygen buried layer, remaining top silicon layer forms fin, and since oxygen buried layer can insulate well
Adjacent fin is isolated, there is no need to additional processing steps or structure to carry out isolation channel；2) body substrate of junction isolation
FinFET forms groove and fin using mask etching body silicon substrate, fill oxide is deposited in the groove between fin
It is laterally dielectrically separated from adjacent fin, subsequent angle-tilt ion injects high dose dopant, is formed in fin bottom different from top
Note people's doped region of conduction type, is isolated fin and substrate using PN junction；3) the body substrate FinFET being isolated based on material,
Groove and fin are formed using mask etching body substrate, deposition oxide is to be laterally isolated in the groove between fin, in fin
Piece side forms the side walls such as nitride to provide protection, executes thermal oxide so that not by the fin bottom part of side wall protection or
Person is all aoxidized so that be connected with each other to form lateral oxide layer, and fin and substrate is isolated using obtained oxide layer.
In these above-mentioned structures and method, although the FinFET structures of SOI substrate and simple for process, substrate material
Expect it is of high cost, not as good as body Si substrates are easily used to mass produce；On body silicon substrate note is utilized using the FinFET of PN junction isolation
Enter junction isolation, isolation effect by implantation dosage, depth restriction and effect is poor, and injection technology is difficult to control, and is easy
Additional doping is introduced to channel region and influences device conducts performance；Lateral selective oxidation isolation is utilized on body silicon substrate
Then complex process is with high costs by FinFET, and oxidate temperature is high, and channel region is readily incorporated extra-stress and strain to influence to lead
Electricity.In addition, these technologies are made during forming silicon fin, when FinFET is manufactured using rear grid technique,
False grid form the isolation structure made during silicon fin before being formed, insulation performance may be damaged when undergoing subsequent technique.Separately
Outside, these current silicon fin trench isolation structures be usually all along vertical-channel direction (hereinafter referred to as the directions X-X' or
Direction that second direction namely grid lines extend) on formed, for along channel direction (hereinafter referred to as the directions Y-Y ' or
The direction that first direction namely fin lines extend) on it is between fin and then incomplete with being isolated for substrate.
Invention content
In view of this, the purpose of the present invention is to provide a kind of method, semi-conductor device manufacturing methods of novelty, by SOI
Etching forms gate trench to reduce element height to realize miniaturization in substrate top layer, and is masked-deposition using filled layer
Shallow trench isolation is formed to improve device isolation isolation performance.
The above-mentioned purpose for realizing the present invention, be by providing a kind of method, semi-conductor device manufacturing method, including：SOI linings are provided
Bottom, including substrate, oxygen buried layer and top layer；Etching forms gate trench in top layer；Laying is formed in gate trench and is filled out
Fill layer；Filled layer, laying and top layer are etched, the opening of exposure oxygen buried layer is formed, the top layer in opening constitutes active area, grid
The top layer constituting channel area of pole channel bottom；Fill insulant forms shallow trench isolation in the opening.
Wherein, 80~200nm of oxygen buried layer thickness, 30~100nm of top layer thickness.
Wherein, laying material includes that silica, TEOS, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like are amorphous
Carbon (DLC) and combinations thereof, thickness are 5~30nm；Filled layer material include silicon nitride, amorphous carbon, DLC, polysilicon, monocrystalline silicon,
Non-crystalline silicon, polycrystal SiGe, polycrystalline Si C and combinations thereof, thickness are 20~50nm.
Wherein, the channel region thickness that the top layer of gate trench bottom is constituted is 1~20nm.
Wherein, shallow trench isolation is formed later to further comprise：Shallow trench, filled layer are planarized until exposure laying；
Doping is injected to the top layer of both sides using filled layer as mask, forms source-drain area；Filled layer is removed, exposes gate trench again；
Gate stack is formed in gate trench.
Wherein, gate stack includes the boundary layer of oxide material, the gate insulating layer of high-g value, nitride material
Work function regulating course and resistance adjustment layer.
Wherein, wet etching removes filled layer.
Wherein, the laying of removal gate trench bottom retains laying for use as gate electrode side in gate trench sidewalls
Wall.
Wherein, gate stack is formed later to further comprise：Interlayer dielectric layer is formed on device；Etch interlayer dielectric layer
Form the contact hole of exposure source-drain area；Metal silicide is formed in the contact hole；Contact plug is formed on metal silicide.
The present invention also provides a kind of semiconductor devices, including：Substrate has substrate, oxygen buried layer and top layer；Grid pile
It is folded, it is located in the active area in top layer；Channel region is located in top layer below gate stack；Source-drain area is located at grid pile in top layer
Folded both sides；Shallow trench isolation is located at outside the active area in top layer.
According to the method, semi-conductor device manufacturing method of the present invention, under etching forms gate trench and defines in SOI top layers
The channel region of side, filling gate trench limit active area and shallow trench isolation, thus form ultra-thin SOI semiconductor device later
Part realizes the miniaturization of device, improves device performance.
Description of the drawings
Carry out the technical solution that the present invention will be described in detail referring to the drawings, wherein：
Fig. 1 to Figure 14 is the sectional view according to each step of method, semi-conductor device manufacturing method of the present invention.
Specific implementation mode
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect.It should be pointed out that similar reference numeral indicates similar structure, term use herein " first ", "
Two ", "upper", "lower", " thickness ", " thin " etc. can be used for modifying various device architectures and/or manufacturing step.These modifications are unless special
The bright space for not implying that modified device architecture and/or manufacturing step, order or hierarchical relationship are not mentionleted alone.
As shown in Figure 1, providing substrate 1, it can be body Si, SOI, body Ge, GeOI, SiGe, GeSb, can also be III-
V races or II-VI group compound semiconductor substrate, such as GaAs, GaN, InP, InSb etc..In order to existing CMOS technology
Compatible to be manufactured with being applied to large-scale digital ic, substrate 1 is preferably the material containing Si such as SOI or SiGe, SiGeOI.
In a preferred embodiment of the invention, substrate 1 includes thicker monocrystalline silicon Si substrates 1A, such as aoxidizes the oxygen buried layer of silicon material
1B and relatively thin single crystalline Si top layer 1C, wherein oxygen buried layer 1B thickness are for exampleAnd preferably
SOI top layer 1C thickness is for exampleAnd preferably
As shown in Fig. 2, forming the first photoetching offset plate figure PR1 on substrate 1 (especially SOI top layer 1C).Pass through spin coating, spray
The techniques such as painting, silk-screen printing coat photoresist layer PR on entire device, and form the using the exposure of scheduled mask plate, development
One photoetching offset plate figure PR1, wherein PR1 have the opening positioned at active area immediate vicinity to expose 1 top layer 1C of substrate, for limiting
Future gate trench position.
As shown in figure 3, using the first photoetching offset plate figure PR1 as mask, the top layer 1C of etched substrate 1 is to form gate trench
1G.Various anisotropic lithographic methods can be selected according to the material difference of top layer 1C, such as plasma dry etch, anti-
Answer ion etching (RIE) or tetramethylammonium hydroxide (TMAH) wet etching etc..Depth (bottom and the top of gate trench 1G
The distance between portion) be less than SOI substrate 1 top layer 1C thickness, namely at least there are a part for top layer bottom for will
The channel region 1CH come.In a preferred embodiment of the invention, (namely the channel region of remaining top layer 1C below gate trench 1G
Thickness 1CH) isPreferably, it is formed after gate trench 1G through dry method or wet processing removal the
One photoetching offset plate figure PR1.
As shown in figure 4, forming laying 2 in gate trench 1G and on top layer 1C.Such as by LPCVD, PECVD,
The techniques such as HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxide, chemical oxidation, evaporation, sputtering form laying 2 to cover
The side wall of gate trench 1G and bottom, and the top of the top layer 1C of SOI substrate 1 is also covered simultaneously.It is preferred that using conformality
To form relatively thin laying 2, material such as silica, TEOS (are prepared using TEOS as raw material CVD good depositing operation
Silica based materials), silicon nitride, silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC) etc. and combinations thereof.It is excellent at one
It selects in embodiment, laying 2 is silica prepared by HDPCVD.The thickness of laying 2 is for example only
As shown in figure 5, forming filled layer 3 in remaining gate trench 1G.By LPCVD, PECVD, HDPCVD,
The techniques such as UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering form filled layer 3 on laying 2, completely fill remaining grid
Pole groove and cover the laying 2 at the top of 1 top layer 1C of substrate.Filled layer 3 preferably has higher etching selection with laying 2
Property material, such as when laying 2 select silica based materials when, filled layer 3 select silicon nitride, amorphous carbon, DLC, polysilicon,
The materials such as monocrystalline silicon, non-crystalline silicon, polycrystal SiGe, polycrystalline Si C, vice versa.It is preferred that the techniques such as PECVD, HDPCVD are to improve ditch
Slot filling rate.It is worth noting that, filled layer 3 will form small protrusion on the position of original gate trench 1G, this be by
Material layer first engages and the top engaged later of having arched upward at bottom, middle part when filling groove.3 thickness of filled layer is for example
As shown in fig. 6, forming the second photoetching offset plate figure PR2 on filled layer 3.It is similar with PR1, it is formed after photoresist layer
Exposure, development form PR2, cover the active area of future device, only active region there are opening portion with exposure fill out
Fill layer 3.In top view (not shown), PR2 by be had that cyclic annular or frame-shaped is open cover active area central part
Figure, according to Butut wiring need its can be rectangle, circle, ellipse, polygon etc..
As shown in fig. 7, using PR2 as mask, filled layer 3, laying 2 and the top layer 1C being sequentially etched in exposure opening,
Until the oxygen buried layer 1B of exposure SOI substrate 1.Etching preferably anisotropic technique, such as plasma dry etch, RIE etc..
Etching gas such as carbon it is fluorine-based (it be 0~4, z is 1~8 that CxHyFz, x, which are 1~4, y, triadic relation meet so that constitute saturation or
The undersaturated fluorohydrocarbon of person) gas, by adjusting carbon fluorine this come the pattern that controls etching rate to obtain steep.For example, etching
Gas may include CF4、CH3F、CHF3、CH2F2、C4F8、C4F6Deng and combinations thereof and further comprise O2, the oxidisability gas such as CO
Body is to adjust etch rate.Etching terminal can be adjusted by controlling etch rate and etch period or detection etch chamber
Interior reaction product material, content determine.
As shown in figure 8, forming dielectric isolation layer 4 on entire device.By LPCVD, PECVD, HDPCVD, UHVCVD,
The techniques such as MOCVD, MBE, ALD, thermal oxide, chemical oxidation, evaporation, sputtering form dielectric isolation layer 4, completely cover filled layer
3 and active area outside opening portion.4 material of dielectric isolation layer is preferably the oxides such as silica, TEOS.
As shown in figure 9, using the techniques planarization such as CMP, time quarter dielectric isolation layer 4, filled layer 3 up to exposing laying 2,
It eliminates the part of the dielectric isolation layer 4 at 3 top of filled layer and only leaves dielectric isolation layer 4 in active region for use as shallow ridges
(STI) is isolated in slot.
As shown in Figure 10, source and drain doping is carried out, to form source-drain area 1S/1D in the top layer 1C of 3 both sides of filled layer.Such as
Ion implanting is carried out, makes ion pass through relatively thin laying 2 to enter in top layer 1C by controlling Implantation Energy and dosage.Note
The dopant entered such as including Li, B, C, N, F, P, As, Be, Si, Ge, In, Ga and combinations thereof, Implantation Energy such as 1~
20KeV, implantation dosage such as 1E13~5E16cm-2.At this point, due to the blocking of filled layer 3, injection ion fails to go deep into lower section
In channel region 1CH.
As shown in figure 11, selective removal filled layer 3 exposes gate trench 1G again.It is selected for the material of filled layer 3
Lithographic method is selected, such as hot phosphoric acid wet etching removes silicon nitride material, HF bases corrosive liquid (dHF, dBOE etc.) wet method goes deoxygenation
SiClx sill (when laying 2 below is not silica material), oxygen plasma dry etching removes amorphous carbon, DLC
Etc. materials, TMAH wet etchings polysilicon, non-crystalline silicon etc., strong oxidizer (ozone, hydrogen peroxide) mixed with strong acid (sulfuric acid, nitric acid)
Remove SiGe, SiC etc..Selective etch technique does not corrode laying 2 entirely or substantially, protects source-drain area and channel region.
At this point, the bottoms gate trench 1G still have laying 2.
Preferably, as shown in figure 12,2 bottom of etching laying is to expose channel region 1CH, while having also been removed the tops top layer 1C
The portions of pads layer 2 in portion.Such as the laying 2 of the bottoms gate trench 1G is removed by dry etching, and remained in side wall
Portions of pads layer 2 for use as device grid curb wall.In addition it is also possible to using wet etching, such as HF base corrosive liquids go deoxygenation
SiClx, control corrosion rate liquid match this and etching temperature so that the etch rate of side wall is apparently higher than for the etch rate of bottom
(the two etch rate this be preferably greater than 5：1).In addition, when laying 2 is thermal oxide either chemical oxidation or HDPCVD technique
When very thin (1~5nm) oxidation silicon material formed, 2 part of laying of the bottoms gate trench 1G can not also be removed, and should
Laying 2 is used as the boundary layer between high-g value gate insulating layer and channel region 1CH later to reduce section defect.
As shown in figure 13, gate stack 5 is formed in gate trench 1G.Preferably, pass through chemical oxidation or thermal oxide
At the top of gate trench 1G and side wall forms ultra-thin boundary layer 5A, for example, oxidation silicon material (when laying 2 is also relatively thin, example
When such as 1~5nm, it is convenient to omit layer 5A；Or when laying 2 is thicker be greater than 5nm when, can preferably use Figure 12 shown in work
Skill part removes or the layer 2 of thinned channel bottom, is formed simultaneously a layer 5A).Then, using LPCVD, PECVD, HDPCVD,
The techniques such as UHVCVD, MOCVD, MBE, ALD, thermal oxide, chemical oxidation, evaporation, sputtering are successively in the bottoms gate trench 1G and side
Wall fills gate insulating layer 5B, work function regulating course 5C, resistance adjustment layer 5D.Gate insulating layer 5B is high-g value, including but not
It is limited to include being selected from Hf02、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnium sill
(wherein, each material distributes this according to multi-element metal group and chemical valence is different, and oxygen atom content x can be adjusted rationally, be may be, for example,
1~6 and be not limited to integer), or including be selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare-earth-based high K dielectric material, or
It includes Al to be2O3, with the composite layer of its above-mentioned material.Work function regulating course 5C materials are MxNy、MxSiyNz、MxAlyNz、
MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.Resistance adjustment layer 5D materials can be polysilicon, polycrystalline germanium
Silicon or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er,
The nitride of the alloy and these metals of the metal simple-substances such as La or these metals, additionally can doped with C, F, N, O, B, P,
The elements such as As are further to adjust work function.
As shown in figure 14, it carries out CMP, return the techniques such as quarter with planarized gate 4 (4A~4D) of stacking until exposure SOI substrate
Top layer 1C.Then, various conventional process can be further used to complete device manufacture.Such as the interlayer dielectric on device
Layer (ILD), etching forms contact hole to expose source-drain area in ILD, forms metal silicide in the contact hole to reduce contact
Resistance fills metal material formation contact plug on metal silicide.
Last device is as shown in figure 14, including grid in SOI substrate, the gate stack in SOI substrate top layer, substrate top layer
Pole stacks the source-drain area of gate stack both sides in the channel region of lower section, substrate top layer.Wherein, all parts material and corresponding
Technological parameter is described in detail in method flow, and details are not described herein.
According to the method, semi-conductor device manufacturing method of the present invention, under etching forms gate trench and defines in SOI top layers
The channel region of side, filling gate trench limit active area and shallow trench isolation, thus form ultra-thin SOI semiconductor device later
Part realizes the miniaturization of device, improves device performance.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to the method for forming device architecture.In addition, public by institute
The introduction opened, which can make many, can be adapted to the modification of particular condition or material without departing from the scope of the invention.Therefore, of the invention
Purpose do not lie in and be limited to as the preferred forms for realizing the present invention and disclosed specific embodiment, and it is disclosed
Device architecture and its manufacturing method will be including falling all embodiments in people's scope of the invention.
Claims (8)
1. a kind of method, semi-conductor device manufacturing method, including：
SOI substrate, including substrate, oxygen buried layer and top layer are provided；
Etching forms gate trench in top layer；
Laying and filled layer are formed in gate trench；
Filled layer, laying and top layer are etched, the opening of exposure oxygen buried layer is formed, the top layer in opening constitutes active area, grid
The top layer constituting channel area of pole channel bottom；
Fill insulant forms shallow trench isolation in the opening；
Shallow trench, filled layer are planarized until exposure laying；
Doping is injected to the top layer of both sides using filled layer as mask, forms source-drain area；
Filled layer is removed, exposes gate trench again, is wherein flushed at the top of source-drain area and gate trench；
Gate stack is formed in gate trench.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein oxygen buried layer 80~200nm of thickness, top layer thickness 30~
100nm。
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein laying material include silica, TEOS, silicon nitride,
Silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC) and combinations thereof, thickness are 5~30nm；Filled layer material includes nitrogen
SiClx, amorphous carbon, DLC, polysilicon, monocrystalline silicon, non-crystalline silicon, polycrystal SiGe, polycrystalline Si C and combinations thereof, thickness are 20~50nm.
4. method, semi-conductor device manufacturing method as claimed in claim 1, wherein the channel region thickness that the top layer of gate trench bottom is constituted
For 1~20nm.
5. method, semi-conductor device manufacturing method as claimed in claim 1, wherein gate stack includes the boundary layer of oxide material, high k
The gate insulating layer of material, the work function regulating course of nitride material and resistance adjustment layer.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein wet etching removes filled layer.
7. method, semi-conductor device manufacturing method as claimed in claim 1, wherein the laying of removal gate trench bottom, in grid ditch
Retain laying in groove sidewall for use as grid curb wall.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein form gate stack and further comprise later：
Interlayer dielectric layer is formed on device；
Etching interlayer dielectric layer forms the contact hole of exposed source-drain area；
Metal silicide is formed in the contact hole；
Contact plug is formed on metal silicide.
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