CN102420185A - Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) - Google Patents
Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) Download PDFInfo
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- CN102420185A CN102420185A CN2010102993487A CN201010299348A CN102420185A CN 102420185 A CN102420185 A CN 102420185A CN 2010102993487 A CN2010102993487 A CN 2010102993487A CN 201010299348 A CN201010299348 A CN 201010299348A CN 102420185 A CN102420185 A CN 102420185A
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Abstract
The invention discloses a manufacturing method of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor). The manufacturing method comprises the following steps of: providing a semiconductor substrate comprising a first doping region and a second doping region; forming a first metal gate on the first doping region; forming a second sacrifice gate structure on the second doping region; forming a dielectric protection layer around the first metal gate and the second sacrifice gate structure; forming a protective cap layer on the semiconductor substrate, wherein the protective cap adopts silicon oxide; partly etching the protective cap layer and exposing a sacrifice gate of the second sacrifice gate structure; removing the sacrifice gate of the second sacrifice gate structure so as to form a second gate opening; and forming a high-K gate dielectric layer and a second metal gate in the second gate opening. According to the manufacturing method disclosed by the invention, the silicon oxide is used as the protective cap layer above the first metal gate; and the protective cap layer made of the silicon oxide is easily removed from the surface of the gate and cannot pollute the subsequently-formed gate dielectric layer, so that the reliability of the CMOS is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of transistorized manufacture method of CMOS that adopts the high-K metal grid.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more littler.Constantly dwindle under the situation in the MOS transistor characteristic size, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in the MOS transistor.
For the metal material of avoiding metal gates to other effect on structure of transistor, the gate stack structure of said metal gates and high K gate dielectric layer adopts grid to substitute (replacement gate) technology usually and makes.In this technology, before source-drain area injects, at first form the sacrificial gate that constitutes by polysilicon in gate location to be formed, said sacrificial gate is used for autoregistration and forms PROCESS FOR TREATMENT such as source-drain area.And after forming source-drain area, can remove said sacrificial gate and form gate openings in the position of sacrificial gate, afterwards, in said gate openings, fill high K gate dielectric layer and metal gates more successively.Because metal gates is made after source-drain area injects completion again, this makes that the quantity of subsequent technique is able to reduce, and has avoided metal material to be inappropriate for the problem of carrying out high-temperature process.
In practical application, the device property of PMOS transistor AND gate nmos pass transistor is also inequality, so its grid structure need design based on different threshold voltage demands.Therefore, when adopting said grid alternative techniques to make the CMOS transistor, need form the grid of PMOS transistor AND gate nmos pass transistor respectively, that is, CMOS transistor fabrication arts demand carries out grid replacement technology twice, to realize the replacement of sacrificial gate.
U.S. Pat 6171910 promptly discloses a kind of employing grid replacement technology and has made the transistorized method of CMOS.Referring to figs. 1 to Fig. 5, show the part flow process of this manufacture method.
As shown in Figure 1; Semiconductor substrate 101 is provided; PMOS district 103 on said Semiconductor substrate 101 forms sacrifice gates structure 107 and source-drain area respectively with nmos area 105, and said sacrifice gates structure comprises pseudo-gate dielectric layer 109, sacrificial gate 111 and hard mask layer 113.
As shown in Figure 2, on said Semiconductor substrate 101, form dielectric protection layer 115, the said dielectric protection layer 115 of planarization is until exposing sacrificial gate 111 surfaces.
As shown in Figure 3, on said Semiconductor substrate 101, form first photoresist layer 117, graphical said first photoresist layer 117, the sacrificial gate of exposing PMOS district 103 is surperficial, afterwards, removes said sacrificial gate to form first grid opening 119.
As shown in Figure 4, in said first grid opening, fill grid dielectric material and metal gate material; Afterwards, carry out planarization, the metal gate material that keeps at said first grid opening constitutes the transistorized grid of PMOS, and the grid dielectric material constitutes gate dielectric layer; Simultaneously, said planarization makes that expose on sacrificial gate 111 surfaces in the sacrifice gates structure 107 on the nmos area 105.
As shown in Figure 5, next carry out the grid of PROCESS FOR TREATMENT with the formation nmos pass transistor, yet, contaminated for fear of the transistorized grid of established PMOS, need on dielectric protection layer 115 and the transistorized grid of PMOS, form protective cap layer 121.Afterwards, the formation technology that is similar to the PMOS transistor gate is again made the grid of nmos pass transistor.
The said protective cap layer 121 that directly overlays on the PMOS transistor gate adopts silicon nitride or titanium nitride usually.Why adopting silicon nitride or titanium nitride, is because said dielectric protection layer 115 is silica, adopts the protective cap layer 121 that is different from dielectric protection layer 115 materials can when subsequent planarization is handled, realize from stopping etching.Yet, find that in the actual fabrication process protective cap layer 121 of these two kinds of material all exists certain problem.For the protective cap layer 121 of silicon nitride, when being difficult in follow-up planarization it is removed totally from the transistorized gate surface of PMOS, this causes on metal gates, forming effective contact hole; And, in the processing procedure of follow-up formation nmos pass transistor gate dielectric layer, find gate dielectric layer is polluted, thereby reduce the dielectric property of gate dielectric layer for the protective cap layer 121 of titanium nitride.
Summary of the invention
The problem that the present invention solves provides the transistorized manufacture method of a kind of CMOS, has improved the technology yield with simple and easy to do method.
For addressing the above problem, the invention provides the transistorized manufacture method of a kind of CMOS, adopt grid replacement technology manufacturing grid, comprising:
Semiconductor substrate is provided; Said Semiconductor substrate comprises first doped region and second doped region; Be formed with the first sacrifice gates structure and the second sacrifice gates structure on said first doped region and second doped region respectively, the said first sacrifice gates structure and the second sacrifice gates structure include pseudo-gate dielectric layer, sacrificial gate and hard mask layer;
On said Semiconductor substrate, form dielectric protection layer, said dielectric protection layer covers the first sacrifice gates structure and the second sacrifice gates structure;
The said dielectric protection layer of planarization also removes said hard mask layer, until exposing the sacrificial gate surface;
The sacrificial gate that removes the said first sacrifice gates structure forms the high K gate dielectric layer and first metal gates to form the first grid opening in said first grid opening;
On said Semiconductor substrate, form the protective cap layer, said protective cap layer adopts silica;
The said protective cap layer of partial etching exposes the sacrificial gate of the second sacrifice gates structure;
The sacrificial gate that removes the said second sacrifice gates structure forms the high K gate dielectric layer and second metal gates to form the second grid opening in said second grid opening.
Compared with prior art; The present invention has the following advantages: after the formation of a grid of PMOS or nmos pass transistor; Adopt the protective cap layer of silica as said grid top; The protective cap layer of said silica is easy to remove from gate surface, and can the gate dielectric layer of follow-up formation not polluted, and makes the reliability of device be improved.
Description of drawings
The prior art that shows Fig. 1 to Fig. 5 adopts grid replacement technology to make the transistorized part flow process of CMOS.
Fig. 6 shows the flow process of CMOS transistor fabrication method of the present invention.
Fig. 7 to Figure 16 shows the generalized section of CMOS transistor fabrication method one embodiment of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part; In the grid replacement technology of prior art; Adopt the protective cap layer existing problem of silicon nitride or titanium nitride: for the protective cap layer of silicon nitride; When being difficult in follow-up planarization it is removed from the transistorized gate surface of PMOS, this causes on metal gates, forming effective contact hole; And for the protective cap layer of titanium nitride; Through further discovering; In the processing procedure of follow-up formation nmos pass transistor gate dielectric layer, the titanium ion in the said titanium nitride can be diffused in the transistorized gate dielectric layer of PMOS, thereby reduces the dielectric property of PMOS transistor gate dielectric layer.
To the problems referred to above, inventor of the present invention provides a kind of CMOS transistorized manufacture method.In this manufacture method, after the formation of a grid of PMOS or nmos pass transistor, adopt the protective cap layer of silica as said grid top.Because silica is easy to remove from said gate surface, and can the gate dielectric layer of follow-up formation not polluted, and makes the reliability of device be improved.
With reference to figure 6, show the flow process of CMOS transistor fabrication method of the present invention, comprising:
Execution in step S602; Semiconductor substrate is provided; Said Semiconductor substrate comprises first doped region and second doped region; Be formed with the first sacrifice gates structure and the second sacrifice gates structure on said first doped region and second doped region respectively, the said first sacrifice gates structure and the second sacrifice gates structure include pseudo-gate dielectric layer, sacrificial gate and hard mask layer;
Execution in step S604 forms dielectric protection layer on said Semiconductor substrate, said dielectric protection layer covers the first sacrifice gates structure and the second sacrifice gates structure;
Execution in step S606, the said dielectric protection layer of planarization also removes said hard mask layer, until exposing the sacrificial gate surface;
Execution in step S608, the sacrificial gate that removes the said first sacrifice gates structure forms the high K gate dielectric layer and first metal gates to form the first grid opening in said first grid opening;
Execution in step S610 forms the protective cap layer on said Semiconductor substrate, said protective cap layer adopts silica;
Execution in step S612, the said protective cap layer of partial etching exposes the sacrificial gate of the second sacrifice gates structure;
Execution in step S614, the sacrificial gate that removes the said second sacrifice gates structure forms the high K gate dielectric layer and second metal gates to form the second grid opening in said second grid opening.
According to the difference of specific embodiment, for said CMOS transistor, both can make transistorized high K gate dielectric layer of PMOS and metal gates earlier, make the high K gate dielectric layer and the metal gates of nmos pass transistor afterwards again; Also can make the high K gate dielectric layer and the metal gates of nmos pass transistor earlier,
Next, in conjunction with concrete embodiment, CMOS transistor fabrication method of the present invention is further explained.
Fig. 7 to Figure 15 shows the generalized section of CMOS transistor fabrication method one embodiment of the present invention.
As shown in Figure 7, Semiconductor substrate 701 is provided, be formed with isolated area 703, first doped region 702 and second doped region 704 in the said Semiconductor substrate 701.Said isolated area 703 is used to isolate first doped region 702 and transistorized second doped region 704 of making PMOS of making nmos pass transistor.
Afterwards, on said Semiconductor substrate 701, form pseudo-gate dielectric layer 705, sacrificial gate layer 707 and hard mask layer 709 successively.In specific embodiment, said pseudo-gate dielectric layer 705 adopts silica, and said sacrificial gate layer 707 adopts polysilicon, and said hard mask layer 709 adopts silicon nitride or silicon oxynitride.
As shown in Figure 8, the said pseudo-gate dielectric layer of partial etching 705, sacrificial gate layer 707 and hard mask layer 709 form the first sacrifice gates structure 706 on first doped region 702, on second doped region 704, form the second sacrifice gates structure 708.
Then, said Semiconductor substrate 701 is carried out twice ion inject, the light doping section of the different doping types of formation in first doped region 702 and second doped region 704; Afterwards, form clearance wall 710 in said first sacrifice gates structure 706 and the second sacrifice gates structure, 708 both sides; And then, once more said Semiconductor substrate 701 is carried out twice ion and inject, in first doped region, 702 second doped regions 704, form the dark doped region of different doping types.The light doping section and the heavily doped region of said sacrifice gates structure both sides have constituted the transistorized source-drain area of CMOS.After forming source-drain area, continue said Semiconductor substrate 701 is carried out annealing in process, activate the injection ion that mixes.
In various embodiment; Said dark doped region can also adopt protruding source-drain structure; Comprise: after forming clearance wall, the Semiconductor substrate of etching sacrifice gates structure both sides is to form the source-drain area opening, afterwards; The heavily doped semi-conducting material of extension in said source-drain area opening, thus heavily doped region formed.
As shown in Figure 9, after source-drain area forms, on said Semiconductor substrate 701, form dielectric protection layer 711, said dielectric protection layer 711 covers the first sacrifice gates structure 706 and the second sacrifice gates structure 708.Afterwards, the said dielectric protection layer 711 of planarization also removes the hard mask layer on sacrifice gates structure top, until exposing sacrificial gate layer 707 surface.In specific embodiment, said dielectric protection layer 711 adopts silica.
Shown in figure 10, on said Semiconductor substrate 701, form first photoresist layer 713.Graphical said first photoresist layer 713 exposes the sacrificial gate layer 707 in the first sacrifice gates structure.Then, remove the said sacrificial gate layer 707 that exposes until exposing pseudo-gate dielectric layer 705, thereby formed first grid opening 715 in the position of the former first sacrifice gates structure.
In various embodiment, after removing said sacrificial gate layer 707, can also continue Semiconductor substrate 701 surfaces of the said pseudo-gate dielectric layer 705 of etching in exposing first grid opening 715.
Shown in figure 11, in said first grid opening, fill grid dielectric material and gate metal material successively.Afterwards, said Semiconductor substrate 701 is carried out planarization, make that the gate metal material surface in the said first grid opening is concordant with the top of clearance wall 710.Said planarization makes the sacrificial gate layer 707 in the second sacrifice gates structure 708 expose simultaneously.
So far, the first grid dielectric layer 712 of nmos pass transistor and first metal gates 714 are made and are formed, i.e. grid dielectric material in the first grid opening 715 and gate metal material.In specific embodiment, said first grid dielectric layer 712 can adopt silica, silicon oxynitride or high-k dielectric material; And said first metal gates 714 can adopt Cu, Al, W, Co or other metal materials.
Next, make transistorized gate dielectric layer of PMOS and metal gates again.
Shown in figure 12, on said Semiconductor substrate 701, form protective cap layer 717, said protective cap layer 717 adopts silica.Said protective cap layer 717 covers first metal gates, 714 surfaces, and sacrificial gate layer 707 surface in the second sacrifice gates structure 708.
Why adopting silica as protective cap layer 717, is because in subsequent planarization was handled, silica was easy to remove from first metal gates, 714 surfaces, also just can not influence the making of correspondence position contact hole.
In specific embodiment, can adopt the method for chemical vapor deposition to form said silica, the thickness of said silica is 50 to 200 dusts.Because first metal gates 714 of nmos pass transistor has been made formation, damages said first metal gates 714 for fear of higher reaction temperature, in the preferred embodiment, the reaction temperature that forms said protective cap layer 717 is lower than 400 degrees centigrade.
Shown in figure 13, on said Semiconductor substrate 701, form second photoresist layer 719.Afterwards, graphical said second photoresist layer 719 exposes the protective cap layer 717 on the second sacrifice gates structure 708.And then, be mask with said second photoresist layer 719, said protective cap layer 717 is carried out etching, expose the sacrificial gate layer 707 in the second sacrifice gates structure 708.
In practical application, adopt the method for dry etching or wet etching to remove said protective cap layer 717.Because protective cap layer 717 adopts identical materials to form with dielectric protection layer 711, therefore, said etching is difficult to realize from stopping etching.Based on this, the thickness of said protective cap layer 717 can not be excessive, otherwise can cause etch period long, and then destroy the dielectric protection layer 711 around the sacrificial gate layer 707.As previously mentioned, protective cap layer 717 thickness of said silica are advisable with 50 to 200 dusts.
In addition, for fear of do not remove the effect that removes that totally influences follow-up sacrificial gate layer 707 because of protective cap layer 717, need carry out over etching to said protective cap layer 717.In specific embodiment, the over etching ratio of said protective cap layer 717 over etching is greater than 30%.So-called over etching ratio is meant the ratio that actual etch period is increased with respect to the expection etch period of etching certain thickness protective cap layer 717.
Shown in figure 14, remove said second photoresist layer.Afterwards, be mask with protective cap layer 717, remove the sacrificial gate layer in the said second sacrifice gates structure, until exposing pseudo-gate dielectric layer 705, thereby formed second grid opening 721 in the position of the former second sacrifice gates structure.
In various embodiment, after removing said sacrificial gate layer 707, can also continue Semiconductor substrate 701 surfaces of the said pseudo-gate dielectric layer 705 of etching in exposing second grid opening 721.
Shown in figure 15, in said second grid opening, fill grid dielectric material and gate metal material successively.Said gate metal material should be crossed filling to cover whole Semiconductor substrate 701.In the second grid opening, fill in the grid dielectric material; Said grid dielectric material is covering protection cap layer 717 simultaneously; Because said protective cap layer 717 adopts silica but not titanium nitride; And silica can not react with the grid dielectric material, also can in said grid dielectric material, not introduce impurity, thereby guarantee the dielectric property of grid dielectric materials.
Shown in figure 16, said Semiconductor substrate 701 is carried out planarization, make that the gate metal material surface in the said second grid opening is concordant with the top of clearance wall 710.Said planarization makes the protective cap layer be removed simultaneously.
So far, transistorized second gate dielectric layer 716 of PMOS and second metal gates 718 are made and are formed, i.e. grid dielectric material in the second grid opening and gate metal material.In specific embodiment, said second gate dielectric layer 716 can adopt silica, silicon oxynitride or high-k dielectric material; And said second metal gates 718 can adopt Cu, Al, W, Co or other metal materials.
According to the difference of specific embodiment, before filling the gate metal material, can also in first grid opening and second grid opening, fill workfunction layers, said workfunction layers can be used to regulate the threshold voltage of PMOS transistor AND gate nmos pass transistor.
Should be appreciated that example here and embodiment only are exemplary, those skilled in the art can make various modifications and corrigendum under the situation of the spirit and scope of the present invention that do not deviate from the application and accompanying claims and limited.
Claims (10)
1. the transistorized manufacture method of CMOS adopts grid replacement technology manufacturing grid, it is characterized in that,
Comprise:
Semiconductor substrate is provided; Said Semiconductor substrate comprises first doped region and second doped region; Be formed with the first sacrifice gates structure and the second sacrifice gates structure on said first doped region and second doped region respectively, the said first sacrifice gates structure and the second sacrifice gates structure include pseudo-gate dielectric layer, sacrificial gate and hard mask layer;
On said Semiconductor substrate, form dielectric protection layer, said dielectric protection layer covers the first sacrifice gates structure and the second sacrifice gates structure;
The said dielectric protection layer of planarization also removes said hard mask layer, until exposing the sacrificial gate surface;
The sacrificial gate that removes the said first sacrifice gates structure forms the high K gate dielectric layer and first metal gates to form the first grid opening in said first grid opening;
On said Semiconductor substrate, form the protective cap layer, said protective cap layer adopts silica;
The said protective cap layer of partial etching exposes the sacrificial gate of the second sacrifice gates structure;
The sacrificial gate that removes the said second sacrifice gates structure forms the high K gate dielectric layer and second metal gates to form the second grid opening in said second grid opening.
2. manufacture method as claimed in claim 1 is characterized in that, said dielectric protection layer adopts silica.
3. manufacture method as claimed in claim 2 is characterized in that, the thickness of said protective cap layer is 50 to 200 dusts.
4. manufacture method as claimed in claim 1 is characterized in that, adopts the method for chemical vapor deposition to form said protective cap layer.
5. manufacture method as claimed in claim 1 is characterized in that, the reaction temperature that forms said protective cap layer is lower than 400 degrees centigrade.
6. manufacture method as claimed in claim 1 is characterized in that, the transistorized source-drain area of said CMOS includes heavily doped region and light doping section, forms said heavily doped region and comprises: before forming dielectric protection layer on the Semiconductor substrate,
The Semiconductor substrate of etching sacrifice gates structure both sides is to form the source-drain area opening;
The heavily doped semi-conducting material of extension in said source-drain area opening.
7. manufacture method as claimed in claim 1 is characterized in that, the said protective cap layer of said partial etching, and the sacrificial gate of exposing the second sacrifice gates structure comprises: the said protective cap layer of method etching that adopts anisotropic dry etch.
8. manufacture method as claimed in claim 7 is characterized in that, the said protective cap layer of said partial etching, and the sacrificial gate of exposing the second sacrifice gates structure also comprises: said protective cap layer is carried out over etching, and the over etching ratio is greater than 30%.
9. manufacture method as claimed in claim 1; It is characterized in that; In said first grid opening or second grid opening, form before the gate metal material, said manufacture method also comprises: in said first grid opening or second grid opening, form workfunction layers.
10. manufacture method as claimed in claim 1 is characterized in that, after the sacrificial gate that removes the sacrifice gates structure, said manufacture method also comprises: remove the pseudo-gate dielectric layer of said sacrifice gates structure and expose the semiconductor substrate surface of gate openings.
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| CN103390547A (en) * | 2012-05-08 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure with metal gate electrode layers |
| CN103456692A (en) * | 2012-05-30 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming complementary metal-oxide-semiconductor tube |
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| CN103390547A (en) * | 2012-05-08 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure with metal gate electrode layers |
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| CN103531541A (en) * | 2012-07-02 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Forming method of CMOS tube |
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| CN103681670A (en) * | 2012-08-30 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Metal gate structure of a semiconductor device |
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| CN104934376A (en) * | 2014-03-18 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| CN106206433A (en) * | 2015-05-05 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106206433B (en) * | 2015-05-05 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106856192A (en) * | 2015-12-09 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106856192B (en) * | 2015-12-09 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming transistor |
| CN112017949A (en) * | 2019-05-28 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112017949B (en) * | 2019-05-28 | 2023-05-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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