KR101060619B1 - A device isolation film manufacturing method for a semiconductor device and a nonvolatile memory device manufacturing method using the same - Google Patents

A device isolation film manufacturing method for a semiconductor device and a nonvolatile memory device manufacturing method using the same Download PDF

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KR101060619B1
KR101060619B1 KR20090010274A KR20090010274A KR101060619B1 KR 101060619 B1 KR101060619 B1 KR 101060619B1 KR 20090010274 A KR20090010274 A KR 20090010274A KR 20090010274 A KR20090010274 A KR 20090010274A KR 101060619 B1 KR101060619 B1 KR 101060619B1
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film
hard mask
method
layer
mask pattern
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KR20090010274A
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Korean (ko)
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KR20100091007A (en
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최영광
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Abstract

The present invention relates to a method of manufacturing a device isolation film of a semiconductor device capable of preventing the occurrence of a moat and a method of manufacturing a nonvolatile memory device using the same, and the method of manufacturing a device isolation film of the present invention for this purpose, a hard mask pattern on a substrate Forming a; Forming a passivation layer by converting a part of the sidewall of the hard mask pattern; Forming a trench by etching the substrate using the hard mask pattern and the passivation layer as an etch barrier; Filling an insulating material in the trench to form an isolation layer; And removing the hard mask pattern and performing a cleaning process. According to the present invention, the protective film is formed to prevent the isolation layer from being lost during the hard mask pattern removal and cleaning process. There is an effect that can prevent the occurrence.
Device Separator, Mort, CTD

Description

METHODS FOR FABRICATING ISOLATION LAYER IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, to a method of manufacturing a device isolation layer of a semiconductor device capable of preventing moat and a method of manufacturing a nonvolatile memory device using the same.

Recently, in order to realize a highly integrated nonvolatile memory device of 40 nm or less, research on a charge trap type nonvolatile memory device, or so-called charge trap device (CTD), has been actively conducted. The charge trap type nonvolatile memory device has a structure in which a tunnel insulating film, a charge trap film, a dielectric film, and a gate electrode are sequentially stacked on a substrate, and have trap sites having a deep level in the charge trap film. Data is stored by trapping (or capturing) the charge on it.

On the other hand, since the charge trapping type nonvolatile memory device is formed by combining a plurality of unit memory elements, an element isolation film for electrically separating the unit memory elements is required. In general, the device isolation layer is formed using a shallow trench isolation method (STI) using a trench structure.

1A to 1C are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to the related art.

As shown in FIG. 1A, the tunnel insulating film 12, the charge trap film 13, the buffer oxide film 14, and the hard mask nitride film pattern 15 are sequentially formed on the substrate 11.

Next, the buffer oxide layer 14, the charge trap layer 13, the tunnel insulation layer 12, and the substrate 11 are etched using the hard mask nitride layer pattern 15 as an etch barrier to form a trench 16 for device isolation. Afterwards, an insulating material is embedded in the trench 16 to form the device isolation layer 17. In this case, the device isolation layer 17 is formed using an oxide having excellent embedding characteristics, for example, a spin on dielectric (SOD) layer, in order to prevent defects such as seams within the film.

As shown in FIG. 1B, the hard mask nitride layer pattern 15 is removed using a wet etch method. At this time, the hard mask nitride film pattern 15 is removed using a phosphoric acid solution.

Next, a washing process is performed to remove residues, and at the same time, the buffer oxide film 14 is removed to expose the top surface of the charge trap film 13. At this time, the washing step is performed using hydrofluoric acid solution (HF).

As shown in FIG. 1C, after forming the dielectric film 18 along the entire structure surface including the device isolation film 17, the gate electrode 19 is formed on the dielectric film 18.

However, the prior art has a problem in that the edges of the device isolation layer 17 are lost in the process of removing the hard mask nitride layer pattern 15, thereby generating a moat (M). This is because the spin-on insulating film used as the device isolation film 17 contains a large amount of impurities such as carbon (C) and fine defects such as vacancy in the film and is easily etched in the phosphate solution. In addition, there is a problem that the mort (M) is further deepened during the cleaning process, because the device separation film 17 and the buffer oxide film 4 is the same oxide, the device separation film 17 is also etched by the hydrofluoric acid solution used in the cleaning process Because it becomes.

In addition, in order for the unit memory devices of the nonvolatile memory device to have uniform operating characteristics, the dielectric film 18 may be formed to have a uniform thickness on the entire structure. However, since the mort M has a horn shape, the dielectric film 18 formed around the mort M has a relatively thin thickness to form a dielectric film 18 having a uniform thickness on the entire surface of the structure. There is a problem that it is difficult to form (see reference B in FIG. 1C).

In addition, in order for the nonvolatile memory device to operate normally, the dielectric film 18 may be electrically separated between the charge trap film 13 and the gate electrode 19. However, a problem occurs in that the coupling ratio between the charge trap film 13 and the gate electrode 19 changes due to the short circuit of the dielectric film 18 due to the mort M (Fig. 1C). See symbol A).

The present invention has been proposed to solve the above problems of the prior art, the method of manufacturing a device isolation film of a semiconductor device that can prevent the generation of the mote during the process of removing the hard mask pattern and cleaning process during the device isolation film forming process. The purpose is to provide.

In addition, another object of the present invention is to provide a method of manufacturing a nonvolatile memory device which can prevent the operation characteristics of the nonvolatile memory device due to the mote.

According to an aspect of the present invention, there is provided a device isolation film manufacturing method comprising: forming a hard mask pattern on a substrate; Forming a passivation layer by converting a part of the sidewall of the hard mask pattern; Forming a trench by etching the substrate using the hard mask pattern and the passivation layer as an etch barrier; Embedding an insulating material in the trench to form an isolation layer; and removing the hard mask pattern. The method may further include performing a cleaning process after removing the hard mask pattern.

The forming of the passivation layer may be performed by oxidizing a part of the sidewall of the hard mask pattern. In addition, the forming of the protective film may be performed using an oxygen plasma (O 2 plasma). In addition, the forming of the protective film may be carried out at a temperature in the range of 10 ℃ ~ 400 ℃.

Removing the hard mask pattern may be performed using a dry etching method.

The protective layer and the device isolation layer may include an oxide layer, and the hard mask pattern may include a silicon layer.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including sequentially forming a tunnel insulating film, a charge trap film, a first protective film, and a hard mask pattern on a substrate; Converting a part of the sidewall of the hard mask pattern to form a second passivation layer; Forming a trench by etching the first protective layer, the charge trap layer, the tunnel insulating layer, and the substrate using the hard mask pattern and the second protective layer as an etch barrier; Filling an insulating material in the trench to form an isolation layer; Removing the hard mask pattern and performing a cleaning process to expose an upper surface of the charge trap layer.

In addition, the method of manufacturing a nonvolatile memory device of the present invention may further include forming a dielectric film along the surface of the entire structure including the device isolation layer and forming a gate electrode on the dielectric film.

The forming of the second passivation layer may be performed by oxidizing a part of the sidewall of the hard mask pattern. In addition, the forming of the second passivation layer may be performed using an oxygen plasma (O 2 plasma). In addition, the forming of the second protective film may be carried out at a temperature in the range of 10 ℃ to 400 ℃.

Removing the hard mask pattern may be performed using a dry etching method.

The first passivation layer, the second passivation layer, and the device isolation layer may include an oxide layer, and the hard mask pattern may include a silicon layer.

The present invention based on the above-described problem solving means, the hard mask pattern comprises a silicon film, by using a dry etching method to remove the hard mask pattern, thereby preventing the loss of the device isolation film during the hard mask pattern removal process There is an effect that can prevent the occurrence of.

In addition, according to the present invention, by forming a protective film (or second protective film) by converting a part of the sidewall of the hard mask pattern, it is possible to prevent the device isolation film from being lost during the hard mask pattern removing process, thereby effectively preventing the occurrence of mott. .

In addition, the present invention has the effect of preventing the occurrence of mott more effectively by preventing the device isolation film from being lost during the cleaning process by forming a protective film (or second protective film).

As described above, the present invention prevents the generation of the mott during the device isolation layer forming process, thereby preventing the deterioration of operating characteristics of the nonvolatile memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention to be described later is a method of manufacturing a device isolation film and a semiconductor of a non-volatile memory device capable of preventing the occurrence of a moat during the process of removing and cleaning the hard mask pattern during the device isolation film forming process. A nonvolatile memory device manufacturing method capable of preventing deterioration of operating characteristics is provided. To this end, the present invention is a technical principle to form a protective film by converting a part of the hard mask pattern sidewall.

2A to 2F are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, a tunnel insulating film 32 is formed on the substrate 31. The tunnel insulating film 32 may be formed of an oxide film, for example, silicon oxide film SiO 2 , and the silicon oxide film for the tunnel insulating film 32 may be formed using thermal oxidation.

Next, a charge trap film 33 is formed on the tunnel insulating film 32. The charge trap layer 33 is a space in which charge is stored, that is, a space in which data is stored, and is preferably formed of a material having a deep level trap site in the film. For example, the charge trap film 33 may be formed of a nitride film. In this case, a silicon nitride film (Si 3 N 4 ) may be used as the nitride film.

Next, a first protective film 34 is formed on the charge trap film 33. In this case, the first passivation layer 34 serves to prevent the inter-process charge trap layer 33 from being damaged and functions as a buffer layer between the hard mask layer and the charge trap layer 33 and is formed of an oxide layer. can do. As the oxide film, a silicon oxide film (SiO 2 ) may be used.

Next, a first hard mask film 35 is formed on the first protective film 34. The present invention is characterized in that the first hard mask film 35 is formed of a silicon film Si. As the silicon film Si, a polysilicon film (poly Si) or a silicon germanium film (SiGe) may be used.

Next, a second hard mask film 36 is formed on the first hard mask film 35. In this case, the second hard mask layer 36 serves to provide an etching margin insufficient for the first hard mask layer 35 in the process of forming a trench for subsequent device isolation, and may be formed of an oxide layer. . Here, the second hard mask film 36 is preferably formed of a silicon oxide film. For reference, since the silicon film is a material having a lower hardness than the nitride film, for example, the silicon nitride film, when only the silicon film is used as the hard mask film, the etching margin for the subsequent process may be insufficient.

Next, after forming a photoresist pattern (not shown) on the second hard mask layer 36, the second and first hard mask layers 36 and 35 are etched using the photoresist pattern as an etch barrier. . The hard mask pattern 37 including the first and second hard mask layers 35 and 36 etched through the above-described process may be formed. For reference, in the related art, the hard mask pattern 37 is formed of a single film made of a nitride film (see FIGS. 1A to 1C), but the hard mask pattern 37 of the present invention is a silicon film (ie, a first hard mask film). And a silicon oxide film (i.e., a second hard mask film) are formed as a stacked film.

As shown in FIG. 2B, a portion of the sidewalls of the first hard mask layer 35 is converted to form the second passivation layer 35A. The second passivation layer 35A prevents the occurrence of a moat due to the loss of the edge of the device isolation layer during the subsequent removal process and cleaning process of the first hard mask layer 35 or the removal process of the first protection layer 34. do. Therefore, the thickness of the second passivation layer 35A is preferably adjusted in consideration of the amount of device isolation film loss lost during the subsequent removal and cleaning of the first hard mask layer 35. In addition, the second passivation layer 35A is formed to have the same or thicker thickness as the first passivation layer 34 in order to prevent the device isolation layer from being lost during the complete removal of the first passivation layer 34 during the subsequent cleaning process. It is desirable to. For example, the second protective film 35A is preferably formed to have a thickness T in the range of 40 kPa to 60 kPa.

In addition, the second protective film 35A is preferably formed of the same material as the first protective film 34. Therefore, the second protective film 35A is preferably formed of an oxide film. This is to simplify the process by simultaneously removing the first protective film 34 and the second protective film 35A during the subsequent cleaning process. For reference, it is preferable to remove the second protective film 35A in order to secure the contact area between the dielectric film and the charge trap film 33 before proceeding with the subsequent dielectric film deposition process.

In addition, in order to prevent the line width of the hard mask pattern 37 from changing, the second passivation layer 35A may be formed by converting a part of the sidewalls of the first hard mask layer 35. For example, the second passivation layer 35A may be formed by oxidizing a part of the sidewall of the first hard mask layer 35 made of a silicon film. Therefore, the second protective film 35A may be formed of a silicon oxide film (SiO 2 ).

Specifically, the second passivation layer 35A may be formed using an oxygen plasma (O 2 plasma) at a low temperature, for example, at a temperature ranging from 10 ° C. to 400 ° C. At this time, the reason why the process of forming the second protective film 35A is performed at a low temperature, for example, in the range of 10 ° C. to 400 ° C., is to easily control the thickness T of the second protective film 35 A and at the same time charge trap between processes. This is to reduce the thermal burden on the film 33. That is, when the second protective film 35A is formed at a temperature of less than 10 ° C., the second protective film 35A may not be normally formed, or the formation speed may be low, resulting in a decrease in productivity. On the other hand, when formed at a temperature exceeding 400 ° C., the formation rate of the second protective film 35A is so fast that it is difficult to form the second protective film 35A having a thickness in the range of 40 kPa to 60 kPa, and the charge trap film 33 ) May cause a problem that the charge trap layer 33 is deformed or damaged due to an increased thermal burden. On the other hand, since the second protective film 35A is formed using oxygen plasma, the second protective film 35A can be formed by easily oxidizing the silicon film even at a low temperature, for example, at a temperature in the range of 10 ° C to 400 ° C.

As shown in FIG. 2C, the first protective layer 34, the charge trap layer 33, the tunnel insulating layer 32, and the substrate 31 are formed by using the hard mask pattern 37 and the second protective layer 35A as an etch barrier. Etching is performed sequentially to form a trench 38 for device isolation. Hereinafter, the reference numerals of the etched first passivation layer 34, the charge trap layer 33, and the tunnel insulation layer 32 are changed to '34A', '33A', and '32A', respectively.

Next, after filling the trench 38 and depositing an insulating material to cover the hard mask pattern 37, a planarization process is performed under the condition that the top surface of the first hard mask layer 35 is exposed. 39). At this time, the second hard mask film 36 is removed, and the planarization process may be performed using chemical mechanical polishing (CMP).

The device isolation layer 39 may be formed of the same material as the first and second passivation layers 34A and 35A. Therefore, the device isolation film 39 may be formed of an oxide film. In this case, the device isolation layer 39 may be formed of an oxide having excellent embedding characteristics, for example, a spin on dielectric layer, in order to prevent defects such as seams within the film.

As shown in FIG. 2D, the first hard mask film 35 is removed. In this case, the first hard mask layer 35 may be removed using a dry etch method, and as the etching gas, the first hard mask layer 35 may be formed of the first isolation layer 39 and the first and second passivation layers 34A and 35A. It is preferable to use a gas having an etching selectivity with the hard mask film 35. That is, as the etching gas, a gas in which the first hard mask layer 35 is well etched and the device isolation layer 39 and the first and second protective layers 34A and 35A are not etched is preferably used. For example, when the first hard mask layer 35 includes a silicon layer and the device isolation layer 39 and the first and second passivation layers 34A and 35A include an oxide layer, hydrogen bromide gas (HBr), Mixed gas (HBr / Cl 2 / SF 6 ) mixed with chlorine gas (Cl 2 ) and sulfur hexafluoride gas (SF 6 ) may be used.

For reference, when the device isolation layer 39 includes an oxide film (particularly a spin-on insulating film) and the hard mask film includes a nitride film, a wet etching method using a phosphoric acid solution may be used to remove only the hard mask film. That is, it is practically impossible to selectively remove only the hard mask film made of the nitride film using the dry etching method. This is because the oxide film is well etched in the fluorine-based gas (for example, CF 4 gas, CHF 3 gas, etc.) which is commonly used as a nitride film etching gas.

However, according to the present invention, the first hard mask layer 35 is formed of a silicon layer, so that the first hard mask is not lost using the dry etching method without loss of the device isolation layer 39, the first and second protective layers 34A and 35A. Only the membrane 35 can be selectively removed. Accordingly, the present invention can prevent the edge of the device isolation layer 39 from being lost in the process of removing the first hard mask layer 35. In addition, during the removal process of the first hard mask layer 35, the second protection layer 35A acts as a barrier to more effectively prevent the device isolation layer 39 from being lost. As a result, the present invention prevents the edges of the device isolation layer 39 from being lost during the first hard mask layer 35 removal process, thereby preventing the mott from occurring.

As shown in FIG. 2E, a cleaning process is performed to remove residues remaining on the substrate 31 and to expose the upper surface of the charge trap film 33A. That is, the first protective film 34A is removed through the cleaning process. At this time, the second protective film 35A made of the same material as the first protective film 34A (that is, the oxide film) is also etched, but the thickness of the second protective film 35A is the same as the thickness of the first protective film 34A, or Since it is formed thicker, it is possible to prevent the device isolation film 39 from being lost due to the second protective film 35A during the cleaning process. Therefore, it is possible to prevent the generation of the mort between the washing steps.

The washing process can be carried out using a wet cleaning method and can be carried out using a solution containing hydrofluoric acid (HF). In this case, as a solution containing hydrofluoric acid, DHF solution or BOE (Buffered Oxide Etchant) mixed with deionized water and hydrofluoric acid solution may be used.

As shown in FIG. 2F, the dielectric film 40 is formed along the entire structure surface including the device isolation film 39. The dielectric film 40 is preferably formed of a material having a high dielectric constant (High-K). Here, a material having a high dielectric constant greater than that of a silicon oxide film. Therefore, it means a material having a dielectric constant of 3.9 or more.

Specifically, the dielectric film 40 may be formed of a metal oxide film having a high dielectric constant. The metal oxide film is selected from the group consisting of aluminum oxide film (Al 2 O 3 ), hafnium oxide film (HfO 2 ), zirconium oxide film (ZrO 2 ), yttrium oxide film (Y 2 O 3 ) and lanthanum oxide film (La 2 O 3 ). Any one or these may be formed into a laminated film in which they are laminated.

Here, the present invention can prevent the generation of the mott during the device isolation film 39 forming process, it is possible to form a dielectric film 40 having a uniform thickness on the entire structure. Through this, the unit memory devices of the charge trapping nonvolatile memory device may be formed to have uniform operating characteristics. That is, the operating characteristics of the nonvolatile memory device can be improved.

Next, the gate electrode 41 is formed on the dielectric film 40. The gate electrode 41 may be formed of a silicon film, a metal film, or a laminated film in which a silicon film and a metal film are stacked. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like can be used. Tungsten film (W), titanium film (Ti), tantalum film (Ta), tungsten nitride film (WN), tantalum nitride film (TaN), titanium nitride film (TiN), tungsten silicide (WSi) and the like can be used as the metallic film. .

Here, the present invention prevents the generation of the mott during the process of forming the device isolation film 39, and thus, the coupling ratio between the charge trap film 33A and the gate electrode 41 due to the short circuit of the dielectric film 40 due to the mote. (Coupling Ration) can be prevented from changing.

Through the above-described process, the charge trapping nonvolatile memory device of the present invention can be completed.

In summary, according to the present invention, the first hard mask layer 35 includes a silicon layer, and the first hard mask layer 35 is removed using a dry etching method, thereby removing the first hard mask layer 35. It is possible to prevent the separation of the separator 39 to prevent the occurrence of mort.

In addition, the present invention prevents the isolation layer 39 from being lost during the first hard mask layer 35 removal process by forming a second passivation layer 35A by converting a part of the sidewalls of the first hard mask layer 35. More effectively prevent the occurrence of mort.

In addition, according to the present invention, by forming the second protective film 35A, it is possible to prevent the device isolation film 39 from being lost during the cleaning process, thereby more effectively preventing the mott from being generated.

As described above, the present invention can prevent the mott from being generated during the process of forming the device isolation layer 39, thereby preventing deterioration of operating characteristics of the nonvolatile memory device.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A to 1C are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to the prior art;

2A to 2F are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to an exemplary embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32, 32A tunnel insulating film

33, 33A: charge trap film 34, 34A: first protective film

35: first hard mask film 35A: second protective film

36: second hard mask film 37: hard mask pattern

38: trench 39: device isolation film

40 dielectric film 41 gate electrode

Claims (22)

  1. Forming a hard mask pattern on the substrate;
    Oxidizing the hard mask pattern sidewalls to form a protective film;
    Forming a trench by etching the substrate using the hard mask pattern and the passivation layer as an etch barrier;
    Filling an insulating material in the trench to form an isolation layer; And
    Removing the hard mask pattern
    Device isolation film manufacturing method of a semiconductor device comprising a.
  2. The method of claim 1,
    After removing the hard mask pattern,
    A device isolation film manufacturing method of a semiconductor device further comprising the step of performing a cleaning process.
  3. delete
  4. The method of claim 1,
    Forming the protective film,
    A device isolation film manufacturing method of a semiconductor device using oxygen plasma (O 2 plasma).
  5. The method of claim 1,
    Forming the protective film,
    A device isolation film manufacturing method of a semiconductor device carried out at a temperature in the range of 10 ℃ to 400 ℃.
  6. The method of claim 1,
    Removing the hard mask pattern,
    A device isolation film manufacturing method for a semiconductor device performed by using a dry etching method.
  7. The method of claim 1,
    The device isolation film manufacturing method of a device isolation film of a semiconductor device comprising a spin on dielectric (SOD).
  8. The method of claim 1,
    The hard mask pattern is formed of a laminated film in which a silicon film and an oxide film are laminated, and the protective film is formed by oxidizing the silicon film.
  9. The method of claim 2,
    The protective film and the device isolation film comprises an oxide film, the hard mask pattern is a silicon device manufacturing method of a semiconductor device comprising a silicon film.
  10. 10. The method of claim 9,
    Removing the hard mask pattern,
    A method of fabricating an isolation layer in a semiconductor device by dry etching using a mixed gas of hydrogen bromide gas (HBr), chlorine gas (Cl 2 ) and sulfur hexafluoride gas (SF 6 ).
  11. 10. The method of claim 9,
    The washing step,
    A device isolation film manufacturing method for a semiconductor device, which is performed using a solution containing hydrofluoric acid (HF).
  12. Sequentially forming a tunnel insulating film, a charge trap film, a first passivation film, and a hard mask pattern on the substrate;
    Oxidizing the hard mask pattern sidewalls to form a second passivation layer;
    Forming a trench by etching the first protective layer, the charge trap layer, the tunnel insulating layer, and the substrate using the hard mask pattern and the second protective layer as an etch barrier;
    Filling an insulating material in the trench to form an isolation layer;
    Removing the hard mask pattern; And
    Performing a cleaning process to expose an upper surface of the charge trap layer;
    Nonvolatile memory device manufacturing method comprising a.
  13. The method of claim 12,
    After performing the washing step,
    Forming a dielectric film along the surface of the entire structure including the device isolation film; And
    Forming a gate electrode on the dielectric layer
    A nonvolatile memory device manufacturing method further comprising.
  14. The method of claim 12,
    And the second passivation layer is formed to have a thickness equal to or greater than that of the first passivation layer.
  15. The method of claim 12,
    Forming the second protective film,
    A nonvolatile memory device manufacturing method using oxygen plasma (O 2 plasma).
  16. The method of claim 12,
    Forming the second protective film,
    A method of manufacturing a nonvolatile memory device at a temperature ranging from 10 ° C to 400 ° C.
  17. The method of claim 12,
    Removing the hard mask pattern,
    A method of manufacturing a nonvolatile memory device using dry etching.
  18. The method of claim 12,
    The device isolation layer includes a spin on dielectric (SOD).
  19. The method of claim 12,
    The hard mask pattern is formed of a laminated film in which a silicon film and an oxide film are stacked, and the second protective film is formed by oxidizing the silicon film.
  20. The method of claim 12,
    The first passivation layer, the second passivation layer, and the device isolation layer include an oxide layer, and the hard mask pattern includes a silicon layer.
  21. 21. The method of claim 20,
    Removing the hard mask pattern,
    A method of manufacturing a nonvolatile memory device by dry etching using a mixed gas of hydrogen bromide gas (HBr), chlorine gas (Cl 2 ) and sulfur hexafluoride gas (SF 6 ).
  22. 21. The method of claim 20,
    The washing step,
    A nonvolatile memory device manufacturing method using a solution containing hydrofluoric acid (HF).
KR20090010274A 2009-02-09 2009-02-09 A device isolation film manufacturing method for a semiconductor device and a nonvolatile memory device manufacturing method using the same KR101060619B1 (en)

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