CN102569049B - Manufacture method of metal grid electrode - Google Patents

Manufacture method of metal grid electrode Download PDF

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CN102569049B
CN102569049B CN201010610018.5A CN201010610018A CN102569049B CN 102569049 B CN102569049 B CN 102569049B CN 201010610018 A CN201010610018 A CN 201010610018A CN 102569049 B CN102569049 B CN 102569049B
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layer
medium layer
metal
replacement gate
metal medium
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CN102569049A (en
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鲍宇
蒋莉
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

A manufacture method of a metal grid electrode comprises forming a gate oxide and a substitution grid electrode on a provided semiconductor substrate and then forming lateral wall layers on two sides of the substitution grid electrode; considering the lateral wall layers and the substitution grid electrode as masks and conducting ion implantation on the semiconductor substrate to form a source and drain region; depositing a contact etching stopping layer on the surfaces of the semiconductor substrate, the lateral wall layers and the substitution grid electrode; depositing a first metal front medium layer on the contact etching stopping layer, enabling the height of the deposited first metal front medium layer to be higher than the surface of the substitution grid electrode, polishing to reach the first metal front medium layer, and forming footsteps on the surfaces of the contact etching stopping layer and the first metal front medium layer which are in a same plane; depositing a second metal front medium layer on the surfaces of the first metal front medium layer and the contact etching stopping layer, completely covering the footsteps, polishing again to reach the substitution grid electrode; and etching the substitution grid electrode to obtain a substitution grid electrode channel and filling the metal grid electrode in the substitution grid electrode channel. The manufacture method removes the footstep effect produced in a manufacture process.

Description

A kind of manufacture method of metal gates
Technical field
The present invention relates to the detection technique of semiconductor applications, particularly a kind of manufacture method of metal gates.
Background technology
At present, high dielectric constant insulating material and metal gates are by the logic circuit device that is used to manufacture in semiconductor device.
In order to control short-channel effect, more the semiconductor device of small-feature-size requires further to improve gate electrode electric capacity.This can realize by the thickness of continuous attenuate gate oxide, but the thing followed is the lifting of gate electrode leakage current.When silicon dioxide is as gate oxide, thickness is during lower than 3.0 nanometer, and leakage current just becomes and cannot stand.Solution to the problems described above is used high dielectric constant insulating material to replace silicon dioxide exactly, high dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., dielectric constant is generally all greater than 15, adopt this material can further improve gate electrode electric capacity, gate electrode leakage current can be significantly improved again simultaneously.For identical gate oxide thickness, by high dielectric constant insulating material and metal gates collocation, its gate electrode leakage current will reduce several index magnitudes, and solve problem incompatible between high dielectric constant insulating material and polysilicon with metal gates replacement polygate electrodes.
When making metal gates, usually adopt the latter made mode of grid to make, namely first under Semiconductor substrate, be formed with behind source region, then form metal gates, below describe in detail.
The method flow diagram of the making metal gates that Fig. 1 provides for prior art, in conjunction with the prior art shown in Fig. 2～Fig. 8, make the procedure sectional structure chart explanation of metal gates:
Step 101, as shown in Figure 2 forms successively gate oxide 201 and the replacement gate 202 with high-k in Semiconductor substrate 200.
Before this step, in Semiconductor substrate 200, carried out the active area of twin well process definition N type semiconductor device and P type semiconductor device, and adopt shallow-trench isolation (STI) to isolate the active area of N type semiconductor device and P type semiconductor device, this and the solution of the present invention have nothing to do, and no longer describe in detail.
In this step, the gate oxide 101 of high-k can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., and dielectric constant is generally all greater than 15.
In this step, replacement gate 202 can be carried out patterning to described photoresistance glue-line by being coated with photoresistance glue-line on the replacement gate material in deposition, the position of definition replacement gate, then take the photoresistance glue-line of patterning as mask carries out etching, obtain replacement gate.It should be noted that, what because final, form is metal gates, and replacement gate can be substituted by metal gates, that is to say that replacement gate is finally non-existent, thus as an alternative the material of grid can have multiple, such as the material of replacement gate is polysilicon.
Step 102, as shown in Figure 3, forms side wall layer 203 in the both sides of replacement gate 202, and take described side wall layer 203 and replacement gate 202 is mask, adopts Implantation mode in Semiconductor substrate 200, to form source-drain area 204.
Wherein, the material of side wall layer is identical with the material of first before-metal medium layer (PMD) of subsequent deposition, such as silicon nitride layer.
Step 103, as shown in Figure 4, deposition contact etching stop layer 205.
In this step, contact etching stop layer 205 can be silicon oxide layer, and requirement and the first before-metal medium layer that upper strata will deposit, have higher selection ratio.
Step 104, as shown in Figure 5, on contact etching stop layer 205, deposit medium 206 before the first metal, the whole height of first before-metal medium layer 206 that deposits surpasses the height of replacement gate 202, then pass through cmp (CMP), at contact etching stop layer 205, stop, preventing that CMP from arriving replacement gate 202.
In this step, the before-metal medium layer 206 depositing can be silicon nitride layer.
In this step, due in CMP process, between the first before-metal medium layer 206 and contact etching stop layer 205, there is very high etching selection ratio, so when being polished to contact etching stop layer 205, not identical with the etch rate of the first before-metal medium layer 206 at conplane contact etching stop layer 205, can cause step effect.
In this step, the pressure of before-metal medium layer is 0～1.6GPa, and tensile force is 0～3.5GPa.
Step 105, as shown in Figure 6, carries out etching to replacement gate 202, obtains replacement gate groove 207.
Etching replacement gate 201 can adopt dry etching, also can adopt wet etching.Wherein, the gas of dry etching can comprise sulphur hexafluoride (SF 6) or chlorine (Cl 2); Wet etching, specifically can adopt the mixed solution of nitric acid and hydrofluoric acid to remove.No matter dry etching or wet etching, when can guarantee etching replacement gate 201, do not carry out etching to the before-metal medium layer of its both sides.
Step 106, as shown in Figure 7, fills metal gate material at replacement gate groove 207, obtains metal gates.
In this step, deposition is as the material of metal gates, during deposition, this metal gate material also can cover the first before-metal medium layer 206 and contact stop-layer 205 surfaces, then pass through CMP, to the first before-metal medium layer 206 with contact the lip-deep metal gate material of stop-layer 205 and carry out polishing, obtain metal gates.
As the material of metal gates, it can be the combination of any two kinds or three kinds in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN).
From the scheme of above-mentioned making metal gates, can find out, due to the step shown in Fig. 6, can in etching replacement gate and filling metal gates, exert an influence to follow-up, finally affect the performance of resulting semiconductor device.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of metal gates, the method can be eliminated the step effect producing in manufacturing process.
For achieving the above object, technical scheme of the invention process is specifically achieved in that
A manufacture method for metal gates, the method comprises:
In the Semiconductor substrate providing, form after gate oxide and replacement gate, in replacement gate both sides, form side wall layer;
Take side wall layer and replacement gate as mask, Semiconductor substrate is carried out to Implantation and form source-drain area;
At Semiconductor substrate, side wall layer and replacement gate surface deposition contact etching stop layer;
At contact etching stop layer, deposit after the first before-metal medium layer, the the first before-metal medium layer height depositing surpasses replacement gate surface, be polished to contact etching stop layer and stop, the first before-metal medium layer surface and contact etching stop layer surface at grade form step;
At the first before-metal medium layer surface and contact etching stop layer surface deposition the second before-metal medium layer, cover completely after described step, be again polished to replacement gate surface;
Etch away replacement gate and obtain replacement gate groove, at replacement gate trench fill metal gates.
The material of described the second before-metal medium layer is silica.
Described the second before-metal medium layer using plasma strengthens chemical vapour deposition (CVD) PECVD method and obtains.
Described the second before-metal medium layer adopts sub-atmospheric pressure chemical vapour deposition (CVD) SACVD method to obtain.
Described the second before-metal medium layer adopts SACVD method and PECVD method to obtain.
Described the second before-metal medium layer first adopts SACVD method, then adopts PECVD method to obtain.
As seen from the above technical solution, the present invention is before etching replacement gate, in polishing after the first before-metal medium layer, also comprise that deposition the second before-metal medium layer covers the step that the front medium of polishing the first metal produces, and then the second before-metal medium layer is polished to replacement gate surface.Like this, in subsequent etching replacement gate and filling metal gates process, on semiconductor device, just can there is not step.Therefore, method provided by the invention is eliminated the step effect producing in metal gates manufacturing process.
Accompanying drawing explanation
The method flow diagram of the making metal gates that Fig. 1 provides for prior art;
Fig. 2～Fig. 7 is the procedure sectional structure chart that prior art is made metal gates;
Fig. 8 is the manufacture method flow chart of metal gates provided by the invention;
The manufacture method sectional structure chart of Fig. 9～Figure 15 metal gates provided by the invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
In making metal gates process, the present invention is in order to overcome the step effect producing on semiconductor device when polishing the first before-metal medium layer, before etching replacement gate, in polishing after the first before-metal medium layer, also comprise that deposition the second before-metal medium layer covers the step that the front medium of polishing the first metal produces, and then the second before-metal medium layer is polished to replacement gate surface.Like this, in subsequent etching replacement gate and filling metal gates process, on semiconductor device, just can there is not step.
In the present invention, before the second metal, medium can be silicon oxide layer, and the mode of employing is that sub-atmospheric pressure chemical vapour deposition (CVD) (SACVD) method, plasma enhanced chemical vapor deposition (PECVD) method or SACVD method combine and obtain with PECVD method.Wherein, the process that adopts SACVD method to obtain silicon oxide layer is: reaction chamber passes into the TEOS of 1～5 gram and the ozone (O of 2000～20000 milliliters every cubic centimetre (sccm) 3), carrier gas adopts the helium (H of 2000～20000sccm e) and the nitrogen (N of 2000～20000sccm 2), the pressure of reaction chamber is 500～700 holders, temperature is 350～450 degrees Celsius; The process that adopts PECVD method to obtain silicon oxide layer is: reaction chamber passes into the TEOS of 2～10gm and the oxygen (O of 2000～10000sccm 2), carrier gas adopts the HE of 2000～0000sccm, and the radio-frequency power of reaction chamber is 1000～1500 watts, and pressure is 500～700 holders, and temperature is 350～450 degrees Celsius.
When adopting SACVD method to combine with PECVD method to obtain silicon oxide layer, can adopt and first carry out SACVD method, and then carry out PECVD method and obtain silicon oxide layer, SACVD method can overcome the hole problem in deposition process, and the deposition velocity of PECVD is faster.
Fig. 8 is the method flow diagram of making metal gates provided by the invention, and its concrete steps are:
Step 801, as shown in Figure 9 forms successively gate oxide 201 and the replacement gate 202 with high-k in Semiconductor substrate 200.
Step 802, as shown in figure 10, forms side wall layer 203 in the both sides of replacement gate 202, and take described side wall layer 203 and replacement gate 202 is mask, forms source-drain area 204 in Semiconductor substrate 200.
Wherein, the material of side wall layer is identical with the material of the before-metal medium layer of subsequent deposition, such as silicon nitride layer.
Step 803, as shown in figure 11, deposition contact etching stop layer 205.
In this step, contact etching stop layer 205 can be silicon oxide layer, and requirement and the before-metal medium layer that upper strata will deposit, have higher selection ratio.
Step 804, as shown in figure 12, on contact etching stop layer 205, deposit the first before-metal medium layer 206, the whole height of the first before-metal medium layer 206 depositing surpasses the height of replacement gate 202, then pass through CMP, at contact etching stop layer 205, stop, preventing that CMP from arriving replacement gate 202.
In this step, the first before-metal medium layer 206 depositing can be silicon nitride layer.
In this step, due in CMP process, between the first before-metal medium layer 206 and contact etching stop layer, there is very high etching selection ratio, so when being polished to contact etching stop layer 205, not identical with the etch rate of the first before-metal medium layer 206 at conplane contact etching stop layer 205, can cause step effect.
In this step, the pressure of before-metal medium layer is 0～1.6GPa, and tensile force is 0～3.5GPa.
Described in step 801～804, process is identical with process described in step 101～step 104, repeats no more here.
Step 805, as shown in figure 13 deposits after the second before-metal medium layer 901 on contact etching stop layer 205 surfaces and the first before-metal medium layer 206 surfaces, and employing CMP is polished to replacement gate surface to the second before-metal medium layer 901.
The second before-metal medium layer 901 can be silicon oxide layer in this step, for covering step.
Step 806, as shown in figure 14, carries out etching to replacement gate 202, obtains replacement gate groove 207.
Etching replacement gate 202 can adopt dry etching, also can adopt wet etching.Wherein, the gas of dry etching can comprise SF 6or Cl 2; Wet etching, specifically can adopt the mixed solution of nitric acid and hydrofluoric acid to remove.No matter dry etching or wet etching, when can guarantee etching replacement gate 202, do not carry out etching to the before-metal medium layer of its both sides.
Step 807, as shown in figure 15, fills metal gate material at replacement gate groove 207, obtains metal gates 208.
In this step, deposition is as the material of metal gates, during deposition, this metal gate material also can cover the second before-metal medium layer 901 and contact stop-layer 205 surfaces, then pass through CMP, to the second before-metal medium layer 901 with contact the lip-deep metal gate material of stop-layer 205 and carry out polishing, obtain metal gates 208.
As the material of metal gates, it can be the combination of any two kinds or three kinds in Ti, TiN, Ta, TaN.
More than lift preferred embodiment; the object, technical solutions and advantages of the present invention are further described; institute is understood that; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any modification of doing, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.

Claims (5)

1. a manufacture method for metal gates, is characterized in that, the method comprises:
In the Semiconductor substrate providing, form after gate oxide and replacement gate, in replacement gate both sides, form side wall layer;
Take side wall layer and replacement gate as mask, Semiconductor substrate is carried out to Implantation and form source-drain area;
At Semiconductor substrate, side wall layer and replacement gate surface deposition contact etching stop layer;
At contact etching stop layer, deposit after the first before-metal medium layer, the the first before-metal medium layer height depositing surpasses replacement gate surface, be polished to contact etching stop layer and stop, the first before-metal medium layer surface and contact etching stop layer surface at grade form step;
At the first before-metal medium layer surface and contact etching stop layer surface deposition the second before-metal medium layer, cover completely after described step, be again polished to replacement gate surface;
Etch away replacement gate and obtain replacement gate groove, at replacement gate trench fill metal gates;
Described contact etching stop layer is silicon oxide layer, and described the first before-metal medium layer is silicon nitride layer, and described the second before-metal medium layer is silicon oxide layer.
2. the method for claim 1, is characterized in that, described the second before-metal medium layer using plasma strengthens chemical vapour deposition (CVD) PECVD method and obtains.
3. the method for claim 1, is characterized in that, described the second before-metal medium layer adopts sub-atmospheric pressure chemical vapour deposition (CVD) SACVD method to obtain.
4. the method for claim 1, is characterized in that, described the second before-metal medium layer adopts SACVD method and PECVD method to obtain.
5. method as claimed in claim 4, is characterized in that, described the second before-metal medium layer first adopts SACVD method, then adopts PECVD method to obtain.
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CN106783585A (en) * 2016-12-26 2017-05-31 苏州工业园区纳米产业技术研究院有限公司 Lithographic method based on ledge structure
US11305988B2 (en) * 2020-09-01 2022-04-19 Aac Acoustic Technologies (Shenzhen) Co., Ltd. Method for preparing silicon wafer with rough surface and silicon wafer

Citations (3)

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Publication number Priority date Publication date Assignee Title
CN1902740A (en) * 2003-12-30 2007-01-24 英特尔公司 Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
CN1967790A (en) * 2005-11-16 2007-05-23 联华电子股份有限公司 Method of removing metal silicide layer on grid and etching method
CN101728330A (en) * 2008-11-03 2010-06-09 台湾积体电路制造股份有限公司 Method for manufacturing semiconductor device

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US20060046523A1 (en) * 2004-08-25 2006-03-02 Jack Kavalieros Facilitating removal of sacrificial layers to form replacement metal gates
US7271045B2 (en) * 2005-09-30 2007-09-18 Intel Corporation Etch stop and hard mask film property matching to enable improved replacement metal gate process

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
CN1902740A (en) * 2003-12-30 2007-01-24 英特尔公司 Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
CN1967790A (en) * 2005-11-16 2007-05-23 联华电子股份有限公司 Method of removing metal silicide layer on grid and etching method
CN101728330A (en) * 2008-11-03 2010-06-09 台湾积体电路制造股份有限公司 Method for manufacturing semiconductor device

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