CN103579076B - The method forming shallow channel isolation area - Google Patents
The method forming shallow channel isolation area Download PDFInfo
- Publication number
- CN103579076B CN103579076B CN201210261968.0A CN201210261968A CN103579076B CN 103579076 B CN103579076 B CN 103579076B CN 201210261968 A CN201210261968 A CN 201210261968A CN 103579076 B CN103579076 B CN 103579076B
- Authority
- CN
- China
- Prior art keywords
- oxide
- layer
- silicon
- isolation area
- channel isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of method forming shallow channel isolation area, described shallow channel isolation area was formed before high-k gate oxide, and the method includes: sequentially form isolating oxide layer and silicon nitride layer on a semiconductor substrate；It is sequentially etched silicon nitride layer, isolating oxide layer and Semiconductor substrate, in described Semiconductor substrate, forms groove；At one layer of liner oxidation silicon of described trench interiors superficial growth；In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer；Wherein, carrying out filling of oxide and use aumospheric pressure cvd form silicon oxide layer and increase the method that silicon oxide layer density combines in groove, repeatedly circulation is carried out.Use the present invention it can be avoided that the equivalent oxide thickness of high-k gate oxide increases.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly to a kind of method forming shallow channel isolation area.
Background technology
In order to control short-channel effect, smaller szie requirement on devices improves gate electrode electric capacity further.This can be realized by the thickness of continuous thinning gate oxide, but the thing followed is the lifting of gate electrode leakage current.When silicon dioxide is as gate oxide, and when thickness is less than 5.0 nanometer, leakage current just becomes to stand.Solution to the problems described above uses high-k (HK) insulant to replace silicon dioxide exactly, high dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., dielectric constant is typically greater than 15, using this material can improve gate capacitance further, gate leak current can be significantly improved again simultaneously.For identical gate oxide thickness, high dielectric constant insulating material is arranged in pairs or groups with metal gate electrode, its gate electrode leakage current will reduce several index magnitude, and replace polygate electrodes with metal gate electrode and solve problem incompatible between high dielectric constant insulating material and polysilicon.
Therefore, high-k gate oxide and metal gate electrode are used for manufacturing MOS device.
Prior art is before making high-k gate oxide, and the concrete manufacture method of shallow channel isolation area comprises the steps:
Step 11, on a semiconductor substrate 100 thermal oxide growth isolating oxide layer 101; with protection active area follow-up remove silicon nitride layer during stain from chemistry; and as the stress-buffer layer between silicon nitride layer and silicon substrate, described Semiconductor substrate is silicon substrate；
Step 12, in the surface deposited silicon nitride layer 102 of described isolating oxide layer 101；Wherein, depositing the silicon nitride layer obtained in this step is one layer of firm mask material；
Step 13, the etching of shallow trench: be sequentially etched silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100, form groove in described Semiconductor substrate 100；
Step 14, the growth of trench liner silicon oxide 103, at one layer of liner oxidation silicon 103 of trench interiors superficial growth, this liner oxidation silicon 103 interfacial characteristics between the oxide improving Semiconductor substrate and follow-up filling；
Step 15, trench oxide 104 are filled and are polished, the method using chemical gaseous phase deposition, and then fill oxide in groove carries out the polishing of oxide；Wherein, deposit the silicon nitride layer obtained in step 12, active area can be protected during performing this step, serve as the barrier material of polishing, prevent the excessive polishing of oxide；
Step 16, remove described silicon nitride layer 102.
According to foregoing description, as shown in Figure 1a, the structural representation that step 16 is formed is as shown in Figure 1 b for the structural representation that step 11 to 15 is formed.Follow-up active region between shallow channel isolation area forms MOS device.Specifically, at Semiconductor substrate 100 surface successively growth interface layer (not shown), high-k gate oxide 105, protective layer (not shown) and polysilicon layer 106, as illustrated in figure 1 c.Wherein, boundary layer is very thin, generally silicon oxide layer, or silicon oxynitride layer.High-k gate oxide 105 can be hafnium silicate, hafnium silicon oxygen nitrogen compound or hafnium oxide etc., and dielectric constant is typically greater than 15.Protective layer can be titanium nitride (TiN) or tantalum nitride (TaN) or the lamination of both combinations.Because ultimately form is metal gate electrode, replacement gate can be substituted by metal gate electrode, say, that replacement gate is finally non-existent, so the material of grid can have multiple as an alternative, in the present embodiment, the material of replacement gate is polysilicon.
It should be noted that prior art fill oxide in groove, the method typically using aumospheric pressure cvd (APCVD), tetraethyl orthosilicate (TEOS) and ozone (O3) reaction formation silicon oxide, the advantage of this method is the groove for high depth-to-width ratio, there is excellent covering filling capacity, but the silicon oxide layer that this deposition process obtains, ratio is more loose, film relatively porous, in an environment of high temperature, oxygen free in film is easy to be diffused in high-k gate oxide or boundary layer, and hafnium element activity in high-k gate oxide is stronger, poor to the controlling of oxygen, so being easy to make the equivalent oxide thickness (EOT) of high-k gate oxide become big, EOT is the least, mean that MOS device performance is the best, the density of the silicon oxide layer filled in the most how increasing shallow channel isolation area, prevent oxygen therein diffusion from becoming the problem paid close attention in the industry.
Summary of the invention
In view of this, the present invention provides a kind of method forming shallow channel isolation area, it is possible to avoid the equivalent oxide thickness of high-k gate oxide to increase.
The technical scheme is that and be achieved in that:
A kind of method forming shallow channel isolation area, described shallow channel isolation area was formed before high-k gate oxide, and the method includes:
Sequentially form isolating oxide layer and silicon nitride layer on a semiconductor substrate；
It is sequentially etched silicon nitride layer, isolating oxide layer and Semiconductor substrate, in described Semiconductor substrate, forms groove；
At one layer of liner oxidation silicon of described trench interiors superficial growth；
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer；
It is characterized in that, carrying out filling of oxide in groove and use aumospheric pressure cvd APCVD form silicon oxide layer and increase the method that silicon oxide layer density combines, repeatedly circulation is carried out.
The method increasing silicon oxide layer density includes: be passed through nitrogen, or the gas Han carbons, or argon, or the combination in any of three kinds of gases at deposition reaction intracavity.
The time being passed through every kind of gas at deposition reaction intracavity is 5～25 seconds.
When being passed through gas, deposition reaction chamber power is 50～500 watts.
It is 50～1000 sccm that deposition reaction intracavity is passed through the flow of every kind of gas.
Aumospheric pressure cvd uses tetraethyl orthosilicate and ozone reaction to form silicon oxide.
Can be seen that from such scheme, the filling of shallow channel isolation area of the present invention inner oxide has deposited several times, and after depositing every time, all oxide layers to deposition carry out increasing the process of film density, so, it is possible to prevent oxygen to diffuse in high-k gate oxide, improves the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 c is the structural representation that prior art forms the detailed process of shallow channel isolation area and follow-up active region formation high-k gate oxide between shallow channel isolation area.
Fig. 2 is the schematic flow sheet of shallow channel isolation area of the present invention manufacture method.
Fig. 2 a to 2e is the structural representation that the present invention forms shallow channel isolation area detailed process.
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearer, develop simultaneously embodiment referring to the drawings, is described in further detail the present invention.
The present invention is before making high-k gate oxide, and the concrete manufacturing process schematic diagram of shallow channel isolation area refers to Fig. 2 a to Fig. 2 e, and the schematic flow sheet of concrete manufacture method is as in figure 2 it is shown, comprise the steps:
Step 21, sequentially form isolating oxide layer 101 and silicon nitride layer 102 on a semiconductor substrate 100；
Specifically, thermal oxide growth isolating oxide layer 101 on a semiconductor substrate 100, with protect active area follow-up remove silicon nitride layer during stain from chemistry, and as the stress-buffer layer between silicon nitride layer and silicon substrate；Then in the surface deposited silicon nitride layer 102 of described isolating oxide layer 101；Wherein, depositing the silicon nitride layer obtained in this step is one layer of firm mask material；
Step 22, the etching of shallow trench: be sequentially etched silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100, form groove in described Semiconductor substrate 100；
Step 23, the growth of trench liner silicon oxide 103, at one layer of liner oxidation silicon 103 of trench interiors superficial growth, this liner oxidation silicon 103 interfacial characteristics between the oxide improving Semiconductor substrate and follow-up filling；
The structural representation formed according to step 21 to step 23 is as shown in Figure 2 a.
Step 24, the filling carrying out oxide in groove and polishing, form shallow channel isolation area；
Wherein, carrying out filling of oxide and use aumospheric pressure cvd form silicon oxide layer and increase the method that silicon oxide layer density combines in groove, repeatedly circulation is carried out.General cycle-index is not less than 2 times.The method increasing silicon oxide layer density has multiple, Ke Yiwei: be passed through nitrogen, or the gas Han carbons, or argon, or the combination in any of three kinds of gases at deposition reaction intracavity.Specifically, the combination in any of three kinds of gases refers to be passed through various gas successively, and every kind of gas acts on the oxide surface scheduled time.The embodiment of the present invention illustrates as a example by 2 circulations.
Step 241, employing aumospheric pressure cvd method carry out silicon oxide layer deposition for the first time, form the first silicon oxide layer 201, as shown in Figure 2 b；
In the embodiment of the present invention, the filling thickness of oxide is 6000 angstroms altogether, then silicon oxide layer deposit thickness is about 3000 angstroms for the first time.
Step 242, it is passed through nitrogen at deposition reaction intracavity, then passes to argon and carry out increasing the process of silicon oxide layer density；
Wherein, the purpose being passed through nitrogen at deposition reaction intracavity is, oxygen free when being deposited by first time silicon oxide layer, combines with nitrogen, is fixed in the semiconductor substrate by free oxygen, and anti-block diffuses in high-k gate oxide.The purpose being passed through argon is, is increased the density of silicon oxide layer deposited for the first time by the method for physical bombardment.Here, being passed through flow 50～1000 sccm of nitrogen, arranging reaction chamber power is 50～500 watts, and the time of being passed through is 5～25 seconds；After the silicon oxide layer of nitrogen with deposition for the first time fully acts on, then being passed through argon, be passed through flow 50～1000 sccm of argon, arranging reaction chamber power is 50～500 watts, and the time of being passed through is 5～25 seconds.
Step 243, employing aumospheric pressure cvd method carry out second time silicon oxide layer deposition, form the second silicon oxide layer 202, as shown in Figure 2 c；
In the embodiment of the present invention, the filling thickness of oxide is 6000 angstroms altogether, then silicon oxide layer deposit thickness is also about 3000 angstroms for the second time.
Step 244, deposition reaction intracavity be passed through argon carry out increase silicon oxide layer density process；
In like manner, being passed through flow 50～1000 sccm of argon, arranging reaction chamber power is 50～500 watts, and the time of being passed through is 5～25 seconds.
Step 245, in groove fill oxide be polished, as shown in Figure 2 d.Wherein, step 21 deposits the silicon nitride layer obtained, active area can be protected during performing this step, serve as the barrier material of polishing, prevent the excessive polishing of oxide；
Step 25, remove described silicon nitride layer 102, as shown in Figure 2 e.
So far, embodiment of the present invention shallow channel isolation area has been formed.
The filling of above-described embodiment oxide deposits at twice, and uses nitrogen and argon to carry out increasing the process of film density after the first filling successively, and second time uses argon to carry out the process of increase film density after filling.This is lifted one way in which, and the most multiple implementation, the present invention includes but not limited to this.Such as, the filling of oxide is divided into more than twice deposition, can individually use nitrogen, or the gas Han carbons every time, or argon processes after filling.Wherein, can be the arbitrarily gas Han carbons such as methane, ethylene, fluoroform containing carbons gas, its object is to, oxygen free when first time silicon oxide layer is deposited, combine with this gas Han carbons, being fixed in the semiconductor substrate by free oxygen, anti-block diffuses in high-k gate oxide.
To sum up, the method forming shallow channel isolation area by the present invention, add the packed density of oxide, the most do not have free oxygen to be diffused in the high-k gate oxide being subsequently formed, thus avoid the equivalent oxide thickness of high-k gate oxide to increase, improve the performance of semiconductor device.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, within should be included in the scope of protection of the invention.
Claims (5)
1. the method forming shallow channel isolation area, described shallow channel isolation area was formed before high-k gate oxide, and the method includes:
Sequentially form isolating oxide layer and silicon nitride layer on a semiconductor substrate；
It is sequentially etched silicon nitride layer, isolating oxide layer and Semiconductor substrate, in described Semiconductor substrate, forms groove；
At one layer of liner oxidation silicon of described trench interiors superficial growth；
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer；
It is characterized in that, carrying out filling of oxide in groove and use aumospheric pressure cvd APCVD form silicon oxide layer and increase the method that silicon oxide layer density combines, repeatedly circulation is carried out；
Wherein, the method increasing silicon oxide layer density includes: be passed through nitrogen, or the gas Han carbons, or argon, or the combination in any of three kinds of gases at deposition reaction intracavity.
2. the method for claim 1, it is characterised in that the time being passed through every kind of gas at deposition reaction intracavity is 5～25 seconds.
3. method as claimed in claim 2, it is characterised in that when being passed through gas, deposition reaction chamber power is 50～500 watts.
4. method as claimed in claim 3, it is characterised in that it is 50～1000 sccm that deposition reaction intracavity is passed through the flow of every kind of gas.
5. the method for claim 1, it is characterised in that aumospheric pressure cvd uses tetraethyl orthosilicate and ozone reaction to form silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261968.0A CN103579076B (en) | 2012-07-26 | 2012-07-26 | The method forming shallow channel isolation area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261968.0A CN103579076B (en) | 2012-07-26 | 2012-07-26 | The method forming shallow channel isolation area |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579076A CN103579076A (en) | 2014-02-12 |
| CN103579076B true CN103579076B (en) | 2016-08-03 |
Family
ID=50050566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210261968.0A Active CN103579076B (en) | 2012-07-26 | 2012-07-26 | The method forming shallow channel isolation area |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103579076B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9349631B2 (en) * | 2014-10-02 | 2016-05-24 | Globalfoundries Inc. | Method for defining an isolation region(s) of a semiconductor structure |
| CN105551962B (en) * | 2015-12-22 | 2018-10-26 | 上海华虹宏力半导体制造有限公司 | Sub-atmospheric pressure non-impurity-doped silica glass film build method |
| CN112864007B (en) * | 2019-11-28 | 2022-04-12 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079391A (en) * | 2006-05-26 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
| CN102487032A (en) * | 2010-12-02 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Method for forming shallow-trench isolating structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7229896B2 (en) * | 2005-08-03 | 2007-06-12 | United Microelectronics Corp. | STI process for eliminating silicon nitride liner induced defects |
| KR100677998B1 (en) * | 2005-09-30 | 2007-02-02 | 동부일렉트로닉스 주식회사 | Method for manufacturing shallow trench isolation layer of the semiconductor device |
-
2012
- 2012-07-26 CN CN201210261968.0A patent/CN103579076B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079391A (en) * | 2006-05-26 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
| CN102487032A (en) * | 2010-12-02 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Method for forming shallow-trench isolating structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579076A (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8772168B2 (en) | Formation of the dielectric cap layer for a replacement gate structure | |
| CN102347362B (en) | Semiconductor device with metal gate and method of manufacturing the same | |
| TWI446522B (en) | Semiconductor device and method for manufacturing the same | |
| US8309448B2 (en) | Method for forming buried word line in semiconductor device | |
| KR102406971B1 (en) | Semiconductor devices including capacitors and methods of manufacturing the same | |
| US20150132938A1 (en) | Methods and Systems for Forming Reliable Gate Stack on Semiconductors | |
| KR20140037983A (en) | Method of manufacturing for semiconductor device using expandable material | |
| US8987804B2 (en) | Nonvolatile semiconductor memory device and method of fabricating the same | |
| CN103390556A (en) | Semiconductor device manufacturing method | |
| CN103579076B (en) | The method forming shallow channel isolation area | |
| CN107305846A (en) | A kind of semiconductor devices and preparation method thereof | |
| US20170309491A1 (en) | Method of forming tungsten film and method of fabricating semiconductor device using the same | |
| KR20120059557A (en) | Film-forming method, semiconductor element manufacturing method, insulating film and semiconductor element | |
| US8008728B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| KR20090019131A (en) | Method of forming a dielectric layer in semiconductor memory device | |
| CN107689393B (en) | Semiconductor device and manufacturing method thereof | |
| CN102569049B (en) | Manufacture method of metal grid electrode | |
| CN110211916B (en) | Method for manufacturing shallow trench isolation structure | |
| CN103456614A (en) | Manufacturing method for semiconductor device with high-K metal gate | |
| CN112447497A (en) | Oxide layer forming method, semiconductor device manufacturing method and semiconductor device | |
| CN102005379A (en) | Method for improving reliability of gate oxygen at the corner of trench gate | |
| TWI828907B (en) | Semiconductor process | |
| KR20110109726A (en) | Method for fabricating buried gate in semiconductor device | |
| KR20080001269A (en) | Semiconductor device having a isolations and method for forming thereof | |
| KR100863413B1 (en) | Method of manufacturing a flash memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |