CN101924030B - Method for improving performance of high-k gate dielectric on high-resistance SOI substrate - Google Patents

Method for improving performance of high-k gate dielectric on high-resistance SOI substrate Download PDF

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CN101924030B
CN101924030B CN2010102316392A CN201010231639A CN101924030B CN 101924030 B CN101924030 B CN 101924030B CN 2010102316392 A CN2010102316392 A CN 2010102316392A CN 201010231639 A CN201010231639 A CN 201010231639A CN 101924030 B CN101924030 B CN 101924030B
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film
soi substrate
gate dielectric
hfo
improving performance
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CN101924030A (en
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程新红
何大伟
王中健
徐大伟
宋朝瑞
俞跃辉
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Shanghai Institute of Microsystem and Information Technology of CAS
Shanghai Simgui Technology Co Ltd
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Shanghai Institute of Microsystem and Information Technology of CAS
Shanghai Simgui Technology Co Ltd
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Abstract

The invention discloses a method for improving the performance of a high-k gate dielectric on a high-resistance silicon-on-insulator (SOI) substrate. The method comprises the following steps of: 1, pre-processing the high-resistance SOI substrate and packaging the pre-processed substrate in a thin-film deposition chamber; 2, growing an Al2O3 thin film with the thickness of no more than 1nm on the upper surface of the high-resistance SOI substrate in situ; 3, growing a HfO2 thin film with the thickness of not greater than 30nm on the Al2O3 thin film in situ; 4, depositing an oxygen-absorbing metal cap layer on the HfO2 thin film in situ; and 5, performing annealing. The method suppresses the growth of an interface layer, contributes to thinning equivalent gate oxide of the high-k gate dielectric, increases the crystallization temperature of the high-k gate dielectric, reduces the thickness of the interface layer and the density of interfacial state and improves the electric property of the high-k gate dielectric on the high-resistance SOI.

Description

A kind of method of improving performance of high-k gate dielectric on high-resistance SOI substrate
Technical field
The invention belongs to microelectronic, relate to a kind of method of improving performance of high-k gate dielectric on high-resistance SOI substrate.
Background technology
Fast development along with microelectric technique; The research and development of high-performance, high integration, multi-functional IC are more and more harsher to the requirement of material; Silicon on the insulator (Silicon on insulator; SOI) material is the novel silicon base integrated circuit material, is described as " the novel silicon base integrated circuit technique of 21 century ".When adopting high resistant SOI (HRSOI) substrate; Can cut off substrate and inject noise channel; Reduce capacitive coupling, reduce the radio frequency loss relevant, and then improve active device and passive device performance with substrate; Especially the HRSOI substrate makes them have higher, more stable performance during operation to adapt to polytechnic variation and disturbance effect in the advantage that also can further give prominence to the analog/digital hybrid circuit when synthetic with radio circuit, voltage controlled oscillator and low noise amplifier etc.
According to " Moore's Law ", the number of transistors on the single-chip should double in per 2 years.But, as the traditional material of electronic devices and components gate medium---SiO 2Attenuate its inherent physics limit is arranged, it is more serious to surpass problems such as tunnelling leakage current that this limit will cause device, needle pore defect, performance failure.Therefore, some integrated circuit researchs and maker have begun to explore, and in the middle of integrated circuit, adopt certain substituted SiO 2The high-dielectric-coefficient grid medium material, developed the high k process technique of 45 nanometers like Intel Company.
HfO 2Film has comparatively ideal dielectric constant, energy gap and leads valence band offset, be generally acknowledge can substitute SiO 2High-k gate dielectric.But HfO 2The crystallization temperature of film is usually less than 700 ℃, causes problems such as electric leakage increase, interface state density increase, electric property poor repeatability to occur; In addition, Si and O element are at HfO 2Diffusion rate in the film is very high, in interface and film, is very easy to form hafnium base acidulants and hafnium base silicate, and then reduces HfO 2Film performance.
Various defect concentrations are much larger than body silicon in the top layer silicon of the HRSOI substrate of injection oxygen isolation technology preparation, and HfO grows on the HRSOI substrate 2Can cause a large amount of diffusions of hypertrophy and the O and the Si of boundary layer in the thin-film process, seriously restrict the development that HRSOI goes up the high-k gate dielectric technology.
Summary of the invention
Technical problem to be solved by this invention is: a kind of method of improving performance of high-k gate dielectric on high-resistance SOI substrate is provided.
For solving the problems of the technologies described above, the present invention adopts following technical scheme.
A kind of method of improving performance of high-k gate dielectric on high-resistance SOI substrate said method comprising the steps of:
Step 1 is carried out preliminary treatment with high resistant SOI substrate, in the thin film deposition chamber of packing into then;
Step 2 is not more than the Al of 1nm at the upper surface growth in situ thickness of high resistant SOI substrate 2O 3Film;
Step 3 is at said Al 2O 3Growth in situ thickness is not more than the HfO of 30nm on the film 2Film;
Step 4 is at said HfO 2In-situ deposition oxygen uptake metal nut cap layer on the film;
Step 5, annealing in process.
As a kind of preferred version of the present invention, said thin film deposition chamber is the ultra vacuum electron beam evaporation chamber.
As another kind of preferred version of the present invention, in the step 1, said pretreated concrete grammar is: utilize standard semiconductor technology that said high resistant SOI substrate is cleaned, the high resistant SOI substrate after will cleaning then is placed among the HF of dilution and soaked 1 minute.
As another preferred version of the present invention, in the step 2, said Al 2O 3The detailed growing method of film is: after said high resistant SOI substrate is heated to 300 ℃, through ultra vacuum electron beam evaporation Al 2O 3Ceramic target is at the growth in situ Al of said high resistant SOI substrate 2O 3Film.
As another preferred version of the present invention, in the step 3, said HfO 2The detailed growing method of film is: through ultra vacuum electron beam evaporation HfO 2Ceramic target is at said Al 2O 3The original position of film forms HfO 2Film, said HfO 2Film is amorphous HfO 2The high-k gate dielectric film.
As another preferred version of the present invention, in the step 4, the detailed growing method of said oxygen uptake metal nut cap layer is: through the electron beam evaporation metallic target, at said HfO 2The original position of film forms oxygen uptake metal nut cap layer.
As another preferred version of the present invention, said metallic target is the Ti metallic target, and said oxygen uptake metal nut cap layer is a Ti metal nut cap layer.
As another preferred version of the present invention, in the step 4, after said oxygen uptake metal nut cap layer forms, utilize and select wet method to carve decorations not the oxygen uptake metal and reflection product of reflection.
As another preferred version of the present invention, in the step 5, the method for said annealing in process is: at N 2Carry out 700 ℃ of quick thermal annealing process of 3 minutes in the atmosphere.
As another preferred version of the present invention, said Al 2O 3Film and HfO 2The growth for Thin Film temperature all remains on 300 ℃.
Beneficial effect of the present invention is: the present invention has suppressed the boundary layer growth; The attenuate that helps high-k gate dielectric equivalence gate oxide thickness; Improve the crystallization temperature of high-k gate dielectric, reduced interfacial layer thickness and interface state density, improved the upward electric property of high-k gate dielectric of high resistant SOI.
Description of drawings
Fig. 1 is for there being Al 2O 3The high-k gate dielectric on barrier layer and EDX (EnergyDispersive X-Ray Fluoresence Spectrometer) the element distribution schematic diagram that does not have the high-k gate dielectric on barrier layer;
Fig. 2 is for there being Al 2O 3The HfO on barrier layer 2Gate medium and the HfO that does not have the barrier layer 2The electric property of gate medium is sketch map relatively;
Fig. 3 measures curve and matched curve for the high-resolution X ray reflection rate of annealing specimen and original position sample under the protection of Ti cap, and block diagram is a model of fit;
Fig. 4 is the electrical performance testing figure of sample after growth in situ sample and the following annealing in process of oxygen uptake metal nut cap layer protection;
Fig. 5 is the flow chart that improves the method for performance of high-k gate dielectric on high-resistance SOI substrate of the present invention.
Embodiment
Do further explain below in conjunction with the accompanying drawing specific embodiments of the invention.
Embodiment one
Present embodiment provides a kind of method of improving performance of high-k gate dielectric on high-resistance SOI substrate, in order to suppress HRSOI and HfO 2Between boundary layer growth and control O spread with Si.The HRSOI material is the material that comprises top layer silicon, buried oxidation layer, substrate silicon three-decker, and middle buried oxidation layer (BOX) all is that direct physics contacts with top layer silicon and substrate silicon, and buried oxidation layer plays the effect of electric isolation top layer silicon and substrate silicon.Silicon thickness on the insulating thick film body is not less than 200nm, barrier layer Al 2O 3Thickness is not more than 1nm, and Annealing Protection atmosphere is high-purity N 2, the after annealing temperature is not higher than 700 ℃.Present embodiment mainly is through at HRSOI substrate and HfO 2Insert the Al of Heat stability is good between the film 2O 3The barrier layer (is claimed Al again 2O 3Film) or at HfO 2Original position covers the realization of oxygen uptake metal nut cap layer on the film.
[Al 2O 3Barrier layer]
At first utilize the standard semiconductor cleaning to clean the HRSOI substrate, in the HF of dilution, soaked 1 minute, in the thin film deposition chamber of packing into then.
The HRSOI underlayer temperature remains on 300 ℃, and growth in situ thickness is less than the Al of 1nm 2O 3Film, HfO then grows 2Film.HfO 2The growth for Thin Film temperature remains on 300 ℃, helps the growth of homogeneous film, improves the adhesion strength between film and the substrate simultaneously.Al 2O 3Thickness cross conference restriction high-k gate dielectric stack equivalent gate oxide thickness dwindle the too small uniformity and inhibition HfO that can influence film 2The effect of crystallization.
Last film is at N 2Carry out 700 ℃ of quick thermal annealing process of 3 minutes under the atmosphere, make film more even, reduce defect concentration.
Al 2O 3The barrier layer can not only suppress the further growth of subsequent anneal process median surface layer, and can reduce O and Si elemental diffusion rate.
[oxygen uptake metal nut cap layer]
Through the membrane deposition method HfO that on the HRSOI substrate, grows 2After the film, original position forms oxygen uptake metallic film cap, and underlayer temperature remains on 300 ℃.Oxygen uptake metal nut cap layer is crossed and thin can't be played the purpose that stops the O diffusion, blocked up cleaning after being unfavorable for annealing, and oxygen uptake metal nut cap layer thickness should be not more than 30nm.
The HfO that will have oxygen uptake metal nut cap layer 2Stack architecture is at N 2Carry out 700 ℃ of quick thermal annealing process of 3 minutes in the atmosphere, utilize then and select wet method to carve unreacted oxygen uptake metal of decorations and product.
The Ti metallic film can stop the interior oxygen element of annealing working chamber to be diffused into HfO 2In the film, and then suppress the boundary layer growth.
Embodiment two
Present embodiment has been described embodiment one described Al 2O 3The detailed growth course on barrier layer, this process may further comprise the steps:
(1) chooses the HRSOI sheet of resistivity, be cut into some small pieces after cleaning with semiconductor standard processes, in the HF acid of dilution, soak and removed the surperficial SiO of HRSOI sheet in 1 minute greater than the notes oxygen partition method formation of 1000 Ω cm 2, put into the ultra vacuum electron beam evaporation chamber;
(2) after the HRSOI sheet is heated to 300 ℃, through electron beam evaporation Al 2O 3Ceramic target, the Al of growth in situ 1nm 2O 3Film;
(3) electron beam evaporation HfO 2Ceramic target, the amorphous HfO of formation 5nm 2The high-k gate dielectric film;
(4) at N 2The following 700 ℃ of short annealings of atmosphere protection 3 minutes.
The described Al of present embodiment 2O 3HfO has been improved on the barrier layer 2Crystallization temperature, suppressed the growth of boundary layer, improved the interface smoothness of HRSOI and high-k gate dielectric.Can find out Al by Fig. 1 2O 3The barrier layer has suppressed the Si elemental diffusion, has controlled the formation of silicate with the thing that silicifies.Can find out to have Al by Fig. 2 2O 3The sample permittivity on barrier layer improves relatively, and the flat band voltage relative displacement is little, and this explanation has Al 2O 3The interfacial layer thickness of the sample on barrier layer (with BL) reduces, and the interface state density reduction, also explains at HRSOI substrate and HfO simultaneously 2Insert one deck Al between the film 2O 3The method on barrier layer helps improving the electric property of gate medium.The abscissa of Fig. 2 is gate bias voltage (Gate bias), and ordinate is electric capacity (Capacitance).
Embodiment three
Present embodiment has been described the detailed growth course of embodiment one described oxygen uptake metal nut cap layer, and this process may further comprise the steps:
(1) chooses the HRSOI sheet of resistivity, be cut into some small pieces after cleaning with semiconductor standard processes, in the HF acid of dilution, soak and removed surperficial SiO in 1 minute greater than the notes oxygen partition method formation of 1000 Ω cm 2, put into the ultra vacuum electron beam evaporation chamber;
(2) the HRSOI sheet is heated to 300 ℃, through electron beam evaporation HfO 2Ceramic target, the amorphous HfO of formation 5nm 2The high-k gate dielectric film, electron beam evaporation Ti metallic target then, original position forms the Ti metal nut cap layer of 30nm;
(3) then at N 2The following 700 ℃ of short annealings of atmosphere protection 3 minutes utilize the wet method selective etching to fall unreacted Ti, product TiN and TiO 2
Fig. 3 has shown the high-resolution X ray reflection rate measurement curve and the matched curve of following annealing specimen (annealed) of oxygen uptake metal nut cap layer protection and original position sample (as-deposited), and block diagram is a model of fit.Can be known that by Fig. 3 the sample of growth in situ has the thick boundary layer of 2nm, this boundary layer is respectively by 0.5nm HfAlSiO and 1.5nm Si x(SiO2) 1-x(x＜2) are formed.The boundary layer of the sample of annealing down in oxygen uptake metal nut cap layer protection is only by the SiO of 1.0nm 2Form.This explanation oxygen uptake metal nut cap layer has suppressed not only that extraneous oxygen element makes boundary layer decompose to the inner diffusion of film simultaneously in the annealing process, discharges oxygen element, forms and is similar to SiO 2The structure of/Si ideal interface.
Fig. 4 has shown the electric property of following annealing specimen of oxygen uptake metal nut cap layer protection and original position sample; Wherein figure (a) expression capacitance curve is schemed (b) expression leakage current curves.Maximum accumulation capacitance by the visible annealing of Fig. 4 back sample increases, and curve is precipitous between accumulation and the depletion region, and leakage current reduces.The equivalent gate oxide thickness of this explanation gate medium reduces, and gate dielectric membrane is fine and close more, and interface state density reduces, and this is consistent with the result of Fig. 3, and this explains at HfO 2In-situ deposition oxygen uptake metal nut cap layer helps improving the thermal stability and the electric property of gate medium on the gate dielectric membrane.
The method of the invention has been improved the electric property of high-k gate dielectric, and it is embodied in: suppressed the boundary layer growth, helped the attenuate of high-k gate dielectric equivalence gate oxide thickness.There is not Al 2O 3The sample on barrier layer, interfacial layer thickness be greater than 3nm, and in uneven thickness; And Al is arranged 2O 3The sample on barrier layer, interfacial layer thickness obviously reduces, and be controlled at about 1nm, and thickness is even.
The method of the invention has improved the thermal stability of high-k gate dielectric, and it is embodied in: the crystallization temperature that has improved high-k gate dielectric.Al is arranged 2O 3The HfO on barrier layer 2Film remains amorphous after 700 ℃ of high annealings, this helps reducing leakage current; Suppressed the growth of hafnium base acidulants and hafnium base silicate, made boundary layer mainly by the SiO of fabricating low-defect-density 2Layer constitutes; Interface roughness between HRSOI and the high K medium film obviously reduces, and the carrier mobility that this helps improving semiconductor device reduces interface state density, and then reduces leakage current and flat band voltage drift, improves HfO 2The permittivity of gate medium.
The present invention adopts the ultra vacuum electron beam evaporation method to realize barrier layer, high-k gate dielectric layer and oxygen uptake metal nut cap layer growth in situ, and the technology of having avoided adopting the several different methods preparation to bring in the traditional silicon substrate is polluted and complexity.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of the embodiment that is disclosed and change are possible, and the replacement of embodiment is known with the various parts of equivalence for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other forms, structure, layout, ratio, and realize with other elements, material and parts.

Claims (10)

1. a method of improving performance of high-k gate dielectric on high-resistance SOI substrate is characterized in that, said method comprising the steps of:
Step 1 is carried out preliminary treatment with high resistant SOI substrate, in the thin film deposition chamber of packing into then;
Step 2 is not more than the Al of 1nm at the upper surface growth in situ thickness of high resistant SOI substrate 2O 3Film;
Step 3 is at said Al 2O 3Growth in situ thickness is not more than the HfO of 30nm on the film 2Film;
Step 4 is at said HfO 2In-situ deposition oxygen uptake metal nut cap layer on the film;
Step 5, annealing in process.
2. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 1 is characterized in that: said thin film deposition chamber is the ultra vacuum electron beam evaporation chamber.
3. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 2; It is characterized in that: in the step 1; Said pretreated concrete grammar is: utilize standard semiconductor technology that said high resistant SOI substrate is cleaned, the high resistant SOI substrate after will cleaning then is placed among the HF of dilution and soaked 1 minute.
4. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 2 is characterized in that: in the step 2, and said Al 2O 3The detailed growing method of film is: after said high resistant SOI substrate is heated to 300 ℃, through ultra vacuum electron beam evaporation Al 2O 3Ceramic target is at the growth in situ Al of said high resistant SOI substrate 2O 3Film.
5. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 2 is characterized in that: in the step 3, and said HfO 2The detailed growing method of film is: through ultra vacuum electron beam evaporation HfO 2Ceramic target is at said Al 2O 3The original position of film forms HfO 2Film, said HfO 2Film is amorphous HfO 2The high-k gate dielectric film.
6. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 2 is characterized in that: in the step 4, the detailed growing method of said oxygen uptake metal nut cap layer is: through the electron beam evaporation metallic target, at said HfO 2The original position of film forms oxygen uptake metal nut cap layer.
7. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 6 is characterized in that: said metallic target is the Ti metallic target, and said oxygen uptake metal nut cap layer is a Ti metal nut cap layer.
8. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 1 is characterized in that: in the step 4, after said oxygen uptake metal nut cap layer forms, utilize and select wet method to carve decorations not the oxygen uptake metal and reflection product of reflection.
9. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 1 is characterized in that: in the step 5, the method for said annealing in process is: at N 2Carry out 700 ℃ of quick thermal annealing process of 3 minutes in the atmosphere.
10. the method for improving performance of high-k gate dielectric on high-resistance SOI substrate according to claim 1 is characterized in that: said Al 2O 3Film and HfO 2The growth for Thin Film temperature all remains on 300 ℃.
CN2010102316392A 2010-07-20 2010-07-20 Method for improving performance of high-k gate dielectric on high-resistance SOI substrate Expired - Fee Related CN101924030B (en)

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CN102820209B (en) * 2011-06-08 2015-03-25 中国科学院上海微系统与信息技术研究所 Preparation method of on-insulator material of high K dielectric buried layer
CN103390547B (en) * 2012-05-08 2016-05-25 中芯国际集成电路制造(上海)有限公司 There is the method for forming semiconductor structure of metal gate electrode layer
KR102099881B1 (en) * 2013-09-03 2020-05-15 삼성전자 주식회사 Semiconductor device and method of fabricating the same
CN111430228B (en) * 2020-04-26 2023-03-28 上海师范大学 Preparation method of dielectric film with ultrahigh dielectric constant
CN112420502A (en) * 2020-11-18 2021-02-26 上海华力集成电路制造有限公司 Method for manufacturing high-dielectric-constant metal gate MOS transistor

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